2020 International Conference on Green and Human Information Technology (ICGHIT)

Prefix-based Multi-Pattern Matching on FPGA

Hoang-Gia Vu Yen Hoang Thi

Department of Radio-Electronics Engineering Department of Radio-Electronics Engineering
Le Quy Don Technical University Le Quy Don Technical University
Hanoi, Vietnam Hanoi, Vietnam
Email: [email protected] Email: [email protected]

Abstract—Multi-pattern matching refers to the search for

multiple patterns in a given text at the same time. This
matching on FPGA is expected to scale with the number of
patterns in hardware consumption. In this paper, we propose
a matching architecture that compares the prefixes of multiple
patterns with the prefix of the matching window in parallel.
The comparison will continue with the body of each pattern
if the corresponding prefix is matched. This architecture is
called the prefix-based multi-pattern matching architecture.
Our implementation on FPGA shows that the proposed match-
ing architecture achieves much higher performance than the
implementation on CPU, while the hardware cost is low.
Keywords-multi-pattern matching; FPGA; prefix-based;

I. I NTRODUCTION
Multi-pattern matching is an important task in data min-
ing. The multi-pattern matching algorithm is employed to Figure 1. Prefix matching architecture
search multiple string patterns in a target text to find the
corresponding position of each pattern in the text. This Our main contributions in this work are the hardware
algorithm requires many comparisons for each matching architecture for multi-pattern matching on FPGA and the
window, thus achieving low performance in sequential- analysis of its hardware consumption and latency. We also
execution processors. Several works proposed algorithms for present the experimental results and address future work.
multi-pattern matching on CPU, such as hash-based multi-
pattern matching [1] and multi-string searching based on II. M ULTI - PATTERN M ATCHING A RCHITECTURE
improved prefix tree [2]. However, these algorithms also The multi-pattern matching architecture is divided into
require many comparisons, and the execution times also two parts. The first part is called the prefix matching part.
scale with the number of patterns. The second part is the body matching part. Before presenting
We believe that multi-pattern matching can be accelerated the two parts, we define several concepts as follows:
on FPGA by executing comparisons in parallel. However, • N is the number of patterns.
executing all comparisons in hardware consumes a large • Prefix of a string is a set of the first several characters
number of hardware resources when the number of patterns in the string. k is defined as the length of the prefix.
and the length of patterns increase. Yuichiro Utan [3] • Pattern body is the rest of a pattern after its prefix.
implemented comparisons on FPGA, but for approximate • Matching window is the text window in the target text
regular expression matching. Tomas Fukac [4] used a hash- that is matched with patterns. The matching window will
based pre-filter on FPGA to reduce the input traffic before slide from the beginning to the end of the text. We assume
matching in CPU. In this work, we implement the whole that all the patterns have the same length of L characters.
exact multi-pattern matching on FPGA. We propose to • Prefix window is the set of the first characters in the
compare only the prefix of each pattern with the prefix of matching window that has the same length as the prefixes -
the matching window. These comparisons are executed in k characters.
parallel. If a comparison is matched, the rest of the pattern • Body window is the rest of the matching window after
will be compared with the rest of the matching window. the prefix window. The length of the body window is L-k.
Otherwise, the matching window will be shifted to a new • Input bandwidth is the number of characters coming per
string for the next matching. clock cycles, defined as M.

978-1-7281-6295-9/20/$31.00 ©2020 IEEE 68

DOI 10.1109/ICGHIT49656.2020.00025
 Table I
E XECUTION TIME FOR DIFFERENT PLATFORMS

Platform 10 KB 100 KB 1 MB 10 MB 100 MB

Core i5 0.00393 0.02531 0.20580 1.90277 18.95482
Cortex-A9 0.01998 0.19713 3.34643 36.47776 367.99406
FPGA 0.00004 0.00026 0.00263 0.02628 0.26292

input bandwidth (M characters per clock cycle). In case that

a prefix window and a prefix are matched, the matching
window is stopped sliding for 3 clock cycles. The 3-clock-
cycle latency is caused by 2-clock-cycle latency of the
resolver and 1-clock-cycle latency of the pattern RAM and
comparators.
Figure 2. Body matching architecture IV. E VALUATION
We have designed the multi-pattern matching hardware
A. Prefix Matching Part presented in this paper with Verilog HDL and implemented
The prefix matching part includes circuits comparing each on Xilinx Zedboard using Vivado 2016.4. The matching
prefix and prefix windows. To meet the input bandwidth of hardware is combined with 3 direct memory access units
M characters, each prefix should be compared with M prefix (DMAs) and a thread-control unit to form an AXI4-based IP
windows 1, 2, ..., M. It is noted that prefix window i+1 is core. In this evaluation, we chose N = 16, k = 4, L = 36, M =
prefix window i sliding one character in the target text. The 8. The hardware consumption of the IP core consists of 3489
outputs of these comparators lead to a resolver to identify slice registers, 4537 LUTs as logic, 391 LUTs as memory,
which pattern is accessed. 3.5 Block RAM tiles. The maximum clock frequency is 160
MHz. The execution time (in seconds) of the matching task
B. Body Matching Part
when it runs on different platforms, such as CPU Intel Core
The body matching part consists of a resolver, a pattern i5, CPU ARM Cortex-A9, and FPGA (Zedboard), is showed
RAM, and comparators. The resolver is a sequential circuit in Table 1. The table shows that multi-pattern matching can
that has its output as the input address of the pattern RAM. achieve much higher performance on FPGA while scaling
The pattern RAM is a one-port RAM storing N pattern the text size, compared with the implementation on CPU.
bodies. The output of the pattern RAM is compared with M
body windows of the target text. These M body windows are V. C ONCLUSION
corresponding to M prefix windows in the prefix matching We have proposed a prefix-based multi-pattern matching
part. A pair of a prefix window and a body window forms architecture on FPGA. Compared with the software imple-
a matching window. mentation, the hardware architecture shows a much higher
efficiency in execution time, while its hardware cost is
III. A NALYSIS
low. In future work, we will evaluate the architecture while
A. Hardware Cost Analysis scaling the number of patterns and the length of patterns.
Assume that a 2-character comparator consumes c look-
R EFERENCES
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Since M matching windows are matched simultaneously
with patterns, the matching throughput is the same as the

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