BCSE305L – Embedded Systems Systems

MODULE - 3
ARCHITECTURE OF SPECIAL PURPOSE
COMPUTING SYSTEM

Dr. Sridhar Chandrasekaran

Assistant Professor (Senior)
VIT University, Chennai
BCSE305L, Dr. C. Sridhar Page 1
ATM, Handheld devices, Data Compressor, Image
Capturing Devices Architecture and Requirements,
Challenges Constraints of special purpose computing
system.

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 MICROCONTROLLER ARCHITECTURE
CLASSIFICATION OF MICROOCNTROLLERS

q BITS: (Size of the data that can be handled by microcontroller)

− 8-Bit: Ex: Intel 8031/8051, PIC1x and Motorola MC68HC11 families

− 16-Bit: Ex: 8051XA, PIC2x, Intel 8096 and MC68HC12 families

− 32-bit: Ex: ARM Cortex, Intel/Atmel 251 family, PIC3x

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 MICROCONTROLLER ARCHITECTURE
CLASSIFICATION OF MICROOCNTROLLERS

q MEMORY ARCHITECTURE:

− Harvard Memory Architecture: When a microcontroller has a

dissimilar memory address space for program & data memory
Ex: 8051, PIC, AVR based microcontroller families

− Von-Neumann Architecture: When a microcontroller has a

common memory address space for program & data memory
Ex: Motorola 68k, PowerPC based Microcontroller families

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 MICROCONTROLLER ARCHITECTURE
HARVARD VS VON-NEUMANN

MICROCONTROLLER
MICROCONTROLLER

PHERIPHERALS
PHERIPHERALS

Input Output
Input Output CPU
Devices CPU Devices
Devices Devices

MEMORY
(Program + Data) Program Data
Memory Memory

VON-NEUMANN ARCHITECTURE HARVARD ARCHITECTURE

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 MICROCONTROLLER ARCHITECTURE
CLASSIFICATION OF MICROOCNTROLLERS

q INSTRUCTION SET:
− CISC: Complex Instruction Set Computer
− Allow single (complex) instructions to perform numerous low-
level (simple) operations like a load from memory, arithmetic
operation, store into memory with multiple clock cycle
− MUL A, B : get the value of A and B from registers, compute
multiplication by repeated addition and store results back to
registers
Ex: Motorola 68000 (68K), 8051

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 MICROCONTROLLER ARCHITECTURE
CLASSIFICATION OF MICROOCNTROLLERS

q INSTRUCTION SET:
− RISC: Reduced Instruction set Computer
− reduce the instruction execution complexity by having
several simple instructions which achieve low-level operation
within a single clock cycle
− LDR for loading, ADD with loop count for multiplication then
STR for storing operations
Ex: AVR, PIC, ARM

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 MICROCONTROLLER ARCHITECTURE
CLASSIFICATION OF MICROOCNTROLLERS
q FAMILIES/ARCHITECTURE:
− MCS51: A microcontroller (MCU) series developed by Intel and optimized for
embedded control applications
− PIC: A family of microcontrollers made by Microchip Technology and used
in a wide variety of embedded systems
− AVR: A family of microcontrollers developed by Atmel (acquired by
Microchip in 2016) and majorly used by hobbyist and educational
embedded applications
− ARM: By combining the ARM microprocessor with RAM, ROM and other
peripherals in one single chip, ARM microcontrollers are made (LPC 11U24)
− OTHERS: MIPS, PowerPC, RISC-V, Motorola etc.,
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 MICROCONTROLLER ARCHITECTURE
MCS51- Features (8051)
Ø Instruction set Architecture : CISC
Ø Data bus size : 8-bit
Ø Address bus size : 16-bit
Ø Program memory (ROM) : 4 KB
Ø Data memory (RAM) : 128 bytes
Ø General purpose registers : 32 (each 8-bit in size)
Ø Program counter : 16-bit (PC)
Ø Data pointer : 16-bit (DPTR)
Ø Input/output ports : 4 (each 8-bit in size)
Ø Timers : 2 (T0 & T1)
Ø Interrupts : 5 (3 internal + 2 external)
Ø Serial port : 1 (8-bit & 9-bit mode)
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 8051- Architecture

8051 – Pin diagram

Ref. URL(From datasheet): http://ww1.microchip.com/downloads/en/DeviceDoc/doc0265.pdf

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 MICROCONTROLLER ARCHITECTURE
PIC – Features (16F877A)
Ø Instruction set Architecture : RISC
Ø Data bus size : 8-bit
Ø Address bus size : 14-bit
Ø Program memory (ROM) : 8 KB
Ø Data memory (RAM) : 368 bytes
Ø Data memory (EEPROM) : 258 bytes
Ø Input/output ports : 5 (A, B, C, D, E)
Ø Timers : 3 (Timer0, 1 & 2)
Ø Interrupts : 15
Ø ADC modules (10-bit) : 8 channels
Ø PWM modules :2
Ø Analog comparators :2
Ø Serial communication : MSSP, USART
Ø Parallel communication : PSP
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 PIC – Architecture (16F877A)

PIC 16F877A – Pin diagram

Ref. URL (from Datasheet): http://ww1.microchip.com/downloads/en/devicedoc/39582c.pdf

MODULE - 3 CSE3006 – EMBEDDED SYSTEM DESIGN 15

 MICROCONTROLLER ARCHITECTURE
AVR - Features (ATmega328P)
Ø Instruction set Architecture : RISC
Ø Data bus size : 8-bit
Ø Address bus size : 16-bit
Ø Program memory (ROM) : 32 KB
Ø Data memory (RAM) : 2 KB
Ø Data memory (EEPROM) : 1 KB
Ø Input/output ports : 3 (B, C, D)
Ø General purpose registers : 32 (each 8-bit in size)
Ø Timers : 3 (Timer0, 1 & 2)
Ø Interrupts : 26 (2 External)
Ø ADC modules (10-bit) : 6 channels
Ø PWM modules :6
Ø Analog comparators :1
Ø Watchdog timer :1
Ø Serial communication : SPI, USART, TWI(I2C)
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 AVR ATmega328P - Architecture

ATmega328P – Pin diagram

Ref. URL (From datasheet): http://ww1.microchip.com/downloads/en/DeviceDoc/ATmega48A-PA-88A-PA-168A-PA-328-P-DS-DS40002061A.pdf

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 MICROCONTROLLER ARCHITECTURE
ARM - Features (Cortex-M0)
Ø Instruction set Architecture : RISC
Ø Data bus size : 32-bit
Ø Address bus size : 32-bit
Ø Program memory (ROM) : 32 KB
Ø Data memory (RAM) : 10 KB
Ø Data memory (EEPROM) : 4 KB
Ø Boot ROM : 16 KB
Ø GPIO pins : 54
Ø General purpose registers : 32
Ø Timers :4
Ø Nested Vectored Interrupt : 24
Ø ADC modules (10-bit) : 8 channels
Ø Windowed Watchdog timer :1
Ø Integrated oscillators : 3 (system, Internal RC, Watchdog oscillator)
Ø Serial communication : USB 2.0, SSP, USART, I2C
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 ARM LPC 11U24 - Architecture

ARM LPC 11U24 – Pin diagram

Ref. URL (From datasheet): https://www.nxp.com/docs/en/data-sheet/LPC11U2X.pdf

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 EMBEDDED MEMORY
MEMEORY ORGANISATION

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 EMBEDDED MEMORY
MEMEORY ORGANISATION
q System Space – Exception Vectors

q Code Space – Stores the Instruction

q ROM Data Space – Stores the constants e.g. error messages

q Stack – Context Switching, grows downwards

q Free Memory – All Statically allocated variables

q Heap – All dynamically allocated variables

q I/O Space – Memory mapped I/O devices
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 EMBEDDED MEMORY
MEMORY CLASSIFICATION
1. Accessibility: Memory devices can provide Random Access,
Serial Access or Block Access.
§ Random Access memory - memory can be directly accessed by
specifying the address of the memory word. Ex: RAM, SDRAM,
NOR Flash.
§ Serial Access Memory - all the previous words (previous to the
word being accessed) need to be accessed, before accessing a
desired word. Ex: I2C PROM, SPI PROM
§ Block Access Memories - entire memory is sub-divided into small
blocks of memory. Each block can be randomly accessed, and
each word in a given block can be serially accessed. Ex: Hard
Disks, NAND flash
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 EMBEDDED MEMORY
MEMORY CLASSIFICATION
2. Persistence of Storage: Memory devices can provide Volatile
storage or a non-Volatile storage.
§ Non-Volatile storage - memory contents remain preserved
even after power shut down. Non-Volatile storage can be
used to store application code, and re-usable data.
Ex: Hard Disks, Flash (NOR & NAND) Memories, SD-MMC,
and ROM
§ Volatile memory - loses its contents, after power shut down.
Volatile memory can be used for all temporary storage.
Ex: RAM, SDRAM
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 EMBEDDED MEMORY
MEMORY CLASSIFICATION

3. Storage cells: Memory Device may employ electronic storage,

magnetic storage or optical storage.
§ RAM, SDRAM are examples of electronic storage.

§ Hard Disks are example of magnetic storage.

§ CDs are example of optical storage.

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 EMBEDDED MEMORY
MEMORY CLASSIFICATION

4. Storage Density & Cost : Storage Density (number of bits which

can be stored per unit area) is generally a good measure of cost.
Dense memories (like SDRAM) are much cheaper than their
counterparts (like SRAM).

5. Power Consumption: Low Power Consumption is highly

desirable in Battery Powered Embedded Systems. Such systems
generally employ memory devices which can operate at low
(and ultra-low) Voltage levels. Mobile SDRAMs are example of
low power memories.
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 EMBEDDED MEMORY

SRAM
RAM
DRAM

MASKED ROM

MEMORY ROM PROM

EPROM

EEPROM

HYBRID FLASH

NVRAM

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 EMBEDDED MEMORY
CHARACTERISTICS OF VARIOUS EMBEDDED MEMORY DEVICES
Type Volatile? Writeable? Erase Size Max Erase Cycles Cost Speed
SRAM Yes Yes Byte Unlimited Expensive Fast

DRAM Yes Yes Byte Unlimited Moderate Moderate

Masked ROM No No n/a n/a Inexpensive Fast

PROM No Once n/a n/a Moderate Fast

EPROM No Yes Entire Chip Limited Moderate Fast

EEPROM No Yes Byte Limited Expensive Fast to read, slow to erase/write

Flash No Yes Sector Limited Moderate Fast to read, slow to erase/write

NVRAM No Yes Byte Unlimited Expensive Fast

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Handheld devices
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 Selecting The Right Processor

MODULE - 3 CSE3006 – EMBEDDED SYSTEM DESIGN 40

 Selecting The Right Processor

q Is it available in a suitable implementation?

q What good is choosing the highest performing processor if the cost of

goods makes your product noncompetitive in the marketplace?

q Is the Processor Capable of Sufficient Performance?

q Processor must be able to do the job on time.

MODULE - 3 CSE3006 – EMBEDDED SYSTEM DESIGN 41

 Selecting The Right Processor

q Is the Processor Supported by an Appropriate Operating System?

q Porting the RTOS kernel to a new or different microprocessor

architecture and having it specifically optimized to take advantage of
the low-level performance features of that microprocessor is not a
task for the faint-hearted.

q Is the Processor Supported by Appropriate and Adequate Tools?

q Good tools are critical to project success.

q At a minimum, you’ll need a good crosscompiler and good
debugging support.

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 PROCESSOR SELECTION CRITERIA

q To design an efficient embedded system, selection of right processor is

very important and challenging task

q Types of processors: µP, µC, Digital signal processor (DSP)

q µP are offered in 4 to 64-bit size with distinct features like cost, speed, no.
of CPU core, address & data line are used in simple toys to network router

q µC plays an important role in embedded system design and majorly used

in low-end to high-end control applications

q DSP are majorly used for high computation intensive applications such as
image processing, communication devices, voice to text converter etc.,
MODULE - 3 CSE3006 – EMBEDDED SYSTEM DESIGN 38
 PROCESSOR SELECTION CRITERIA
q Sequence of analysis to be made selecting an appropriate processor for
embedded system applications as follows,
1. Application requirement analysis: understand the purpose of
application and arrive specific requirement
2. Processor Architecture analysis: MCS51, ARM, PIC, PowerPC, MIPS etc.,

3. Peripheral set analysis: Includes on-chip (RAM, ROM ,I/O Ports, ADC)
and specialized processing units (FPU, MMU, DMA)

4. Technical analysis: Execution speed, operating voltage, power

consumption, and data & address bus size etc.,

5. Non-technical analysis: Cost, software tools, package type, vendor

reputation, support etc.,
MODULE - 3 CSE3006 – EMBEDDED SYSTEM DESIGN 39
 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Wireless Spot Billing Machine

q POS Hand Held spot Billing Machine (SBM) is a GPRS Enabled machine.
The device is compact and lightweight(less than 500grms).
q The machine is equipped with technology which serves as a Hand Held
computer.
q The device is WEB/USB enabled which helps the operator to get instant
bill remotely and update transactions back to the server.

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Wireless Spot Billing Machine

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Application Spot Billing Machine spot billing machine

q Electricity and Water Billing

q Cable and Internet Billing
q Canteen and Hotel Billing
q Finance and Daily Bill Collection
q Bus and Parking Ticketing
q Distribution and Retail Billing
q Petrol and Toll Gate Tokens
q All kinds of General Billing

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Block Diagram

MODULE - 3 CSE3006 – EMBEDDED SYSTEM DESIGN 42

 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Features of Spot Billing Machine spot billing machine

q Billing Machine is easy to operate and user-friendly.

q It is highly secured with Password protection.
q It is accessible to the remote application via GPRS.
q It holds the Customer Data in memory.
q Accurate data Import and Export Settings

MODULE - 3 CSE3006 – EMBEDDED SYSTEM DESIGN 42

 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Specification
Processor : ARM 32-bit Cortex-M3 CPU(120 Mhz max)with Adaptive real-time accelerator (ART Accelerator),
MPU,150DMIPS/1.25DMIPS/MHz(Dhrystone 2.1)capable of In-System Programming.
On The Fly Programming(Can be done in the field using laptop)for Upgrading the units through
Serial/USB Ports.
Choice of Program Memory Capacity of 512K/1024K bytes.

Memory : 8 MB of Non-volatile data memory is provided with the units data retention is minimum 10 years
with out any power being applied. Expandable to 16 MB
Optional - It also has micro SD card slat for large memory backup.
Real Time Clock : In-built Real time clock with battery backup.
Key-Board : A 35 key multi function key board is provided on the front panel.
LC Display : 132*64 pixels graphical LCD display with back light provided for user interaction. It has various
graphical icons for indication of battery status, signal status etc.

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Specification
Printer : High Speed 24 Column Impact Printer With 2.7 Lines/Sec, is Provided as
Standard fitment.
Paper Roll : 57.5mm+/-0.5mm,60mm dia Paper Roll Fitment.
Communication : a) RS232C Ports-1 Nos(Option of second port)with flexible baud rates.
b) RS232C Ports-1 Nos(Option of second port)with flexible baud rates.
c) Optional IR or IRDA or Both IR or IRDA Port for Communication with electricity meters.
d) Built-in GSM/GPRS modem optional.
e) Optional GPS.
Smart Card Interface : Optional Contact & Contact less(MIFARE)Smart Card Interface.
Batteries : The units are powered by 7.4v 2600 mAH LI-ION Rechargeable Battery pack.
Battery Charger : External Universal voltage AC/DC 9.7V-2Amp Adaptor provided.
Mechanical Dimension : Width-102.00,Length-276.00,Height-82.00.
Weight : Weight-655grams~(without paper roll).

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Processor

The Cortex-M3 processor is specifically developed for high-performance,

low-cost platforms for a broad range of devices including microcontrollers,
automotive body systems, industrial control systems and wireless networking
and sensors

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Processor

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Processor

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device
Nested Vector Interrupt

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Nested Vector Interrupt

q Nested vector interrupt control (NVIC) is a method of prioritizing interrupts,

improving the MCU’s performance and reducing interrupt latency.

q NVIC also provides implementation schemes for handling interrupts that

occur when other interrupts are being executed or when the CPU is in the
process of restoring its previous state and resuming its suspended process.

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Rugged Handheld Data Terminal

q It is built for life out in the field, integrates Corning Gorilla glass for display,
able to handle drops, bumps, spills, dust, vibration.

q With stable wireless connections and accurate efficient data capture

options, you can find this easy-to-deploy device a valuable helper to
increase productivity in logistics, express delivery, warehousing, retail
and industrial manufacture etc.

MODULE - 3 CSE3006 – EMBEDDED SYSTEM DESIGN 42

 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Rugged Handheld Data Terminal

q Android 10.0 OS
q 8GB ROM + 1 GB RAM（16GB+2GB Optional）
q 4'' high resolution(480*800) IPS TFT display
q 8MP AF Camera with LED flash
q 2G,3G,4G ,WIFI,Bluetooth connection
q IP 65 Sealing
q 2D Zebra SE4710 barcode scanner

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Specification

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Processor

q The Cortex-A53 processor is a high efficiency processor that implements

the Armv8-A architecture.

q The Cortex-A53 processor has one to four cores, each with an L1 memory
system and a single shared L2 cache. It can be combined with other
Cortex-A CPUs in a big. LITTLE configuration.

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Processor

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 PROCESSOR SELECTION CRITERIA
Case study-1: Handheld Device

Processor

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Digital Still Camera

q Digital still cameras require a significant amount of silicon contents,

including the sensor (CCD or CMOS), the analog components (ADC, NTSC
encoder, …) and the engine (Digital Signal Processor).

q DSP - is the brain of the camera and is responsible for performing all the
computations needed to process and compress the image.

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Digital Still Camera

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Digital Still Camera

q Most DSCs use a CCD imager to sense the images.

q The driver electronics and the Timing Generator circuitry generate the
necessary signal to clock the CCD.
q Correlated Double Sampling and Automatic Gain Control electronics are
used to get a good-quality image signal from the CCD sensor.
q This CCD data is then digitized and fed into the DSC engine.
q All the image-processing and image-compression operations are
performed in the DSC engine.

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Digital Still Camera

q On most DSCs, the user has the ability to view the image to be captured
on the LCD display.
q The compressed images are stored in Flash memory for later use.
q Most DSC systems also provide an NTSC/PAL video signal to view the
captured images (also the preview images) on a TV monitor.
q The current DSCs also provide ways to connect to the external PC or
printer through an RS-232 or a USB port.

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera
Image Pipeline

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Image Pipeline
q The Colour Filtered Array (CFA) data needs to undergo significant amount
of image processing before the image can be finally presented in a
usable format for compression.
q All these processing stages are collectively called the “image pipeline.”
q Most of these tasks are multiply-accumulate (MAC) intensive operations.
q The TMS320C54x DSP is well suited to perform these tasks efficiently and
generate a high-quality image that is close to the image quality offered
by traditional film from the raw CCD data.

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Processor - TMS320C54x DSC

q This system interfaces to the CCD/CMOS module directly.

q The DSP reads the data from the sensor, processes the raw sensor data,
and writes it to the SDRAM.
q The built-in NTSC/PAL encoder chip on the board allows direct display of
the processed picture on the TV monitor.
q All image pipeline operations, including JPEG compression, can be
performed on the TMS320C54x on this 16 x 16 block of pixels and then the
compressed bit stream is written out to the SDRAM.

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Processor - TMS320C54x DSC

q This system interfaces to the CCD/CMOS module directly.

q The DSP reads the data from the sensor, processes the raw sensor data,
and writes it to the SDRAM.
q The built-in NTSC/PAL encoder chip on the board allows direct display of
the processed picture on the TV monitor.
q All image pipeline operations, including JPEG compression, can be
performed on the TMS320C54x on this 16 x 16 block of pixels and then the
compressed bit stream is written out to the SDRAM.

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Processor - TMS320C54x DSC

q On this system, all image pipeline operations can be executed on chip

since only a small 16 x 16 block of the image is used.
q The TMS320C549 is well suited due to its large on-chip memory (32K x 16-
bit RAM and 16K x 16-bit ROM).
q In this way, the processing time is kept short, because there is no need for
external high-speed memory.
q This device offers high performance (100 MIPS) at low power consumption
(0.45mA/MIPS).

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Processor - TMS320C54x DSC

q Due to the efficiency of the TMS320C54x instruction set and architecture,

the entire image pipeline, including JPEG, takes about 150 cycles/pixel.
q Hence, a 1-Mpixel CCD image can be processed in 1.5 seconds on a
100-MHz TMS320C54x.
q This offers about a 2-second shot-to-shot delay, including data movement
from external memory to on-chip memory.

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Processor - TMS320C54x DSC

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 PROCESSOR SELECTION CRITERIA
Case study-2: Digital Camera

Processor - TMS320C54x DSC

q Due to the efficiency of the TMS320C54x instruction set and architecture,

the entire image pipeline, including JPEG, takes about 150 cycles/pixel.
q Hence, a 1-Mpixel CCD image can be processed in 1.5 seconds on a
100-MHz TMS320C54x.
q This offers about a 2-second shot-to-shot delay, including data movement
from external memory to on-chip memory.

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 PROCESSOR SELECTION CRITERIA
Case study-3: ATM

An automated teller machine or automatic teller machine (ATM) is a

computerized telecommunications device that provides a financial
institution's customers a secure method of performing financial transactions
in a public space without the need for a human clerk or bank teller.

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 PROCESSOR SELECTION CRITERIA
Case study-3: ATM

ATM – Block Diagram

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 PROCESSOR SELECTION CRITERIA
Case study-3: ATM

ATM – Harware
q CPU (to control the user interface and transaction devices)
q Magnetic and/or Chip card reader (to identify the customer)
q PIN Pad (similar in layout to a Touch tone or Calculator keypad), often
manufactured as part of a secure enclosure.
q Secure cryptoprocessor, generally within a secure enclosure.
q Display (used by the customer for performing the transaction)
q Function key buttons (usually close to the display) or a Touchscreen (used
to select the various aspects of the transaction)
q Record Printer (to provide the customer with a record of their transaction)
q Vault (to store the parts of the machinery requiring restricted access)
q Housing (for aesthetics and to attach signage to)
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 PROCESSOR SELECTION CRITERIA
Case study-3: ATM

ATM – Vaults

q Dispensing mechanism (to provide cash or other items of value)

q Deposit mechanism (to take items of value from the customer)
q Security sensors (Magnetic, Thermal, Seismic)
q Locks (to ensure controlled access to the contents of the vault)

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 PROCESSOR SELECTION CRITERIA
Case study-3: ATM

ATM – Networking

q The internet service provider (ISP) also plays an important role in the ATMs.
q This provides communication between ATM and host processors.
q When the transaction is made, the details are input by the cardholder.
q This information is passed on to the host processor by the ATM.
q The host processor checks these details with an authorized bank.
q If the details are matched, the host processor sends the approval code to the machine
so that the cash can be transferred.)

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 PROCESSOR SELECTION CRITERIA
Special Purpose Processor

q Using a single-purpose processor in an embedded system results in several design metric

benefits and drawbacks, which are essentially the inverse of those for general purpose
processors.
q Performance may be fast, size and power may be small, and unit-cost may be low for
large quantities
q While design time and NRE costs may be high, flexibility is low, unit cost may be high for
small quantities, and performance may not match general-purpose processors for some
applications.

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GOALS OF DATA COMPRESSION IN EMBEDDED SYSTEM

üCompress data transmitted over serial line.

üReceives byte-size input symbols.

üProduces output symbols packed into bytes.

üWill build software module only here.

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BLOCK DIAGRAM FOR COMPRESSOR

1..m packed
1..n input output
symbols symbols
input data compressor output

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HUFFMAN CODING

Ø Early statistical text compression algorithm.

Ø Select non-uniform size codes.
Ø Use shorter codes for more common symbols.
Ø Use longer codes for less common symbols.
Ø To allow decoding, codes must have unique prefixes.
Ø No code can be a prefix of a longer valid code.

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HUFFMAN EXAMPLE

character P
a .45
b .24
c .11
d .08
e .07
f .05

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EXAMPLE HUFFMAN CODE

• Read code from root to leaves:

a 1
b 01
c 0000
d 0001
e 0010
f 0011

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REQUIREMENTS

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BUILDING A SPECIFICATION

• Block diagram shows only input/output.

• A real system must:
• Accept an encoding table.
• Allow a system reset that flushes the compression buffer.

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DATA-COMPRESSOR CLASS

data-compressor

buffer: data-buffer
table: symbol-table
current-bit: integer
encode(): boolean,
data-buffer
flush()
new-symbol-table()
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DATA-COMPRESSOR BEHAVIORS

• encode: Takes one-byte input, generates packed encoded symbols and a

Boolean indicating whether the buffer is full.
• new-symbol-table: installs new symbol table in object, throws away old
table.
• flush: returns current state of buffer, including number of valid bits in
buffer.

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AUXILIARY CLASSES

data-buffer symbol-table

databuf[databuflen] : symbols[nsymbols] :
character data-buffer
len : integer len : integer

insert() value() : symbol

length() : integer load()

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AUXILIARY CLASS ROLES

• data-buffer holds both packed and unpacked symbols.

• Longest Huffman code for 8-bit inputs is 256 bits.
• symbol-table indexes encoded verison of each symbol.
• load() puts data in a new symbol table.

Computers as Components 5e © 2022 Marilyn Wolf

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CLASS RELATIONSHIPS

data-compressor
1
1

1 1

data-buffer symbol-table

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ENCODE BEHAVIOR

create new buffer return true

T add to buffers
input symbol

encode buffer filled?

F
add to buffer return false

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INSERT BEHAVIOR

pack into
T this buffer
input
symbol update
fills buffer?
length

F
pack bottom bits
into this buffer,
top bits into
overflow buffer
 PROGRAM DESIGN

• To build an encoder by using either object-oriented and non-object-

oriented implementations
• Object-oriented design might be done using C++
• Non-object-oriented design might be done using C.
TESTING
• Test by encoding, then decoding:

symbol table

input symbols encoder decoder result

compare

Computers as Components 5e © 2022 Marilyn Wolf