A new Excess-1 circuit based High-Speed Carry

Select Adder in 18 nm FinFET Technology

JEEVAN BATTINI (  [email protected] )
Kakatiya Institute of Technology and Science
NARAYANA PASHYA
Kakatiya Institute of Technology and Science
SIVANI KOSARAJU
Kakatiya Institute of Technology and Science

Research Article

Keywords: FinFET, Carry Select Adders, Multiplexer, Cadence

Posted Date: May 5th, 2023

DOI: https://doi.org/10.21203/rs.3.rs-2884939/v1

License:   This work is licensed under a Creative Commons Attribution 4.0 International License.
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Additional Declarations: No competing interests reported.

 A new Excess-1 circuit based High-Speed Carry Select
Adder in 18 nm FinFET Technology

Jeevan Battini1, Pashya Narayana Reddy2 and SivanKosaraju3

[email protected], [email protected],
[email protected]

Abstract. Conventional carry select adder (CCSA) uses a multiplexer in the fi-
nal stage to select either an excess-1 result or a normal result. To improve the
delay and number of transistors a new topology is Proposed (PCSA) that uses
only a single type of cell i.e., a 2-1 multiplexer. The 2-1 multiplexer is con-
structed in CMOS and TGL logic styles using 18nm FinFETs. The sub-blocks
such as half adder and excess-1 circuit used in this PCSA is realized using only
a 2:1 multiplexer. Due to the usage of a single type 2:1 multiplexer, the PCSA
exhibits better circuit regularity. The new topology of PCSA is designed using
FinFET-based TGL and CMOS styles. All the adders such 4- and 8-bit are de-
signed, simulated, and analyzed using Cadence Virtuoso, ADEL, and ADEXL
at 18nm FinFET technology. The result analysis reveals that the speed perfor-
mance and the number of transistors of 8-bit PCSA are better by 44.02% and
4% respectively compared to existing adders.
Keywords: FinFET, Carry Select Adders, Multiplexer, Cadence

1 Introduction

Mobile gadgets, wireless receivers, and bio-medical instruments are constructed with
low-power VLSI sub-systems. The main element of an arithmetic unit is the adder.
Multiple adders are used in a complicated digital signal processing (DSP) system. A
sophisticated DSP system's performance is basically improved by an effective adder
design. An RCA-RCA arrangement known as a conventional carry select adder
(CCSA) corresponds to the expected input-carry (Cin = 0 and 1), creates a pair of sum
bits and two output carry bits, and selects one from each pair for the final-sum and
final-output-carry [1]. The most fundamental components of all arithmetic and digital
processing units are adder circuits. The most crucial adder block characteristics are
area and propagation delays [22]. In many signal-processing applications, addition is
a crucial arithmetic operation [23]. Consequently, power usage turns into a significant
issue in the design of digital circuits. Achieving performance requirements while
using the least amount of power is one of the goals of VLSI circuit design. Depending
on the fin height and fin thickness, a FinFETs effective width might vary. The Fin-
FETs used have a gate length of 18nm and a fin pitch of 48nm [2]. A CPU's adder
circuit is largely responsible for its speed performance. It has been observed that cer-
2

tain adder circuits can perform faster [3] but with more Power consumption. To ad-
dress the issues with power usage, a FinFET based carry select adder (CSA) is pro-
posed which consumes less power than MOSFET [4]. On a structural level, the Fin-
FET is one of the most famous innovations of the fin-type FET, features a thin silicon
body covered in gate electrodes or by biasing it individually, the leakage current may
be reduced [5].
The most fundamental arithmetic operation is addition, and several adders are utilized
in VLSI. For creating reliable systems, reliable adders are crucial [6]. A ripple-carry
adder requires the carry to ripple through all full adders, but a carry-select adder just
requires the carry to travel through a single multiplexer. This is the fundamental dif-
ference between the two types of adders [7]. A carry-select adder's n-bit slices are
broken up into different blocks that might have varying lengths with block carry-in
values of 0 and 1, each block is assessed conditionally [8]. As dependencies only exist
in the shortest path of each level, the impact of any shortest path on the critical path is
independent of the other paths, and the high-speed feature of the Kogge-Stone adder
is used to make up for the extra delay in place of a circuit for error detection and cor-
rection. The amount of time needed to create the carry is determined by the input
data[17]. The configuration, design constraints, and effective utilization of the funda-
mental data path design for basic digital operations like addition, multiplication, divi-
sion, and subtraction that combines standard full adders have all improved processor
core performance [25].
The PMOS pull-up network and the NMOS pull-down network are the foundation of
the traditional CMOS (Complementary metal-oxide-semiconductor) logic approach.
High-speed Multiplexer circuit design has recently been worked on utilizing a con-
ventional CMOS technology [9]. CMOS specifications were used to create the basic
semiconductor technology that was used to build the traditional adders and subtrac-
tors. There is an increase of more transistors and delays because of this [20]. The
benefit of traditional CMOS logic is its resistance to voltage scaling, which is neces-
sary for dependable operation at low voltage. The transmission gate is a parallel as-
sembly of NMOS and PMOS transistors. The operation of NMOS and PMOS transis-
tors is simultaneous. Over the whole input voltage range, TG provides a low re-
sistance path between the input and output terminals. When combined, NMOS and
PMOS transistors propagate logic values without experiencing a threshold voltage
drop since their gate terminals are controlled by complementary signals [10]. The TG
transmits specific input signals to the output according to the voltage provided to the
gate input [11].
The Carry-Select adder is based on the idea that if the result is computed immediately,
the carry propagation (and sum evaluation) in a chain of m full adders (FAs) may be
greatly sped-up. Cin does not wait for the carry input signal to arrive. To be more
precise, carry and sum outputs are assessed in parallel with the assumption that Cin is
equal to 0 and 1, respectively, and the proper outcome is then chosen using a multi-
plexer based on the value of Cin [19]. The proposed approach utilizes carry computa-
tion blocks that minimize the area without requiring external blocks and can create the
sum output without calculating a separate process using carry inputs of '0' and '1' in
place of Binary to Excess-1 Converter and Carry Generation Logic [18].
 3

2 Existing Designs

2.1 Conventional Carry Select Adder (CCSA)

A Conventional Carry Select adder (CCSA) has a Ripple Carry adder RCA-RCA
architecture and generates two outputs, the sum and carry bits, corresponding to the
carry input signals Cin=0 and Cin=1, selecting one from each pair as the final-sum
and final-carry. It has three stages, the first and second stage contains RCAs, and the
third stage contains the sum and carry generation units. In comparison to a ripple
carry adder, a CCSA has a less carry propagation delay, but it employs a dual RCA,
hence the design is not attractive [12]. However, the extra RCA structure in each
block increases the adder's size and propagation delay. Many CSA methods have
already been proposed [24].

2.2 XOR Based CSA(XBC)

The XOR-based full adder is used to create XOR-based CSAs (XBC). In its de-
sign, it makes use of two AND gates, two XOR gates, and a single OR gate. The pri-
mary distinction between conventional and XOR-based adders is that the former uses
only one 2:1 MUX in place of two XOR gates and only needs six MOSFETs, whereas
the latter uses two AND gates and one OR gate in place of two XOR gates and needs
at least 18 MOSFETs. Therefore, XOR-based 1-bit adders save at least 12 MOSFETs
compared to conventional ones, which reduces their need for space and power while
simultaneously improving their delay performance [13] than conventional adders.

2.3 Multiplexer

Any logic gate may be implemented using a multiplexer, which is a versatile combi-
national circuit. A digital circuit called a multiplexer contains 2n input lines, n selec-
tion lines, and an output line [14]. A general block diagram for the multiplexer is
shown in Figure 1. Multiplexer is a device that generates the output, depending on the
signals sent into the selection lines, it reflects one input at the output. If selection line
S is logic ‘0’, then the output generated is A and if S is logic ‘1’, then the output gen-
erated is B. When A=0, B=0 and S=0, then Y=0. When A=0, B=1 and S=1, then Y=1.
When A=1, B=0 and S=0, then Y=1. When A=1, B=1 and S=1, then Y=1. The output
is obtained as shown below in Table 1. The main block of the proposed design is the
2:1 multiplexer as shown in Figure 1. The multiplexer is designed using two logic
styles CMOS and TGL. The Boolean expression for the 2:1 multiplexer is given be-
low.

Y= A.S’ + B.S (1)

4

A 0
2:1 '
Y = A.S + B.S
B 1 Mux

Fig. 1. 2:1 Multiplexer Block Diagram.

Table 1. 2:1 Multiplexer Truth Table.

A B S Y = A S’ + B S
0 0 0 0
0 1 1 1
1 0 0 1
1 1 1 1

2.4 CMOS 2-1Multiplexer

CMOS 2:1 Multiplexer (2-1M) is designed using 10 FinFETs including an inverter at

the output as shown in Figure 2. It has two networks pull-up network (PUN) and a
pull-down network (PDN). The working of CMOS 2-1M is based on a selection line.
The operation of CMOS 2-1M for various logic values of A, B, and S is given below.
1. When A=0, B=0, S=0 then transistors P1, P3, P4 gets turned ON, P2
will be OFF in PUN and the transistors N1, N2, N4 gets turned
OFF, N3 will be ON in PDN. Then A is generated at the output.
2. When A=0, B=1, S=1 then transistors P3, P4 gets turned OFF, P1,
P2 will be ON in PUN and the transistors N1, N3 gets turned OFF,
N2, N4 will be ON in PDN. Then B is generated at the output.
3. When A=1, B=0, S=0 then transistors P1, P2 gets turned OFF and
P3, P4 will be ON in PUN and the transistors N2, N4 gets turned
OFF, N1, N3 will be ON in PDN. Then A is generated at the out-
put.
4. When A=1, B=1, S=1 then transistors P1, P3, P4 gets turned OFF
and P2 will be ON in PUN and the transistors N1, N2, N4 gets
turned ON, N3 will be OFF in PDN. Then B is generated at the
output.
 5

VDD

'
A S

P1 P2

B S

P1 P2 Y= A. S' + B.S

A B

N1 N2

'
S S

N3 N4

Fig. 2. CMOS 2-1M Circuit.

2.5 TGL 2-1 Multiplexer

A TGL based 2-1 M is realized using 4 FinFETs and is shown in Figure 3. The work-
ing of TGL 2-1 M is based on a selection line. When selection line S is logic ‘0’ then
the transistors N2 and P2 are turned OFF, N1 and P1 transistors are turned ON and
pass data A to the output. When selection line S is logic ‘1’ then the transistors N2
and P2 are turned ON, the transistors N1 and P1 are turned OFF and passes data B to
the output.
S'
N1

P1

S Y= A. S' + B.S
N2

P2
S'
Fig. 3. TGL 2-1M Circuit.
6

2.6 Half Adder

Two inputs (A & B) and two outputs (SUM and CARRY) make up a half-adder and
are shown in Figure 4 which is realized using 2-1Ms. The internal structure of Half
adder contains XOR & AND gate logics. The SUM is generated by XOR logic and
CARRY is generated by AND logic. In this research, half adder is realized using only
2-1 M. The expression for SUM and CARRY is shown below.

S=A^B (2)
C=A&B (3)
VDD
Ab
N1
B Ab
B
P1 P2

Bb A P1
A SUM
P3 P4 N2
SUM
Bb
B Bb

N1 N2 P2
Ab
Ab A

N3 N4

VDD
Ab
N1
0 Ab
0
P1 P2

B A P1

A CARRY
P3 P4
N2
CARRY
B

0 B

N1 N2 P2
Ab
Ab A

N3 N4

(i) (ii)
Fig. 4. (i) CMOS Half adder using 2-1M (ii) TGL Half adder using 2-1M
 7

3 Proposed Carry Select Adder (PCSA)

3.1 New Excess-1 Circuit

An Excess-1 circuit has two direct inputs (A and B) and two outputs, known as EX1_
SUM and EX1_CARRY. In this work, the Excess-1 circuit is realized using only 2-
1M as shown in Figure 5. The truth table for the Excess-1 circuit is shown in Table 2.

EX1_SUM = ~ (A^B) (4)

EX1_CARRY = A | B (5)

Table 2. Excess-1 circuit Truth Table.

A B EX1_SUM EX1_CARRY
0 0 1 0
0 1 0 1
1 0 0 1
1 1 1 1

3.2 4-Bit Proposed Carry Select Adder

The 4-bit PCSA is realized using a Half adder, a new Excess-1 circuit and 2-1Ms.
PCSA 4-bit uses 4 Half adders, 4 Excess-1 circuits, and 8 Multiplexers in its design. It
has two stages i.e., Stage I and Stage II. Stage I contains only Half adders, Excess-1
adders, and Stage II contains only multiplexers to give sum and carry outputs as
shown in figure 6.
A 4-bit PCSA provides the SUM (S3-S0) and CARRY (Cout-C0) as outputs based
on Cin (0 or 1). In a 4-bit PCSA there are four sections, each section contains one
Half adder, one Ex-1 adder, and two multiplexers to produce Si & Ci where i value
depends on size of the adder. Where A [0] & B [0] are the two inputs given to HA0
and Ex1_0 adder. The SUM generated by HA0 and Ex1_0 adder is given to 2-1M _1
which produces S[0] and then CARRY generated by HA0 and Ex1_0 is given to 2-
1M_2 which produces C[0].In this PCSA the Carry propagation is done through The
generated C[0] is propagated through 2-1M_3 which provides S[1] as output with
respect to Cin (0 or 1). Similarly, S [2], S [3], and C[1], C[2], Cout are generated.
8

VDD
Ab
N1
Bb Ab
Bb

P1 P2

B A P1
A Ex1_SUM
P3 P4 Ex1_SUM N2
B
Bb B

N1 N2 P2
Ab
Ab A

N3 N4

VDD
Ab
N1
B Ab
B
P1 P2

1 A P1

A Ex1_CARRY
P3 P4 Ex1_CARRY
N2
1

B 1

N1 N2 P2
Ab
Ab A

N3 N4

(i) (ii)
Fig. 5. (i) CMOS Excess-1 adder using 2-1M (ii) TGL Excess-1 adder using 2-1M

The main highlights of the proposed topology of 4-bit PCSA are listed below.
1. The excess-1 result is directly generated from readily available inputs instead
from half adders output as seen in existing CSAs.
2. The excess-1 block is designed in a distinct way using FinFETs in both
CMOS and TGL styles.
3. The PCSA has only two stages which minimize the delay compared to exist-
ing designs (comprises three stages)
4. The design uses a single type of cell i.e., 2-1M strictly following the cell reg-
ularity concept.
5. As the design uses FinFETs, it is best suitable for lower technology nodes
(18nm) and lower supply voltages (0.8V, 1V, 1.2V and 1.5V).
 9

Cin

A[0] S1[0] 0
2-1 S[0]
C1[0] M_1
HA0 1
B[0]
Cin

0
Se1[0]
EX1_0 1 2-1 C[0]
Ce1[0]
M_2

Cin

S1[1] 0
A[1]
2-1 S[1]
C1[1]
HA1 1 M_3
B[1]
Cin

0
Se1[1]
EX1_1 2-1 C[1]
Ce1[1] 1
M_4

Cin

A[2] S1[2] 0
2-1 S[2]
C1[2]
HA2 1 M_5
B[2]
Cin

0
Se1[2]
EX1_2 2-1 C[2]
Ce1[2] 1
M_6

Cin

A[3] S1[3] 0
2-1 S[3]
C1[3]
HA3 1 M_7
B[3]
Cin

0
Se1[3]
EX1_3 2-1 Cout
Ce1[3] 1
M_8

STAGE-I STAGE-II
Fig. 6. Proposed Block diagram of 4-Bit PCSA.
10

Similarly, an 8-bit PCSA is realized using 2:1 multiplexer, half adders, an Excess-1
circuit. 8-bit PCSA uses 8 Half adders, 8 Excess-1 circuits, and 16 Multiplexers in its
design. The output of 8-bit PCSA is SUM (S7-S0) and CARRY (Cout-C0) with respect
to Cin (0 or 1).

4 Results and Analysis

4.1 Simulation set-up

A useful simulation environment is needed to analyze the Proposed design perfor-

mance while it is really being used in VLSI applications [15]. All the circuits are de-
signed, simulated, and analyzed using Cadence virtuoso, ADEL & ADEXL tools in
the 18-nm FinFETs technology. For comparison of power dissipation, all the designs
are tested at different voltages such as 0.8V, 1V,1.2V, and 1.5V. A 4-bit and 8-bit
PCSA design with less delay and a smaller number of transistors has been presented
in this paper [16]. The proposed design and Existing design results are compared and
are presented in Table 7 [21]. The real-time schematics of the half adder and Excess-1
circuit are shown in Figure 7 and Figure 9 respectively and the real-time schematic of
the 4-bit PCSA is shown in Figure 11 which is implemented using the Cadence Virtu-
oso tool.

4.2 Delay analysis

The delay analysis is carried out using the analog design environment of the ca-
dence tool and the transient response of half adder and excess-1 circuit are shown in
figure 8 and figure 10 respectively and the transient response of 4-bit CMOS and
TGL PCSA is shown in figure 12 and figure 13 respectively. The delay analysis is
carried out for various supply voltages i.e., 0.8V, 1V, 1.2V and 1.5V. After perform-
ing critical path analysis by considering worst-case delay CMOS and TGL 4-bit
PCSAs exhibit a delay of 404.5ps and 272ps with minimum supply voltage that is
0.8V. Both PCSAs exhibit a maximum delay at least the possible supply voltage and a
minimum delay of 1.5V. The analysis is extended to 8-bit PCSAs; 809.9ps and
777.7ps are the delays exhibited by CMOS and TGL Proposed adders respectively.
The delay results of 4-bit PCSAs and 8-bit PCSAs are given in Table 3 and Table 4.
The delay comparison is shown table5; it manifests that there is a 43.33% and 44.02%
improvement in delay for Proposed 4- and 8-bit CMOS PCSAs respectively. Among
CMOS and TGL types of PCSAs, the later exhibit more delay therefore it is compared
with the existing adder’s delay.
 11

Fig. 7. Half adder schematic

Fig. 8. Transient response of Half adder

12

Fig. 9. Excess-1 circuit schematic

Fig. 10. Transient response of Excess-1 circuit.

Table 3. Delay results of 4-bit PCSAs.

Voltage(V) CMOS 4-bit PCSA TGL 4-bit PCSA

0.8 404.5ps 272ps

1 287.8ps 211.9ps

1.2 229.5ps 167.8ps

1.5 186.1ps 133.7ps

 13

Fig. 11. 4-Bit PCSA schematic

Fig. 12. Transient response of CMOS 4-Bit PCSA

14

Fig. 13. Transient response of TGL 4-Bit PCSA

Table 4. Delay results of 8-bit PCSAs.

Voltage(V) CMOS 8-bit PCSA TGL 8-bit PCSA

0.8 809.9ps 777.7ps

1 570.9ps 557.5ps

1.2 453.8ps 444.7ps

1.5 366.1ps 359.7ps

4.3 FinFETs count comparison

The area comparison of the proposed and existing design is done based on the Fin-
FETs count. The block-wise transistor count required to construct 4-and 8-bit PCSAs
is shown in Table 6 and Table 7 respectively. The Total transistors required for 4-bit
CMOS and TGL PCSAs are 286 and 118 respectively. The Proposed TGL PCSA
requires a lower number of FinFETs compared to CMOS PCSA.

Table 5. Delay Comparison of 4-bit and 8-bit PCSAs.

Bit size Adder Delay(ps)

CCSA 512.2
XBC 507.6
4-bit Adder CMOS PCSA 287.7
TGL PCSA 211.9
% reduction 43.33%
CCSA 1100
XBC 1020
8-bit Adder CMOS PCSA 570.9
TGL PCSA 557.5
% reduction 44.02%
 15

But CMOS PCSA exhibits a high noise margin compared to TGL PCSA. The 4-bit
TGL type PCSA requires 8 fewer FinFETs compared to the Existing type XBC adder.
Similarly, 8-bit PCSA requires less area compared to 8-bit XBC. The FinFET count
comparison is shown in Table 8. Therefore, CMOS PCSA is best suitable for high
noise margin output and is robust to supply voltage. TGL PCSAs are preferred for
low-area and high-speed applications.

Table 6. Number of FinFETs required for 4-bit PCSAs.

4-Bit PCSA CMOS TGL
PCSA PCSA
1-INV 2T 2T
1-MUX 10T 4T
1-HA 20T 8T
1-EX-1 30T 12T
3-INV 6T 6T
8-MUX 80T 32T
4-HA 80T 32T
4-EX-1 120T 48T
Total number of FinFETs 286T 118T

Table 7. Number of FinFETs required for 8-bit PCSAs.

8-Bit PCSA CMOS PCSA TGL
PCSA
1-INV 2T 2T
1-MUX 10T 4T
1-HA 20T 8T
1-EX-1 30T 12T
7-INV 14T 14T
16-MUX 160T 64T
8-HA 160T 64T
8-EX-1 240T 96T
Total number of FinFETs 574T 238T
16

Table 8. FinFETs count Comparison of Proposed and Existing adders.

Bit size Adder # of FinFETs

CCSA 198
XBC 126
4-bit PCSA CMOS PCSA 286
TGL PCSA 118
% reduction 7%
CCSA 390
XBC 246
8-bit PCSA CMOS PCSA 574
TGL PCSA 238
Percentage reduction 4%

5 Conclusion

The performance of CMOS and TGL-based PCSAs are analyzed and compared in
terms of delay and FinFETs count with respective existing designs. This work uses a
2:1 multiplexer, half adder, and New Excess-1 circuit to construct PCSAs. TGL type
uses fewer FinFETs than CMOS in both 4- and 8-bit PCSAs. The Proposed adders
exhibit better circuit regularity with the usage of a single 2:1 Multiplexer in each
block. All the circuits are designed in 18nm FinFETs technology and simulated at
different Voltages such as 0.8V, 1V,1.2V, and 1.5V using Cadence Analog Design
Environment Virtuoso, ADEL & ADEXL tools. The proposed 8-bit CMOS PCSA has
less delay by 44.02% compared to existing designs in the worst case. The Proposed
TGL PCSAs require 8 fewer FinFETs compared to existing designs. Hence, the pro-
posed adder circuits are better than the existing adders. This work can be extended by
developing the layouts and post-layout analysis for the final custom integrated circuit
design. These adders may be applicable for high-speed and low-area arithmetic and
logic VLSI circuits.

Authors’ contributions
All authors contributed to the study conception and design. Material preparation, data
collection and analysis were performed by [B. Jeevan] [P. Narayana] and [K. Sivani].
The first draft of the manuscript was written by [B. Jeevan] and all authors comment-
ed on previous versions of the manuscript. All authors read and approved the final
manuscript.

Funding
The author(s) received no fnancial support for the research, authorship, and/or publi-
cation of this article.

Data availability
 17

The datasets generated during and/or analyzed during the current study are available
from the corresponding author on reasonable request.

Declarations
Ethics approval
Not Applicable (as the results of studies do not involve any human or animal).

Consent to participate
Not Applicable (as the results of studies do not involve any human or animal).

Consent for publication

All authors approved the final manuscript.

Conflict of interests/ Competing interests

The authors declare that they have ‘no known conflict of interests or personal rela-
tionships’ that could have appeared to influence the work reported in this paper.

Acknowledgments

The authors would like to express gratitude to all those who helped directly/ indirectly
to carry out the research work.

Research involving human participants and/or animals

Not Applicable (as the results of studies do not involve any human or animal).

Informed consent
All authors read and approved the final manuscript.

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