Rashtreeya Sikshana Samithi Trust

RV Institute of Technology and Management ®

(Affiliated to VTU, Belagavi)

JP Nagar, Bengaluru – 560076

Department of Computer Science and Engineering

&
Department of Information Science and Engineering

Course Name: Computer Organization

Course Code: 18CS34

III Semester

2018 Scheme

Prepared By:
Dr. Anitha J,
Professor and Head of the Department,
Department of Computer Science and Engineering
RVITM, Bengaluru - 560076
Email: anithaj.rvitm@rvei.edu.in

Dr. Priyanga P,
Assistant Professor,
Department of Computer Science and Engineering
RVITM, Bengaluru - 560076
Email: priyangap.rvitm@rvei.edu.in
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COMPUTER ORGANIZATION MODULE I

MODULE I

BASIC STRUCTURE OF COMPUTERS

Computer definition: High speed Electro-mechanical device which accepts the inputs process
it according to the user instruction and produces the desirable output the presents in user readable
form on display or stores in the memory.

BASIC OPERAT1IONAL CONCEPTS

To perform a given task an appropriate program consisting of a list of instructions is stored
in the memory. Individual instructions are brought from the memory into the processor, which
executes the specified operations. Data to be stored are also stored in the memory. Examples:

Add LOCA, R0
This instruction adds the operand at memory location LOCA, to operand in register R0 &
places the sum into register. This instruction requires the performance of several steps,
1. First the instruction is fetched from the memory into the processor.
2. The operand at LOCA is fetched and added to the contents of R0
3. Finally the resulting sum is stored in the register R0

The preceding add instruction combines a memory access operation with an ALU Operations. In
some other type of computers, these two types of operations are performed by separate instructions
for performance reasons.
Load LOCA, R1
Add R1, R0
Transfers between the memory and the processor are started by sending the address of the
memory location to be accessed to the memory unit and issuing the appropriate control signals. The
data are then transferred to or from the memory. The figure1.1 shows how memory & the processor
can be connected. In addition to the ALU & the control circuitry, the processor contains a number of
registers used for several different purposes.

Instruction register (IR): Holds the instructions that is currently being executed. Its output is
available for the control circuits which generates the timing signals that control the various processing
elements in one execution of instruction.

Program counter PC: This is another specialized register that keeps track of execution of a program.
It contains the memory address of the next instruction to be fetched and executed.
The other two registers which facilitate communication with memory are: -
1. MAR – (Memory Address Register):- It holds the address of the location to be accessed.
2. MDR – (Memory Data Register):- It contains the data to be written into or read out of the
address location.
Apart from these register processor contains general purpose registers R0 to R n-1.

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Figure 1.1: Connections between the processor and the memory

Let us consider the steps involved in executing the instructions

o Programs reside in the memory & usually get these through the I/O unit.
 Execution of the program starts when the PC is set to point at the first
instruction of the program.
 Contents of PC are transferred to MAR and a Read Control Signal is sent to
the memory.
 After the time required to access the memory elapses, the address word is
read out of the memory and loaded into the MDR.
 Now contents of MDR are transferred to the IR & now the instruction is
ready to be decoded and executed.
 If the instruction involves an operation by the ALU, it is necessary to obtain
the required operands.
 An operand in the memory is fetched by sending its address to MAR &
Initiating a read cycle.
 When the operand has been read from the memory to the MDR, it is
transferred from MDR to the ALU.
o After one or two such repeated cycles, the ALU can perform the desired operation.
 If the result of this operation is to be stored in the memory, the result is sent to
MDR. Address of location where the result is stored is sent to MAR & a write
cycle is
 Initiated.
 The contents of PC are incremented so that PC points to the next instruction
that is to be executed.

Normal execution of a program may be preempted (temporarily interrupted) if some devices

require urgent servicing, to do this one device raises an Interrupt signal. An interrupt is a request
signal from an I/O device for service by the processor.

The processor provides the requested service by executing an appropriate interrupt service
routine. The Diversion may change the internal stage of the processor its state must be saved in the
memory location before interruption. When the interrupt-routine service is completed the state of the
processor is restored so that the interrupted program may continue.

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BUS STRUCTURE
To achieve a very good speed of operation a computer must be organized so that all its units
can handle one full word of data at a given time. When all the bits of the Word of data transferred at
s time then it is called as parallel connection. The group of wires/lines that serves as connection path
between the devices are called as bus.
There are several ways to connect devices to the bus the simplest way to interconnect is to use the
single bus as shown figure 1.2

Figure 1.2: Single bus structure

Since the bus can be used for only one transfer at a time, only two units can actively use the
bus at any given time. Bus control lines are used to arbitrate multiple requests for use of one bus.
Single bus structure is Low cost and Very flexible for attaching peripheral devices.

Multiple bus structure certainly increases, the performance but also increases the cost
significantly. All the interconnected devices are not of same speed & time, leads to a bit of a problem.
This is solved by using cache registers (ie buffer registers). These buffers are electronic registers of
small capacity when compared to the main memory but of comparable speed. The instructions from
the processor at once are loaded into these buffers and then the complete transfer of data at a fast rate
will take place. Example printer comes with buffer for the coordination with processor speed and
printing speed.

PERFORMANCE
The most important measure of the performance of a computer is how quickly it can execute
programs. The speed with which a computer executes program is affected by the design of its
hardware. For best performance, it is necessary to design the compiles, the machine instruction set,
and the hardware in a coordinated way.

The total time required to execute the program is elapsed time is a measure of the performance
of the entire computer system. It is affected by the speed of the processor, the disk and the printer.
The time needed to execute a instruction is called the processor time.

Just as the elapsed time for the execution of a program depends on all units in a computer
system, the processor time depends on the hardware involved in the execution of individual machine
instructions. This hardware comprises the processor and the memory which are usually connected by
the bus as shown in the figure 1.3 The pertinent parts of the figure 1.2 is repeated in figure 1.3 which
includes the cache memory as part of the processor unit. Let us examine the flow of program
instructions and data between the memory and the processor.

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Figure 1.3: The processor cache

At the start of execution, all program instructions and the required data are stored in the main
memory. As the execution proceeds, instructions are fetched one by one over the bus into the
processor, and a copy is placed in the cache later if the same instruction or data item is needed a
second time, it is read directly from the cache.

The processor and relatively small cache memory can be fabricated on a single IC chip. The
internal speed of performing the basic steps of instruction processing on chip is very high and is
considerably faster than the speed at which the instruction and data can be fetched from the main
memory. A program will be executed faster if the movement of instructions and data between the
main memory and the processor is minimized, which is achieved by using the cache.

For example suppose a number of instructions are executed repeatedly over a short period of time
as happens in a program loop. If these instructions are available in the cache, they can be fetched quickly
during the period of repeated use. The same applies to the data that are used repeatedly.

: PROCESSOR CLOCK
Processor circuits are controlled by a timing signal called clock. The clock designer the
regular time intervals called clock cycles. To execute a machine instruction the processor divides the
action to be performed into a sequence of basic steps that each step can be completed in one clock
cycle. The length P of one clock cycle is an important parameter that affects the processor
performance. Processor used in today’s personal computer and work station have a clock rates that
range from a few hundred million to over a billion cycles per second.

: BASIC PERFORMANCE EQUATION

We now focus our attention on the processor time component of the total elapsed time. Let
‘T’ be the processor time required to execute a program that has been prepared in some high-level
language. The compiler generates a machine language object program that corresponds to the source
program. Assume that complete execution of the program requires the execution of N machine cycle
language instructions. The number N is the actual number of instruction execution and is not
necessarily equal to the number of machine cycle instructions in the object program. Some instruction
may be executed more than once, which in the case for instructions inside a program loop others may
not be executed all, depending on the input data used.

Suppose that the average number of basic steps needed to execute one machine cycle
instruction is S, where each basic step is completed in one clock cycle. If clock rate is ‘R’ cycles per
second, the program execution time is given by

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T=( N* S ) / R

This is often referred to as the basic performance equation.

We must emphasize that N, S & R are not independent parameters changing one may affect
another. Introducing a new feature in the design of a processor will lead to improved performance
only if the overall result is to reduce the value of T.

: PIPELINING AND SUPER SCALAR OPERATION

We assume that instructions are executed one after the other. Hence the value of S is the total
number of basic steps, or clock cycles, required to execute one instruction. A substantial improvement
in performance can be achieved by overlapping the execution of successive instructions using a
technique called pipelining. Consider

Add R1 R2 R3

This adds the contents of R1 & R2 and places the sum into R3. The contents of R1 & R2 are
first transferred to the inputs of ALU. After the addition operation is performed, the sum is transferred
to R3. The processor can read the next instruction from the memory, while the addition operation is
being performed. Then of that instruction also uses, the ALU, its operand can be transferred to the
ALU inputs at the same time that the add instructions is being transferred to R3.

In the ideal case if all instructions are overlapped to the maximum degree possible the
execution proceeds at the rate of one instruction completed in each clock cycle. Individual instructions
still require several clock cycles to complete. But for the purpose of computing T, effective value of
S is 1.

A higher degree of concurrency can be achieved if multiple instructions pipelines are

implemented in the processor. This means that multiple functional units are used creating parallel
paths through which different instructions can be executed in parallel with such an arrangement, it
becomes possible to start the execution of several instructions in every clock cycle. This mode of
operation is called superscalar execution. If it can be sustained for a long time during program
execution the effective value of S can be reduced to less than one. But the parallel execution must
preserve logical correctness of programs, that is the results produced must be same as those produced
by the serial execution of program instructions. Now a days may processor are designed in this
manner.

: CLOCK RATE

These are two possibilities for increasing the clock rate ‘R’.
1. Improving the IC technology makes logical circuit faster, which reduces the time of execution
of basic steps. This allows the clock period P, to be reduced and the clock rate R to be
increased.
2. Reducing the amount of processing done in one basic step also makes it possible to reduce the
clock period P. however if the actions that have to be performed by an instructions remain the
same, the number of basic steps needed may increase.

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Increase in the value ‘R’ that are entirely caused by improvements in IC technology affects
all aspects of the processor’s operation equally with the exception of the time it takes to access the
main memory. In the presence of cache the percentage of accesses to the main memory is small.
Hence much of the performance gain excepted from the use of faster technology can be realized.

: INSTRUCTION SET CISC & RISC

Simple instructions require a small number of basic steps to execute. Complex instructions
involve a large number of steps. For a processor that has only simple instruction a large number of
instructions may be needed to perform a given programming task. This could lead to a large value of
‘N’ and a small value of ‘S’ on the other hand if individual instructions perform more complex
operations, a fewer instructions will be needed, leading to a lower value of N and a larger value of S.
It is not obvious if one choice is better than the other.
But complex instructions combined with pipelining (effective value of S 1) would achieve
one best performance. However, it is much easier to implement efficient pipelining in processors with
simple instruction sets.

: PERFORMANCE MEASUREMENTS

It is very important to be able to access the performance of a computer, comp designers use
performance estimates to evaluate the effectiveness of new features. The previous argument suggests that
the performance of a computer is given by the execution time T, for the program of interest.
In spite of the performance equation being so simple, the evaluation of ‘T’ is highly complex.
Moreover the parameters like the clock speed and various architectural features are not reliable indicators
of the expected performance. Hence measurement of computer performance using bench mark programs
is done to make comparisons possible, standardized programs must be used.
The performance measure is the time taken by the computer to execute a given bench mark.
Initially some attempts were made to create artificial programs that could be used as bench mark
programs. But synthetic programs do not properly predict the performance obtained when real
application programs are run. A nonprofit organization called SPEC- system performance Evaluation
Corporation selects and publishes bench marks.
The program selected range from game playing, compiler, and data base applications to
numerically intensive programs in astrophysics and quantum chemistry. In each case, the program is
compiled under test, and the running time on a real computer is measured. The same program is also
compiled and run on one computer selected as reference.
The ‘SPEC’ rating is computed as follows.

If the SPEC rating = 50, means that the computer under test is 50 times as fast as the ultra
sparc 10. This is repeated for all the programs in the SPEC suit, and the geometric mean of the result
is computed. Let SPECi be the rating for program ‘i’ in the suite. The overall SPEC rating for the
computer is given by

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Where ‘n’ = number of programs in suite.

Since actual execution time is measured the SPEC rating is a measure of the combined effect of all
factors affecting performance, including the compiler, the OS, the processor, the memory of comp
being tested.

: MEMORY LOCATIONS AND ADDRESSES

Number and character operands, as well as instructions, are stored in the memory of a
computer. The memory consists of many millions of storage cells, each of which can store a bit of
information having the value 0 or 1. Because a single bit represents a very small amount of
information, bits are seldom handled individually. The usual approach is to deal with them in groups
of fixed size. For this purpose, the memory is organized so that a group of n bits can be stored or
retrieved in a single, basic operation. Each group of n bits is referred to as a word of information, and
n is called the word length. The memory of a computer can be schematically represented as a
collection of words as shown in figure 1.4.

Modern computers have word lengths that typically range from 16 to 64 bits. If the word
length of a computer is 32 bits, a single word can store a 32-bit 2’s complement number or four ASCII
characters, each occupying 8 bits. A unit of 8 bits is called a byte.

Accessing the memory to store or retrieve a single item of information, either a word or a
byte, requires distinct names or addresses for each item location. It is customary to use numbers from
0 through 2K-1, for some suitable values of k, as the addresses of successive locations in the memory.
The 2k addresses constitute the address space of the computer, and the memory can have up to 2 k
addressable locations. 24-bit address generates an address space of 224 (16,777,216) locations. A 32-
bit address creates an address space of 232 or 4G (4 giga) locations.
: BYTE ADDRESSABILITY

We now have three basic information quantities to deal with: the bit, byte and word. A byte is
always 8 bits, but the word length typically ranges from 16 to 64 bits. The most practical assignment
is to have successive addresses refer to successive byte . Figure 1.4, Figure 1.5 and Figure 1.6 are
examples of encoding information in a 32-bit word.

: BIG-ENDIAN AND LITTLE-ENDIAN ASIGNMENTS

There are two ways that byte addresses can be assigned across words, as shown in fig b.
The name big-endian is used when lower byte addresses are used for the more significant bytes (the
leftmost bytes) of the word. The name little-endian is used for the opposite ordering, where the
lower byte addresses are used for the less significant bytes (the rightmost bytes) of the word.
In addition to specifying the address ordering of bytes within a word, it is also necessary to
specify the labeling of bits within a byte or a word. The same ordering is also used for labeling bits
within a byte, that is, b7, b6, …., b0, from left to right.

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: WORD ALIGNMENT

In the case of a 32-bit word length, natural word boundaries occur at addresses 0, 4, 8, …, as
shown in above figure. We say that the word locations have aligned addresses . in general, words are
said to be aligned in memory if they begin at a byte address that is a multiple of the number of bytes
in a word. The memory of bytes in a word is a power of 2. Hence, if the word length is 16 (2 bytes),
aligned words begin at byte addresses 0,2,4,…, and for a word length of 64 (23 bytes), aligned words
begin at bytes addresses 0,8,16 ….

Figure 1.4: Memory words

Figure 1.5: Signed integer

Figure 1.6: Four Characters

There is no fundamental reason why words cannot begin at an arbitrary byte address. In that case,
words are said to have unaligned addresses. While the most common case is to use aligned addresses,
some computers allow the use of unaligned word addresses.

: ACCESSING NUMBERS, CHARACTERS, AND CHARACTER STRINGS

A number usually occupies one word. It can be accessed in the memory by specifying its
word address. Similarly, individual characters can be accessed by their byte address.
In many applications, it is necessary to handle character strings of variable length. The
beginning of the string is indicated by giving the address of the byte containing its first character.
Successive byte locations contain successive characters of the string. There are two ways to indicate
the length of the string. A special control character with the meaning “end of string” can be used as
the last character in the string, or a separate memory word location or processor register can contain
a number indicating the length of the string in bytes.

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Figure 1.7: Byte and addressing representation

: MEMORY OPERATIONS
Both program instructions and data operands are stored in the memory. To execute an
instruction, the processor control circuits must cause the word (or words) containing the instruction
to be transferred from the memory to the processor. Operands and results must also be moved between
the memory and the processor. Thus, two basic operations involving the memory are needed, namely,
Load (or Read or Fetch) and Store (or Write).

The load operation transfers a copy of the contents of a specific memory location to the
processor. The memory contents remain unchanged. To start a Load operation, the processor sends
the address of the desired location to the memory and requests that its contents be read. The memory
reads the data stored at that address and sends them to the processor.

The store operation transfers an item of information from the processor to a specific memory
location, destroying the former contents of that location. The processor sends the address of the
desired location to the memory, together with the data to be written into that location. An information
item of either one word or one byte can be transferred between the processor and the memory in a
single operation. Actually this transfer in between the CPU register & main memory.

: INSTRUCTIONS AND INSTRUCTION SEQUENCING

A computer must have instructions capable of performing four types of operations.
Data transfers between the memory and the processor
registers Arithmetic and logic operations on data
Program sequencing and
control I/O transfers

: REGISTER TRANSFER NOTATION

Transfer of information from one location in the computer to another. Possible locations that
may be involved in such transfers are memory locations that may be involved in such transfers are
memory locations, processor registers, or registers in the I/O subsystem. Most of the time, we identify
a location by a symbolic name standing for its hardware binary address.

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Example, names for the addresses of memory locations may be LOC, PLACE, A, VAR2;
processor registers names may be R0, R5; and I/O register names may be DATAIN, OUTSTATUS,
and so on. The contents of a location are denoted by placing square brackets around the name of the
location. Thus, the expression

Means that the contents of memory location LOC are transferred into processor register R1.
As another example, consider the operation that adds the contents of registers R1 and R2, and then
places their sum into register R3. This action is indicated as
R3 [R1] + [R2]

This type of notation is known as Register Transfer Notation (RTN). Note that the right-hand
side of an RTN expression always denotes a value, and the left-hand side is the name of a location
where the value is to be places, overwriting the old contents of that location.

: ASSEMBLY LANGUAGE NOTATION

Another type of notation to represent machine instructions and programs. For this, we use an
assembly language format. For example, an instruction that causes the transfer described above,
from memory location LOC to processor register R1, is specified by the statement Move LOC, R1

The contents of LOC are unchanged by the execution of this instruction, but the old contents of
register R1 are overwritten. The second example of adding two numbers contained in processor registers
R1 and R2 and placing their sum in R3 can be specified by the assembly language statement
Add R1, R2, R3

: BASIC INSTRUCTIONS
The operation of adding two numbers is a fundamental capability in any computer. The
statement
C=A+B
In a high-level language program is a command to the computer to add the current values of
the two variables called A and B, and to assign the sum to a third variable, C. When the program
containing this statement is compiled, the three variables, A, B, and C, are assigned to distinct
locations in the memory. We will use the variable names to refer to the corresponding memory
location addresses. The contents of these locations represent the values of the three variables. Hence,
the above high-level language statement requires the action.
C [A] + [B]
To carry out this action, the contents of memory locations A and B are fetched from the
memory and transferred into the processor where their sum is computed. This result is then sent back
to the memory and stored in location C. Let us first assume that this action is to be accomplished by
a single machine instruction. Furthermore, assume that this instruction contains the memory addresses
of the three operands – A, B, and C. This three-address instruction can be represented symbolically
as
Add A, B, C
Operands A and B are called the source operands, C is called the destination operand, and Add is
the operation to be performed on the operands. A general instruction of this type has the format.
Operation Source1, Source 2, Destination

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If k bits are needed for specify the memory address of each operand, the encoded form of the
above instruction must contain 3k bits for addressing purposes in addition to the bits needed to denote
the Add operation.
An alternative approach is to use a sequence of simpler instructions to perform the same task,
with each instruction having only one or two operands. Suppose that two-address instructions of the
form
Operation Source, Destination
Are available. An Add instruction of this type is
Add A, B
Which performs the operation B [A] + [B].

A single two-address instruction cannot be used to solve our original problem, which is to
add the contents of locations A and B, without destroying either of them, and to place the sum in
location C. The problem can be solved by using another two-address instruction that copies the
contents of one memory location into another. Such an instruction is
Move B, C
Which performs the operations C [B], leaving the contents of location B unchanged.

Using only one-address instructions, the operation C [A] + [B] can be performed by executing
the sequence of instructions
Load A
Add B
Store C
Some early computers were designed around a single accumulator structure. Most modern
computers have a number of general-purpose processor registers – typically 8 to 32, and even
considerably more in some cases. Access to data in these registers is much faster than to data stored
in memory locations because the registers are inside the processor. Let R i represent a general-
purpose register. The instructions
Load A, Ri
Store Ri, A and
Add A, Ri
Are generalizations of the Load, Store, and Add instructions for the single-accumulator case,
in which register Ri performs the function of the accumulator. When a processor has several general-
purpose registers, many instructions involve only operands that are in the register. In fact, in many
modern processors, computations can be performed directly only on data held in processor registers.
Instructions such as
Add Ri, Rj
Or
Add Ri, Rj, Rk
In both of these instructions, the source operands are the contents of registers Ri and Rj. In
the first instruction, Rj also serves as the destination register, whereas in the second instruction, a
third register, Rk, is used as the destination.
It is often necessary to transfer data between different locations. This is achieved with the
instruction
Move Source, Destination
When data are moved to or from a processor register, the Move instruction can be used rather
than the Load or Store instructions because the order of the source and destination operands
determines which operation is intended. Thus,

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Move A, Ri
Is the same as
Load A, Ri
And
Move Ri, A
Is the same as
Store Ri, A
In processors where arithmetic operations are allowed only on operands that are processor
registers, the C = A + B task can be performed by the instruction sequence
Move A, Ri
Move B, Rj
Add Ri, Rj
Move Rj, C
In processors where one operand may be in the memory but the other must be in register, an
instruction sequence for the required task would be
Move A, Ri
Add B, Ri
Move Ri, C
The speed with which a given task is carried out depends on the time it takes to transfer
instructions from memory into the processor and to access the operands referenced by these
instructions. Transfers that involve the memory are much slower than transfers within the processor.
We have discussed three-, two-, and one-address instructions. It is also possible to use
instructions in which the locations of all operands are defined implicitly. Such instructions are found
in machines that store operands in a structure called a pushdown stack. In this case, the instructions
are called zero-address instructions.

: INSTRUCTION EXECUTION AND STRAIGHT-LINE SEQUENCING

In the preceding discussion of instruction formats, we used to task C [A] + [B]. Figure 1.8
.shows a possible program segment for this task as it appears in the memory of a computer. We have
assumed that the computer allows one memory operand per instruction and has a number of processor
registers. The three instructions of the program are in successive word locations, starting at location
i. since each instruction is 4 bytes long, the second and third instructions start at addresses i + 4 and i
+ 8.
Let us consider how this program is executed. The processor contains a register called the
program counter (PC), which holds the address of the instruction to be executed next. To begin
executing a program, the address of its first instruction (I in our example) must be placed into the PC.
Then, the processor control circuits use the information in the PC to fetch and execute instructions,
one at a time, in the order of increasing addresses. This is called straight-line sequencing. During the
execution of each instruction, the PC is incremented by 4 to point to the next instruction. Thus, after
the Move instruction at location i + 8 is executed, the PC contains the value i + 12, which is the
address of the first instruction of the next program segment.
Executing a given instruction is a two-phase procedure. In the first phase, called instruction fetch,
the instruction is fetched from the memory location whose address is in the PC. This instruction is placed
in the instruction register (IR) in the processor. The instruction in IR is examined to

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determine which operation is to be performed. The specified operation is then performed by the
processor. This often involves fetching operands from the memory or from processor registers,
performing an arithmetic or logic operation, and storing the result in the destination location.

Figure 1.8 : A program for C <- [A] +[B]

Figure 1.9: A straight program for adding n numbers.

: BRANCHING
Consider the task of adding a list of n numbers. Instead of using a long list of add instructions,
it is possible to place a single add instruction in a program loop, as shown in figure b. The loop is a
straight-line sequence of instructions executed as many times as needed. It starts at location LOOP
and ends at the instruction Branch > 0. During each pass through this loop, the address of the next list
entry is determined, and that entry is fetched and added to R0

Assume that the number of entries in the list, n, is stored in memory location N, as shown.
Register R1 is used as a counter to determine the number of time the loop is executed. Hence, the
contents of location N are loaded into register R1 at the beginning of the program. Then, within the
body of the loop, the instruction.

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Decrement R1

Reduces the contents of R1 by 1 each time through the loop. This type of instruction loads a new
value into the program counter. As a result, the processor fetches and executes the instruction at this
new address, called the branch target, instead of the instruction at the location that follows the branch
instruction in sequential address order. A conditional branch instruction causes a branch only if a
specified condition is satisfied. If the condition is not satisfied, the PC is incremented in the normal
way, and the next instruction in sequential address order is fetched and executed.

Branch > 0 LOOP

Figure 1.10: Using a loop to add n numbers

Branch if greater than 0 is a conditional branch instruction that causes a branch to location LOOP if
the result of the immediately preceding instruction, which is the decremented value in register R1, is
greater than zero. This means that the loop is repeated, as long as there are entries in the list that are
yet to be added to R0. At the end of the nth pass through the loop, the Decrement instruction produces
a value of zero, and hence, branching does not occur.

: CONDITION CODES
The processor keeps track of information about the results of various operations for use by
subsequent conditional branch instructions. This is accomplished by recording the required information
in individual bits, often called condition code flags. These flags are usually grouped together in a special
processor register called the condition code register or status register. Individual condition code flags are
set to 1 or cleared to 0, depending on the outcome of the operation performed.

Four commonly used flags are

N(negative) Set to 1 if the result is negative; otherwise, cleared to 0
Z(zero) Set to 1 if the result is 0; otherwise, cleared to 0
V(overflow) Set ot1 if arithmetic overflow occurs; otherwise, cleared to 0
C(carry) Set to 1 if a carry-out results from the operation; otherwise, cleared to 0

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The instruction Branch > 0, discussed in the previous section, is an example of a branch
instruction that tests one or more of the condition flags. It causes a branch if the value tested is neither
negative nor equal to zero. That is, the branch is taken if neither N nor Z is 1. The conditions are
given as logic expressions involving the condition code flags.

In some computers, the condition code flags are affected automatically by instructions that
perform arithmetic or logic operations. However, this is not always the case. A number of computers
have two versions of an Add instruction.

GENERATING MEMORY ADDRESSES

Let us return to figure 1.10. The purpose of the instruction block at LOOP is to add a different
number from the list during each pass through the loop. Hence, the Add instruction in the block must
refer to a different address during each pass. How are the addresses to be specified? The memory
operand address cannot be given directly in a single Add instruction in the loop. Otherwise, it would
need to be modified on each pass through the loop.
The instruction set of a computer typically provides a number of such methods, called
addressing modes. While the details differ from one computer to another, the underlying concepts are
the same.

ADDRESSING MODES
In general, a program operates on data that reside in the computer’s memory. These data can be
organized in a variety of ways. If we want to keep track of students’ names, we can write them in a list.
Programmers use organizations called data structures to represent the data used in computations. These include
lists, linked lists, arrays, queues, and so on.
Programs are normally written in a high-level language, which enables the programmer to use
constants, local and global variables, pointers, and arrays. The different ways in which the location of an
operand is specified in an instruction are referred to as addressing modes.

Table 1 Generic addressing modes

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REGISTER ,ABSOLUTE, IMMEDIATE ADDRESSING

MODE (Implementation Of Variable And Constants)

Variables and constants are the simplest data types and are found in almost every computer program.
In assembly language, a variable is represented by allocating a register or memory location to hold its value.
Thus, the value can be changed as needed using appropriate instructions.
Register Mode:
EA: The operand is the contents of a processor register. The name address of the register is given in the
instruction.
Absolute Mode:
EA: The operand is in a memory location, the address of this location is given explicitly in the instruction. This
mode is called Direct).
Example for both register and absolute addressing modes is as follows:
Move LOC, R2
Processor registers are used as temporary storage locations where the data is a register are accessed
using the Register mode. The Absolute mode can represent global variables in a program. A declaration such
as
Integer A, B;
Immediate mode: The operand is given explicitly in the instruction. For example, the instruction
Move 200immediate, R0
Places the value 200 in register R0. Clearly, the immediate mode is only used to specify the value of
a source operand. Using a subscript to denote the immediate mode is not appropriate in assembly languages.
A common convention is to use the sharp sign (#) in front of the value to indicate that this value is to be used
as an immediate operand. Hence, we write the instruction above in the form
Move #200, R0
Register and Direct modes are used for accessing variables and immediate mode for constants.
INDIRECT MODE (POINTERS)
In this addressing modes the instruction does not give the operand, instead, it provides information
from which the memory address of the operand can be determined. We refer to this address as the effective
address (EA) of the operand.
EA : The effective address of the operand is the contents of a register or memory location whose address
appears in the instruction. EA= [Ri] / [LOC A]
To execute the Add instruction in figure 1.11 (a), the processor uses the value which is in register R1,
as the effective address of the operand. It requests a read operation from the memory to read the contents of
location B. the value read is the desired operand, which the processor adds to the contents of register R0.
Indirect addressing through a memory location is also possible as shown in figure 1.11 (b). In this case, the
processor first reads the contents of memory location A, then requests a second read operation using the value
B as an address to obtain the operand.

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Figure 1.11: (a) Through a general-purpose register (b) Through a memory location

Figure 1.12: Program to explain indirect addressing mode

The register or memory location that contains the address of an operand is called a pointer. Indirection and the
use of pointers are important and powerful concepts in programming.
In the program shown in figure 1.12, Register R2 is used as a pointer to the numbers in the list, and
the operands are accessed indirectly through R2. The initialization section of the program loads the counter
value n from memory location N into R1 and uses the immediate addressing mode to place the address value
NUM1, which is the address of the first number in the list, into R2. Then it clears R0 to 0. The first two
instructions in the loop implement the unspecified instruction block starting at LOOP. The first time through
the loop, the instruction Add (R2), R0 fetches the operand at location NUM1 and adds it to R0. The second
Add instruction adds 4 to the contents of the pointer R2, so that it will contain the address value NUM2 when
the above instruction is executed in the second pass through the loop. Where B is a pointer variable. This
statement may be compiled into
Move B, R1
Move (R1), A
Using indirect addressing through memory, the same action can be achieved with
Move (B), A
Indirect addressing through registers is used extensively. The above program shows the flexibility it
provides. Also, when absolute addressing is not available, indirect addressing through registers makes it
possible to access global variables by first loading the operand’s address in a register.

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INDEXING, BASE WITH INDEX, BASE WITH INDEX AND OFFSET

ADDRESSING MODES (ARRAYS AND STRUCTURES, LIST)
Index mode:
EA: The effective address of the operand is generated by adding a constant value to the contents of a
register. EA = X + [Rj]
The register use may be either a special register provided for this purpose, or, more commonly, it may
be any one of a set of general-purpose registers in the processor. In either case, it is referred to as index register.
We indicate the Index mode symbolically as

X (Ri)
Where X denotes the constant value contained in the instruction and Ri is the name of the register
involved.
The contents of the index register are not changed in the process of generating the effective address.
In an assembly language program, the constant X may be given either as an explicit number or as a symbolic
name representing a numerical value.
Figure 1.17 illustrates two ways of using the Index mode. In figure 1.15(a) the index register, R1,
contains the address of a memory location, and the value X defines an offset (also called a displacement) from
this address to the location where the operand is found. An alternative use is illustrated in figure 1.15(b). Here,
the constant X corresponds to a memory address, and the contents of the index register define the offset to the
operand. In either case, the effective address is the sum of two values; one is given explicitly in the instruction,
and the other is stored in a register.

Figure 1.15. (a) Offset is given as a constant (b) Offset is in the index register
The assembly code for finding total of Marks1,Marks2 , Marks3 and storing in memory location Total Marks
is as shown in the figure 1.16

Base with Index :

EA:The effective address is the sum of the contents of registers Ri and Rj. The second register is usually called
the base register. EA = [Ri]+[Rj]
In the most basic form of indexed addressing several variations of this basic form provide a very
efficient access to memory operands in practical programming situations. For example, a second register may
be used to contain the offset X, in which case we can write the Index mode as
(Ri, Rj)

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This form of indexed addressing provides more flexibility in accessing operands, because both
components of the effective address can be changed. we have only Marks1,Marks2,Marks3 in figure 1.18 if it
have 10 subject marks(Marks1-Marks10) then indexing mode will not be an appropriate one, instead we can
use Base with Index mode as shown in figure 1.18 .f

Figure 1.16: Memory allocation for Student list

Figure 1.17: Program for adding all marks and storing in total marks using index addressing mode
Base With Index And Offset:
EA: The effective address is the sum of the constant X and the contents of registers Ri and Rj.
EA =X + [Ri]+[Rj]
Another version of the Index mode uses two registers plus a constant, which can be denoted as
X (Ri, Rj)
This added flexibility is useful in accessing multiple components inside each item in a record, where
the beginning of an item is specified by the (Ri, Rj) part of the addressing mode. In other words, this mode
implements a three-dimensional array.
RELATIVE ADDRESSING
EA: The effective address is determined by the Index mode using the program counter in place of the general-
purpose register Ri. EA= X+[PC]
We have defined the Index mode using general-purpose processor registers. A useful version of this
mode is obtained if the program counter, PC, is used instead of a general purpose register. Then, X(PC) can be
used to address a memory location that is X bytes away from the location presently pointed to by the program
counter.

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Figure 1.18: Program for adding all marks and storing in total marks using Base with Index addressing mode

: AUTOINCREMENT MODE
EA: The effective address of the operand is the contents of a register specified in the instruction. After accessing the
operand, the contents of this register are automatically to point to the next item in a list. EA=[Ri]
(Ri)+
Figure 1.22 Illustrate the use of autoincrement mode. It uses the register R2 and then increments its value. If
the content of the register is an address then it increments by 4, by 1 for character and byte operand, increments
by 2 for 16-bit operand.
: AUTODECREMENT MODE
EA: The contents of a register specified in the instruction are first automatically decremented and are then
used as the effective address of the operand. EA= [Ri]- 4

-(Ri)
Autodecrement works in same as autoincrements except it first decrements and then it uses the value in the
program.

Figure 1.20: Example program the Autoincrement addressing mode

ASSEMBLY LANGUAGE
Machine instructions are represented by patterns of 0s and 1s. Such patterns are awkward to deal with when
discussing or preparing programs. Therefore, we use symbolic names to represent the pattern. So far, we have used
normal words, such as Move, Add, Increment, and Branch, for the instruction operations to represent the
corresponding binary code patterns. When writing programs for a specific computer, such words are normally
replaced by acronyms called mnemonics, such as MOV, ADD, INC, and BR. Similarly, we use the notation R3 to
refer to register 3, and LOC to refer to a memory location. A complete set of such symbolic names and rules for
their use constitute a programming language, generally referred to as an assembly language.

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Programs written in an assembly language can be automatically translated into a sequence of machine
instructions by a program called an assembler. When the assembler program is executed, it reads the user
program, analyzes it, and then generates the desired machine language program. The latter contains patterns of
0s and 1s specifying instructions that will be executed by the computer. The user program in its original
alphanumeric text format is called a source program, and the assembled machine language program is called
an object program.
ASSEMBLER DIRECTIVE:
In addition to providing a mechanism for representing instructions in a program, the assembly
language allows the programmer to specify other information needed to translate the source program into the
object program. We have already mentioned that we need to assign numerical values to any names used in a
program. Suppose that the name SUM is used to represent the value 200. This fact may be conveyed to the
assembler program through a statement such as
SUM EQU 200
This statement does not denote an instruction that will be executed when the object program is run; in
fact, it will not even appear in the object program. It simply informs the assembler that the name SUM should
be replaced by the value 200 wherever it appears in the program. Such statements, called assembler directives
(or commands), are used by the assembler while it translates a source program into an object program. Some
of the other assembler directives are listed in table 2.

ASSEMBLY AND EXECUTION OF PRGRAMS:

A source program written in an assembly language must be assembled into a machine language object
program before it can be executed. This is done by the assembler program, which replaces all symbols denoting
operations and addressing modes with the binary codes used in machine instructions, and replaces all names
and labels with their actual values.
The assembler assigns addresses to instructions and data blocks, starting at the address given in the
ORIGIN assembler directives. It also inserts constants that may be given in DATAWORD commands and
reserves memory space as requested by RESERVE commands.
As the assembler scans through a source programs, it keeps track of all names and the numerical values that
correspond to them in a symbol table. Thus, when a name appears a second time, it is replaced with its value
from the table. A problem arises when a name appears as an operand before it is given a value. For example,
this happens if a forward branch is required. A simple solution to this problem is to have the assembler scan
through the source program twice. During the first pass, it creates a complete symbol table. At the end of this
pass, all names will have been assigned numerical values. The assembler then goes through the source program
a second time and substitutes values for all names from the symbol table. Such an assembler is called a two-
pass assembler.
The assembler stores the object program on a magnetic disk. The object program must be loaded into
the memory of the computer before it is executed. For this to happen, another utility program called a loader
must already be in the memory.
When the object program begins executing, it proceeds to completion unless there are logical errors in the
program. The user must be able to find errors easily. The assembler can detect and report syntax errors. To
help the user find other programming errors, the system software usually includes a debugger program. This
program enables the user to stop execution of the object program at some points of interest and to examine the
contents of various processor registers and memory locations.

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Table .2: List of few Assembler Directives

NUMBER NOTATION:
When dealing with numerical values, it is often convenient to use the familiar decimal notation. Of
course, these values are stored in the computer as binary numbers. In some situations, it is more convenient to
specify the binary patterns directly. Most assemblers allow numerical values to be specified in different ways,
using conventions that are defined by the assembly language syntax. Consider, for example, the number 93,
which is represented by the 8-bit binary number 01011101. If this value is to be used an immediate operand, it
can be given as a decimal number, as in the instructions.
ADD #93, R1
Or as a binary number identified by a prefix symbol such as a percent sign, as in
ADD #%01011101, R1
Binary numbers can be written more compactly as hexadecimal, or hex, numbers, in which four bits
are represented by a single hex digit. In hexadecimal representation, the decimal value 93 becomes 5D. In
assembly language, a hex representation is often identified by a dollar sign prefix. Thus, we would write
ADD #$5D, R1

BASIC INPUT/OUTPUT OPERATIONS

Input/Output (I/O) operations are essential, and the way they are performed can have a significant
effect on the performance of the computer. Consider a task that reads in character input from a keyboard and
produces character output on a display screen. A simple way of performing such I/O tasks is to use a method
known as program-controlled I/O.
The rate of data transfer from the keyboard to a computer or Computer to display is limited by the
typing speed of the user and, which is unlikely to exceed a few characters per second which is much slower
than the speed of a processor that can execute many millions of instructions per second. The difference in speed
between the processor and I/O devices creates the need for mechanisms to synchronize the transfer of data
between them. (Inserting Buffer is one way to overcome the problem).

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The keyboard and the display are separate device as shown in figure 1.23. The action of striking a key
on the keyboard does not automatically cause the corresponding character to be displayed on the screen. One
block of instructions in the I/O program transfers the character into the processor, and another associated block
of instructions causes the character to be displayed.
Striking a key stores the corresponding character code in an 8-bit buffer register associated with the keyboard. Let
us call this register DATAIN, as shown in figure2.9. To inform the processor that a valid character is in DATAIN,
a status control flag, SIN, is set to 1. A program monitors SIN, and when SIN is set to 1, the processor reads the
contents of DATAIN. When the character is transferred to the processor, SIN is automatically cleared to 0. If a
second character is entered at the keyboard, SIN is again set to 1, and the processor repeats.

Figure 1.21: BUS connection for Processor, Keyboard and Display

An analogous process takes place when characters are transferred from the processor to the
display. A buffer register, DATAOUT, and a status control flag, SOUT, are used for this transfer. When SOUT
equals 1, the display is ready to receive a character. The assembly code for reading character and display it is
as shown in Figure 1.22.
Address issued by the processor to access instruction and operand for I/O devices always refer to the
memory locations i.e., some memory address values used to refer to peripheral device buffer registers,such as
DATAIN and DATAOUT .such an arrangement is called as an memory mapped I/O. SIN and SOUT are
included in the device registers usually at 3rd bit. SIN/SOUT along with buffer registers DATAIN/DATAOUT
is called as device interface.

STACKS AND QUEUES:

A stack is a list of data elements, usually words or bytes, with the accessing restriction that
elements can be added or removed at one end of the list only. This end is called the top of the stack, and the
other end is called the bottom. Another descriptive phrase, last-in-first-out (LIFO) stack, is also used to describe
this type of storage mechanism; the last data item placed on the stack is the first one removed when retrieval
begins. The terms push and pop are used to describe placing a new item on the stack and removing the top item
from the stack, respectively.
Figure 1.23 shows a stack of word data items in the memory of a computer. A processor register is
used to keep track of the address of the element of the stack that is at the top at any given time. This register is
called the stack pointer (SP). Byte addressability (32 bit word) the PUSH and POP operation would be as sown
in figure 1.24
While working with stack we must avoid pushing an item on to the stack when the stack has reached
its maximum size and poping the item of an empty stack which will result in a programming error. The care is
taken by the comparing bottom/top address of the stack with address contained in stack pointer.

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Compare instruction CMP src, dest or Compare src, dest

Performs the operation [dest]- [src] based on the result the flags will be set but either of the operand value is
not changed due to compare instruction execution.

Figure 1.22: program for read line from the keyboard and display it.

Figure 1.23: Stack of words in memory

Figure 1.24: Program for safe push and pop operation

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Another useful data structure that is similar to the stack is called a queue. Data are stored in and
retrieved from a queue on a first-in-first-out (FIFO) basis. Thus, if we assume that the queue grows in the
direction of increasing addresses in the memory, which is a common practice, new data are added at the back
(high-address end) and retrieved from the front (low-address end) of the queue.

SUBROUTINES
In a given program, it is often necessary to perform a particular subtask many times on different data-
values. Such a subtask is usually called a subroutine. For example, a subroutine may evaluate the sine function
or sort a list of values into increasing or decreasing order.
It is possible to include the block of instructions that constitute a subroutine at every place where it is
needed in the program. However, to save space, only one copy of the instructions that constitute the subroutine
is placed in the memory, and any program that requires the use of the subroutine simply branches to its starting
location. When a program branches to a subroutine we say that it is calling the subroutine. The instruction that
performs this branch operation is named a Call instruction.
After a subroutine has been executed, the calling program must resume execution, continuing
immediately after the instruction that called the subroutine. The subroutine is said to return to the program that
called it by executing a Return instruction.
The way in which a computer makes it possible to call and return from subroutines is referred to as its
subroutine linkage method. The simplest subroutine linkage method is to save the return address in a specific
location, which may be a register dedicated to this function. Such a register is called the link register. When
the subroutine completes its task, the Return instruction returns to the calling program by branching indirectly
through the link register. Figure 1.27 illustrate how the link register works in proper execution of program with
subroutines.
The Call instruction is just a special branch instruction that performs the following operations
Store the contents of the PC in the link register
Branch to the target address specified by the instruction
The Return instruction is a special branch instruction that performs the operation
Branch to the address contained in the link register

Figure 1.25: Subroutine linkage using a link register.

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SUBROUTINE NESTING AND THE PROCESSOR STACK

A common programming practice, called subroutine nesting, is to have one subroutine call another.
In this case, the return address of the second call is also stored in the link register, destroying its previous
contents. Hence, it is essential to save the contents of the link register in some other location before calling
another subroutine. Otherwise, the return address of the first subroutine will be lost.
Subroutine nesting can be carried out to any depth. Eventually, the last subroutine called completes
its computations and returns to the subroutine that called it. The return address needed for this first return is
the last one generated in the nested call sequence. That is, return addresses are generated and used in a last-in-
first-out order. This suggests that the return addresses associated with subroutine calls should be pushed onto
a stack. A particular register is designated as the stack pointer, SP, to be used in this operation.
The stack pointer points to a stack called the processor stack. The Call instruction pushes the contents
of the PC onto the processor stack and loads the subroutine address into the PC. The Return instruction pops
the return address from the processor stack into the PC.
PARAMETER PASSING
When calling a subroutine, a program must provide to the subroutine the parameters, that is, the
operands or their addresses, to be used in the computation. Later, the subroutine returns other parameters, in
this case, the results of the computation. This exchange of information between a calling program and a
subroutine is referred to as parameter passing. Parameter passing may be accomplished in several ways. The
parameters may be placed in registers or in memory locations, where they can be accessed by the subroutine
as shown in figure 1.26. Alternatively, the parameters may be placed on the processor stack used for saving
the return address as shown in figure 1.27

Figure 1.26: Parameter passing through register for program in figure 1.20
The purpose of the subroutines is to add a list of numbers. Instead of passing the actual list entries, the
calling program passes the address of the first number in the list. This technique is called passing by reference. The
second parameter is passed by value, that is, the actual number of entries, n, is passed to the subroutine.
THE STACK FRAME
Now we observe how space is used in the stack in the example. During execution of the subroutine,
six locations at the top of the stack contain entries that are needed by the subroutine. These locations constitute
a private workspace for the subroutine, created at the time the subroutine is entered and freed up when the
subroutine returns control to the calling program. Such space is called a stack frame.

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Figure 1.27: Parameter passing through stack for program in figure 1.20

Figure 1.28: A subroutine stack frame example

Figure 1.28 shows an example of a commonly used layout for information in a stack frame. In addition
to the stack pointer SP, it is useful to have another pointer register, called the frame pointer (FP), for convenient
access to the parameters passed to the subroutine and to the local memory variables used by the subroutine.
These local variables are only used within the subroutine, so it is appropriate to allocate space for them in the
stack frame associated with the subroutine. We assume that four parameters are passed to the subroutine, three
local variables are used within the subroutine, and registers R0 and R1 need to be saved because they will also
be used within the subroutine.
The pointers SP and FP are manipulated as the stack frame is built, used, and dismantled for a particular
subroutine. We begin by assuming that SP point to the old top-of-stack (TOS) element in figure 1.30 Before the
subroutine is called, the calling program pushes the four parameters onto the stack. The call instruction is then
executed, resulting in the return address being pushed onto the stack. Now, SP points to this return address, and the
first instruction of the subroutine is about to be executed. This is the point at which the

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frame pointer FP is set to contain the proper memory address. Since FP is usually a general-purpose register, it
may contain information of use to the Calling program. Therefore, its contents are saved by pushing them onto
the stack. Since the SP now points to this position, its contents are copied into FP. Thus, the first two
instructions executed in the subroutine are
Move FP, -(SP)
Move SP, FP
After these instructions are executed, both SP and FP point to the saved FP contents.
Subtract #12, SP
Finally, the contents of processor registers R0 and R1 are saved by pushing them onto the stack. At
this point, the stack frame has been set up as shown in the fig.
The subroutine now executes its task. When the task is completed, the subroutine pops the saved values
of R1 and R0 back into those registers, removes the local variables from the stack frame by executing the
instruction.
Add #12, SP
And pops the saved old value of FP back into FP. At this point, SP points to the return address, so the
Return instruction can be executed, transferring control back to the calling program.

Stack Frames For Nested Subroutines

The stack is a proper data structure for holding return addresses when subroutines are nested. It should be
clear that the stack frames for the nested subroutines build upon the processor stack as they are called. In this
regard, the saved contents of FP in the current frame at the top of the stack are the FP contents for the stack
frame of the subroutine that called the current subroutine.
An example of main program calling a first subroutine SUB1, which intern calls the second subroutine SUB2
is shown in the figure 1.30. The stack frame corresponding to these two nested subroutines are shown in the
figure 1.29.

Figure 1.29: Stack frame for the program given in figure 1.30

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Figure 1.30: program with Nested Subroutines

ADDITIONAL INSTRUCTIONS
Along with arithmetic instructions like ADD, SUB and instructions like MOVE, COMPARE
assembly level language is provided with special instructions for programming as given in the following
sections.
LOGICAL INSTRUCTIONS
Logical operators like AND, OR and NOT are applied to integer bits are the basic building blocks of
digital circuits. It is also useful to be able to perform logical operations in soft wares, which is done using
instructions that apply these operations to all bits of an word or byte independently in parallel. Example
instructions are as shown in figure 1.29
Example 1:
NOT LOC
Compliments all bits of the value stored in the location LOC .NOT instruction is used in taking 2’s compliment
of an number. First take 1’s compliment using NOT and then add 1 to it.

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NOT LOC
ADD #1,LOC

Example 2: NEGATE LOC

Takes 2’s compliment for the value in stored in LOC and stores back in LOC.

SHIFT AND ROTATE INSTRUCTIONS

There are many applications that require the bits of an operand to be shifted right or left some specified
number of bit positions. The details of how the shifts are performed depend on whether the operand is a signed
number or some more general binary-coded information. For general operands, we use a logical shift. For a
number, we use an arithmetic shift, which preserves the sign of the number.
Logical shifts
Two logical shift instructions are needed, one for shifting left (LShiftL) and another for shifting right
(LShiftR). These instructions shift an operand over a number of bit positions specified in a count operand
contained in the instruction. The general form of a logical left shift instruction is
LShiftL count, dst
The figure 1.32 shows working few logical shift operations.
Rotate Operations
In the shift operations , the bit shifted out of the operand are lost, except lost for the bit shifted out
which is retained in the carry flag C. To preserve all bits a set of rotation instructions can be used. They move
the bits that re shifted out of the one end to the other. The versions of both left and right rotate instruction are
provided by the assembly level language. The examples are as shown in the figure 1.34.

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Figure 1.31: Logical and arithmetic shift instructions

Figure 1.32: Examples of rotate instructions

ENCODING OF MACHINE INSTRUCTIONS

We have introduced a variety of useful instructions and addressing modes. These instructions specify the
actions that must be performed by the processor circuitry to carry out the desired tasks. We have often referred to
them as machine instructions. Actually, the form in which we have presented the instructions is indicative of the
form used in assembly languages, except that we tried to avoid using acronyms for the various operations, which
are awkward to memorize and are likely to be specific to a particular commercial processor.

To be executed in a processor, an instruction must be encoded in a compact binary pattern. Such encoded instructions
are properly referred to as machine instructions. The instructions that use symbolic names and acronyms are called
assembly language instructions, which are converted into the machine instructions using the assembler program. We
have seen instructions that perform operations such as add, subtract, move, shift, rotate, and branch. These
instructions may use operands of different sizes, such as 32-bit and 8-bit numbers or 8-bit ASCII-encoded characters.
The type of operation that is to be performed and the type of operands used may be specified using an encoded
binary pattern referred to as the OP code for the given instruction.

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Suppose that 8 bits are allocated for this purpose, giving 256 possibilities for specifying different instructions.
This leaves 24 bits to specify the rest of the required information.
Let us examine some typical cases. The instruction
Add R1, R2
Has to specify the registers R1 and R2, in addition to the OP code. If the processor has 16 registers, then four
bits are needed to identify each register. Additional bits are needed to indicate that the Register addressing
mode is used for each operand. The instruction
Move 24(R0), R5
Requires 16 bits to denote the OP code and the two registers, and some bits to express that the source operand
uses the Index addressing mode and that the index value is 24. The shift instruction
LShiftR #2, R0
And the move instruction
Move #$3A, R1
Have to indicate the immediate values 2 and #$3A, respectively, in addition to the 18 bits used to
specify the OP code, the addressing modes, and the register. This limits the size of the immediate operand to
what is expressible in 14 bits.

Consider next the branch instruction

Branch >0 LOOP
Again, 8 bits are used for the OP code, leaving 24 bits to specify the branch offset. Since the offset is
a 2’s-complement number, the branch target address must be within 223 bytes of the location of the branch
instruction. To branch to an instruction outside this range, a different addressing mode has to be used, such as
Absolute or Register Indirect. Branch instructions that use these modes are usually called Jump instructions.
In all these examples, the instructions can be encoded in a 32-bit word. Depicts a possible format.
There is an 8-bit Op-code field and two 7-bit fields for specifying the source and destination operands. The 7-
bit field identifies the addressing mode and the register involved (if any). The “Other info” field allows us to
specify the additional information that may be needed, such as an index value or an immediate operand.
But, what happens if we want to specify a memory operand using the Absolute addressing mode? The
instruction
Move R2, LOC
Requires 18 bits to denote the OP code, the addressing modes, and the register. This leaves 14 bits to
express the address that corresponds to LOC, which is clearly insufficient.
And #$FF000000. R2
In which case the second word gives a full 32-bit immediate operand.
If we want to allow an instruction in which two operands can be specified using the Absolute
addressing mode, for example
Move LOC1, LOC2
Then it becomes necessary to use tow additional words for the 32-bit addresses of the operands.
This approach results in instructions of variable length, dependent on the number of operands and the type
of addressing modes used. Using multiple words, we can implement quite complex instructions, closely resembling
operations in high-level programming languages. The term complex instruction set computer

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(CISC) has been used to refer to processors that use instruction sets of this type. The restriction that an
instruction must occupy only one word has led to a style of computers that have become known as reduced
instruction set computer (RISC). The RISC approach introduced other restrictions, such as that all manipulation
of data must be done on operands that are already in processor registers. This restriction means that the above
addition would need a two-instruction sequence
Move (R3), R1
Add R1, R2
If the Add instruction only has to specify the two registers, it will need just a portion of a 32-bit word.
So, we may provide a more powerful instruction that uses three operands
Add R1, R2, R3
Which performs the operation
R3 [R1] + [R2]

A possible format for such an instruction in shown in figure 1.21. Of course, the processor has to be
able to deal with such three-operand instructions. In an instruction set where all arithmetic and logical
operations use only register operands, the only memory references are made to load/store the operands
into/from the processor registers.

Figure 1.33: Encoding instructions into 32-bit words

RISC-type instruction sets typically have fewer and less complex instructions than CISC-type sets.
We will discuss the relative merits of RISC and CISC approaches which deals with the details of processor
design.

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