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Class - Analog CMOS Design & Tech - Part-11

The document discusses operational amplifiers including: 1) how the output voltage is determined when the two input voltages are equal, 2) the input common mode range and how it is determined, 3) the output voltage swing and how it is determined, 4) an example calculation of the maximum permissible input voltage range for a unity gain buffer, 5) the expression for closed loop output impedance of a unity gain buffer, and 6) assigning a homework problem to derive expressions for dc gain, input common mode range, and output voltage swing for an OTA with a PMOS input pair.

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Mainuddin Mondal
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43 views7 pages

Class - Analog CMOS Design & Tech - Part-11

The document discusses operational amplifiers including: 1) how the output voltage is determined when the two input voltages are equal, 2) the input common mode range and how it is determined, 3) the output voltage swing and how it is determined, 4) an example calculation of the maximum permissible input voltage range for a unity gain buffer, 5) the expression for closed loop output impedance of a unity gain buffer, and 6) assigning a homework problem to derive expressions for dc gain, input common mode range, and output voltage swing for an OTA with a PMOS input pair.

Uploaded by

Mainuddin Mondal
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Course code: ET/PC/B/T/316

Analog CMOS Design &


Technology
Part-11
Sep 2023

Dr. Joydeep Basu, Assistant Professor


Dept. of Electronics & Telecommunication Engg., Jadavpur University
https://jadavpuruniversity.in/faculty-profile/joydeep-basu
Op-amp Output Voltage
 What is 𝑉𝑜𝑢𝑡 when 𝑉𝑖𝑛,1 = 𝑉𝑖𝑛,2 ?

𝑉𝑜𝑢𝑡 = 𝑉𝐴 = 𝑉𝐷𝐷 − 𝑉𝑆𝐺,3


A
 Can be proved by contradiction (e.g., assuming 𝑉𝑜𝑢𝑡 < 𝑉𝐴 )

For any value


within ICMR

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 2


Op-amp ICMR
 Permissible range of i/p CM voltage:
 For 𝑉𝐼,𝐶𝑀 (max): there are two paths from 𝑉𝐼,𝐶𝑀 to 𝑉𝐷𝐷

 G1  M1  M3  𝑉𝐷𝐷 :

𝑉𝐼,𝐶𝑀 ≤ 𝑉𝐷𝐷 − 𝑉𝑆𝐺,3 + 𝑉𝑇𝐻,𝑛

 G2  M2  M4  𝑉𝐷𝐷 :
𝑉𝐼,𝐶𝑀 ≤ 𝑉𝐷𝐷 − 𝑉𝑂𝑉,4 + 𝑉𝑇𝐻,𝑛

 For 𝑉𝐼,𝐶𝑀 (min): for saturation of M5:


𝑉𝐼,𝐶𝑀 ≥ 𝑉𝐺𝑆,1 + 𝑉𝑂𝑉,5

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 3


Op-amp Output Swing
 Maximum range of o/p voltage swing:
 For saturation of M2:
𝑉𝑜𝑢𝑡 ≥ 𝑉𝐼,𝐶𝑀 − 𝑉𝑇𝐻,𝑛

 For saturation of M4:


𝑉𝑜𝑢𝑡 ≤ 𝑉𝐷𝐷 − 𝑉𝑂𝑉,4

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 4


Op-amp in Closed-loop
Exercise-1:
For the unity-gain buffer realized using single-stage (5T) OTA, calculate the max
permissible voltage range of i/p.
Assume VTH=0.3 V and VOV=0.1 V for all transistors.

ANS: 𝑉𝑖𝑛 𝑚𝑖𝑛 = 𝑉𝐺𝑆,1 + 𝑉𝑂𝑉,5


𝑉𝑖𝑛 𝑚𝑎𝑥 = 𝑉𝐷𝐷 − 𝑉𝑆𝐺,3 + 𝑉𝑇𝐻,𝑛 M5

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 5


Op-amp in Closed-loop
Exercise-2:
For the unity-gain buffer realized using single-stage (5T) OTA, find the expression of
the closed-loop output impedance.

ANS: Voltage-series f/b  o/p impedance


reduces  divided by (1 + 𝐴 ∙ 𝛽) M5

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 6


Op-amp w/ PMOS Input-Pair
Home Exercise:
For the 5T OTA with PMOS input-pair, derive expressions for the dc-gain, ICMR, and
o/p voltage swing.

J. Basu Image: P. Allen and D. Holberg, CMOS Analog Circuit Design 7

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