Journal of Remote Sensing & GIS Review Article

Minimizing the Delay of C2MOS D Flip Flop using Logical Effort Theory
Swarnima Trivedi*
Department of Engineering and Technology, Mody University of Science and Technology, Lakshmangarh, India

ABSTRACT
Future Electronics has a full selection of Binary counters or Frequency dividers such as Radio Frequency divider,
digital frequency divider, analog frequency divider which can further be used for improving the performance of
electronic counter measures equipment’s, communications systems and laboratory instruments. An arrangement of
D Flip Flops is a classical method of designing a Frequency Divider. There is vast variation encountered in digital
circuits because of scaling and process imperfections. So this paper deals with D flip-flop circuit in terms of
propagation delay. The task is to minimize the propagation delay of D flip-flop blocks using Logical Effort Theory
which is further used in designing binary counter.
Keywords: Frequency Divider; Counter; C2MOS; Logical Effort Theory

INTRODUCTION of D flip-flops are to introduce delay in timing circuit, as a

buffer, sampling data at specific intervals etc. The symbol of D
Sequential logic is a type of logic circuit where output not only Flip Flop is shown in Figure 2.1. The clock signal has to be high
depends on the present value of its input signals but also on the for the inputs to get activated and whenever the clock signal is
sequence of past inputs unlike combinational logic, where LOW, the output remains unaffected. C2MOS design uses
output is a function of only the present inputs. clocked inverter shown in Figure2.2. The circuit combines the
The basic memory element in sequential logic is the bistable static logic with synchronization which is achieved through clock
latch or flip-flop. Sequential circuits can be synchronous or signals. It is just like an ordinary inverter except that it is
asynchronous depending upon the construction of clock signal controlled by a set-signal i.e. c’ and c [1]. These are normally
i.e. in synchronous circuits the internal state of the circuit connected to the clock signal so that the inverter either inverts
change their state simultaneously with the given`input clock while the clock is low or while it is high.
signal whereas in asynchronous circuits clock signal ripple
through stages to achieve the next state.
This paper is organized as follows: Section 2 describes D flip
flop symbol , clocked inverter circuit; Section 3 describes the
logical effort technique for delay minimization; Section 4
describes the design specification for D Flip Flop designed by
C2MOS technique using Logical Effort Theory; Section 5
presents the simulation results and the conclusion is given in
Section 6.

THE CLOCKED INVERTER

D Flip-flops are used as a part of memory storage elements and Many efforts have been done to enhance the performance of D
data processors also they are simpler in terms of wiring flip flop. The method of logical effort is the easiest way to
connection as compared to JK flip-flop. The major applications estimate delay in a CMOS circuit.

*Correspondence to: Swarnima Trivedi, Department of Engineering and Technology, Mody University of Science and Technology, Lakshmangarh,
India; Tel No: 9166305026; E-Mail: [email protected]
Received date: May 26, 2021; Accepted date: September 14, 2021; Published date: September 24, 2021
Citation: Trivedi S (2021) Minimizing the delay of C2MOS D flip flop using Logical effort theory. J Remote Sens GIS 10: p747
Copyright: © 2021 Trivedi S. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which
permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

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Trivedi S

More importantly, it leads to a natural extension for estimating

the minimum delay, D, of a path of complex logic as
D = NF1/N+P
Gate sizes required for calculating least delay
Cin = giCouti/𝑓̂
While calculating logical effort length of transistor is kept
constant and we capture transistor size by its width,w.As the
capacitance of the transistor’s gate is proportional to w and its
ability to produce output current, or conductance, is also
proportional to w [2]. We compute the logical effort as a ratio of
capacitances, the units we use to measure capacitance may be
In particular Transistor Sizing is effective method in reducing arbitrary (as the quantity is ratioless). This observation simplifies
delay in particular circuit and through method of logical effort the calculations largely. In CMOS processes, pullup transistors
the proper number of logic stages on a path and the best must be wider than pulldown transistors to have the same
transistor sizes for the logic gates can be estimated. conductance or same resistance µ is defined which is µ = µn/µp
The scheme C2MOS D flip flop is presented in this paper to is the ratio of PMOS to NMOS width in an inverter [3]. For
achieve better transition delay as compared with conventional simplicity, we will often assume that γ = µ = 2 which means an
design. inverter will have a pulldown transistor of width w and a pullup
transistor of width 2w, represents in Figure 3.1a, so the total
input capacitance can be said to be 3w (i.e. 2+1=3).
DELAY IN A LOGIC GATE
The logical effort of a logic gate is defined as the number of
times worse it is at delivering output current than would be an
inverter with identical input capacitance. In the method, the
delay of a gate is estimated by modeling it as a linear function of
the load being driven as:
D = g× cout/cin + p = g×h+ p
= f+p
Logical Effort (g) is the complexity of the gate, relative to a
standard inverter circuit .i.e.
Figure.3.1 a) Inverter b) 2-input NAND Gate c) 2-input NOR
g =Cb/Cinv Gate
=(Σb Ci)/Cinv Similarly we find the logical effort of the 2-input NAND, 2-
Where, Cb is the combined input capacitance of every signal. input NOR gate in Figure 3.1b & Figure 3.1c respectively and of
Electrical Effort, or Gain (h=cout/cin) describes how the clocked inverter in Figure 2.2 by extracting capacitances from
electrical environment of the logic gate affects circuit the circuit. The input capacitance of one input signal is equals
performance and how the size of the transistors in the gate to the sum of the width of the pulldown transistor and the
determines its load-driving capability in any circuit and Parasitic pullup transistor [4], or 2+2 = 4 in NAND gate logic and
Delay (p) which is a fixed quantity expresses the intrinsic delay similarly for 2- input NOR gate 4+1 = 5 shown in Figure 3.1c.
of the gate due to its own internal capacitance. The input capacitance of logic gates are compared with the
input capacitance of the inverter with identical output drive is
Acc. to Sutherland the minimum delay of any circuit is obtained Cinv = 1+2 = 3. According to Equation, the logical effort per
by distributing the path effort F equally to each gate on the input of the 2-input NAND gate is therefore g = 4/3 and g = 5/3
path. Parasitic delay (pinv) of inverter is normalized to unity for for NOR gate.
our purpose and
Logical effort for clocked inverter is as below: For input in, gin
N-input NAND = n*pinv = (4+2/3) = 2 Similarly for clock signal c,
N-input NOR = n*pinv gc = (4+2/3) = 2
N-way mux = 2n*pinv gtotal = (2+2) =4
XOR = 4* pinv
Delay is the smallest when each stage bears some effort
DESIGN SPECIFICATION FOR C2MOS
COUNTER
𝑓̂= F1/N
The baseline counter circuit is shown in Figure 4.2 designed
using C2MOS D flip flop because of its fast and low power

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Trivedi S

applications [5][6]. It is an inverter- based master-slave D flip-flop (W/L)13=(W/L)14=2(W/L)11 6.12

uses clocked inverters described in section 2 to control the
loading value and breaking the feedback loop. The schematic for (W/L)15=(W/L)16 2.63
C2MOS D flip flop [7] is shown in Figure 4.1.
(W/L)17=(W/L)18=2(W/L)15 5.27

(W/L)20=2(W/L)19 2.26

Table 2: Delay comparison in DFF with or without LET

Delay DFF without LET(in DFF with LET(in

nsec) nsec)

Delay Time 49.2190 48.5893

Average Delay 49.1136 48.3917

Figure.4.1 C2MOS D flip flop structure Table 3: Delay comparison in Counter circuit with or without
LET

Delay Counter without Counter with LET

LET(in nsec)
(in nsec)

Delay Time 29.2188 28.5911

Average Delay 27.1149 26.3923

CONCLUSION
Use of Logical Effort methods for performance comparison of
counter circuit is presented. Obtained results are found
These are the following specifications keeping the parameters of consistent with simulation and are encouraging that counter
first stage constant we calculated rest of parameters using logical designed with LET technique is faster as compared to
effort theory for designing the flip flop of channel length conventional design.
L=0.18µm having 65fF load.
REFERENCES
SIMULATION RESULTS 1. S.Thomas Niba, “Analysis of shift register using integrated power and
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2. Sutherland, B. Sproull, D. Harris, “Logical Effort: Designing Fast
16.30 with 65fF load. The model is compared against the CMOS Circuits,” Morgan Kaufmann Publisher, 1999.
original one. 3. Kunwar Singh, Aman Jain “Optimum transistor sizing of CMOS logic
circuits using logical effort theory and evolutionary algorithms,”
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(W/L)10=2(W/L)9 0.89
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