(CO F- Bu teem Da Beg mel there | AYE OF of @ Ruse evs ay PI 917 9B Flagh Ge ach tent Cm AY oo < @ OT pat IK OE on oun A AVR microcontroller cue WO Ram —s a we @ LeFor Sopret : git Soest me BD AVR is a B-bit RISC architecture (Reduced Instruction Set Cofmpiiting) microcontroller: on Ries P. programmable flash memory, SRAM, IO data space & EEPROM. AVR is the first MCU in, arrotvhicineeee flash storage.) / @ mye “ered “2.98 | toh “a (The AVR is @ modified Harvard architecture machine .This means the Flash Program Memory space is on a separate ‘address bus than the Static Random Access Memory (SRAM), where program and data are stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions. ) Which microcontrolieris used in AVR? (Atmegas AVR Microcontroller It consists of 26 Pins, 1KByte Internal SRAM, Skb of flash memory, two exterior \nterrupts support. It has two wire interface, external pin to connect two voltages into two input of the comparator. Uses: Mainly used to build electrical and electronic Projects.) 1, {Whats the architecture of AVR ane ARM ‘AVR microcontrollers are known for their low cost and high performance. ARM microcontrollers are known for their high-speed operation, AVR microcontrollers have a smaller number of built-in peripherals. ARM icrocontroliers have a greater number of built-in peripherals. \VR is a family of microcontrollers developed since 1996 by Atmel, aequired-by-Microchip |. “Technology in-2026. These are modified Harvard architecture 8-bitRISC single-chip microcontrollers. AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time. AVR microcontrollers find many applications as embedded systems. They are especially common in hobbyist and educational embedded applications, popularized by their inclusion in many of the Arduino line of open hardware development boards. AVRs are generally classified into following:Tiny AVR, Mega AVR, AVR DX etc, where X is DA, DB, DD. ) 32-bit AVRs 1n 2006, Atmel released microcontrollers based on the 32-bit AVR32 architecture. This was a completely different architecture unrelated to the &-bit AVR, intended to compete withthe ARM-based processors}(t hada 32-bit data pati) SIMD and DSP instructions, along with other audio- and video-processing features, The instruction set was Similar to other RISC cores, bat it was not compatible with the original AVR (nor any ofthe various ARM cores) and was never mainlined, Instead Atinel had already been a licensee of the ARM architecture, with both ARM7 and ARM9 microcontrollers having been released prior to and concurrently with the AVR32; later ‘Atmel focused most development effort on 32-bit chips with ARM Cortex-M and Corten-A cores. Prelilecdne Contains Device architecture © 32,581! ey vk ‘Atmel ATxmegal28A1 in 100-pin! OFP package @ Prog ¢ hash OF aay SP Res: nates ‘QD. the aves have 22 siiaié-bvte ealsters and are clasified as 8-bit RISC devices. Arean TUK STEP It aterm §R — ERT ates PEM HC vod ccaspacs cmarth 4 by Fi) (Program memory. ————, a Tio Ay * ‘program instructions are stored in ndn-volaile flash memory. Although the MCUs Phtets - Pisruction takes one oF two 16-bit words. The size of the program mpmory is usually indicated in the 532 sm @ Frio — gels ‘eoeatod V4naming ofthe device itself (e.g., the ATmega64x line has 64 KB of flash, while the ATmega32x line has 32 KB), There is no provision for off- gram memory all code executed by the AVR core must veside in the on-chip flash. However, ths limitation does not apply to the AT94 FPSLIC AVRIFPGA chips internal data memory ry, The data address space consists of the reaister fl, 110 registers, and SRAM. Some small models also map the program ROM into the data address space, but larger models do not. Internal registers GPIO ports CQemerel Puvpose) Each GPIO port on a tiny or mega AVR drives up to eight pins and is controlled by three &-bit registers: DDRx, PORTx and PINx, where x is the port identifier. EEPROM ‘Almost all AVR microcontrollers have internal EEPROM for semi-permanent data storage. Like flash memory, EEPROM can maintain its contents when electrical power is removed. AVRs offer a wide range of features: 2 Multifunction, ional general-purpose V/O ports with-configurable, built-in pull-up resistors “¥¢ Niultiple internal oscilators, including RC oscillator without external parts \2- Internal, self-progtammable instruction flash memory up to 256 KB (384 KB on XMega) On-chip debugging (OCD) support through JTAG or debugWIRE on most devices P Internal data EEPROM up to 4 KB Internal SRAM up to 16 KB (32 KB on XMega)fé «> > External 64 KB little\endian data space on certain models, o /S-bit and 16-bit timers ~~ #\Analog comparator ~~ + 10 or 12-bit A/D converters/~with multiplex of up to 16 channels = 12-bit DIA converters 7 * A variety of serial interfaces, including ‘© PC compatible Two-Wire Interface (TWI) ‘© Synchronous/asynchronous serial peripherals (UART/USART) (used with RS-232, RS-485, and sto 29018 more) ©. Serial Peripheral Interface Bus (SPI) ~ aot «Watchdog timer (WDT) | >¢ul panto? at + Multiple power-saving sleep modes —~ ag « CAN controller support + | a oe a an «USB controller support” vi se «Ethernet controller support *~ te ee a elt ae oot «> LCD controller support ~ i is a 25 Jlow-voltage devices operating down to 1.8 V}to 0.7 V for parf\with built-in DC-DC upconvert SpicoPower devices ne erter) «DMA controllers and "event system" pepe coptineaton a eTTh 7 ; - _ There are 7 basic addressing modes for the AVR tre Re Avo ®&, R3 wv 1. Register Direct - pec Rs SuGB RE ,RF * Single Register = —___ — —— ; AND WO, 47 Two Registers — OT : 3 ‘wo Registers Le P FF ey Rit RH add r1,r2 ;add the two numbers and store in rl ~~ com r4 ; complimant the contents of r4. inc r15 ; increment\he contents of r15 by 1 clr r2 ; clear the contents of r2-allOsinr2 — J add r2,r5 ; add the contents of the 2 registers _- a eo a Format: label: mnemonic destination_reg, source_reg ,comment 4” 7 of a, Ks coo? and r6,r1 ; logically AND the contents of the 2 registers yor 3? & ox sf mov r14,r15 ; move the contents of r15 to r14 ne 3h ; feat ote ot a ope 2. 1/0 Direct — a Format: label: IN rd,Port_Address comment ‘~ label: OUT Port_Address,rs comment »— rd and rs can be any of the 32 registers 4 EBASIZR. rd and rs can be any io rd is a destination register when data is read from a port — Input ports are referred to as PIN PinA, PinB, PinC, etc) Nw the source register when data is being sent out ae You at I bx 400% , we wy 02 an Ry, o%é cor ef 27 nw or? gm Ry,» bur add. our Ro avd , Ri oe Ces,we eq ot Deas Ce 3. Immediate - por Rel The destination operand is one of the 32 registers — ee ‘The source operand is immediate data Loe Ra, of Aer oe * The actual data that will be used in the instruction vegelt ao + Immediate mode is denoted by an “i” in the mnemonic Yor Example Idi r2,0x62 ; load hex 62 into register r2. OK Fe label: mnemonic destinatior Idi 17,10 ; put 10 inr 17 4, Data Direct Data Direct: — Instructions are two word (16-bit) One of the operands is the address of the data (address ‘of where the data is stored) ~ The other operan 1g,data comment — wera : Od 4 Horeen Op Cade (Operation code) Register Source or destination Drver & re 16 bit address ($0000 - SFFFF) (ie : 0 0s a Assume: vs L ‘usd + ()=F0 a ee i 5 vo) s< BFFECS v8 it 1,90% 3FFF IA wor 69 Looe 2? oe 4000 32 vt oo He 4001 BE ox ye be Whats the data in and 5 after the follwing struction? by Ef bes lds r1,0x4000 (ed yen ee") a sts Ox3ffer15 ch ne : 303 v to Data Direct « In Data Direct, one of the operands is an explicitly Data Direct, one of the operands is an explicit ‘ar Specified address (to store or\etrieve data) + In Data Indirect, the address is specified as the contents of the X, Y, or Z registdy—X is the combination of r26 & 127 —-Y 128 & 129 —Zis the combination Wf r30 & Format: label: mnemonic destinytion_reg, register) the combination of ~%, Y, orZ are referred to as the “p ert X comment (Moves data frommemorytoa ** label: mnemonic x, source_reg comment (Moves data from a re In the formats shown above, x could be register X, Y, or ZX = : 126: Low Byte of address r29: : Low Byte of address r31: High Byte of address r30: Low Byte of address 6 .Indirect Program Addressing — c 3 40 sister to memory) a register = 660"7. Relative Program Addressing LSeannernseeenes see The current PC is used as a pointer 2k offset from the current PC Can have a + or — Used for Relative Jumps or Subroutine Calls Example rjmp or reall a ay? fet eck . eux : wer? es oy dt) peice Ae (te ¥ vie yo ye oe hn ye 3)