COMPUTER ORGANIZATION

MODULE 2: INPUT/OUTPUT ORGANIZATION

ACCESSING I/O-DEVICES
• A single bus-structure can be used for connecting I/O-devices to a computer (Figure 7.1).
• Each I/O device is assigned a unique set of address.
• Bus consists of 3 sets of lines to carry address, data & control signals.
• When processor places an address on address-lines, the intended-device responds to the command.
• The processor requests either a read or write-operation.
• The requested-data are transferred over the data-lines.

• There are 2 ways to deal with I/O-devices: 1) Memory-mapped I/O & 2) I/O-mapped I/O.
1) Memory-Mapped I/O
 Memory and I/O-devices share a common address-space.
 Any data-transfer instruction (like Move, Load) can be used to exchange information.
 For example,
Move DATAIN, R0; This instruction sends the contents of location DATAIN to register R0.
Here, DATAIN  address of the input-buffer of the keyboard.
2) I/O-Mapped I/O
 Memory and I/0 address-spaces are different.
 A special instructions named IN and OUT are used for data-transfer.
 Advantage of separate I/O space: I/O-devices deal with fewer address-lines.
I/O Interface for an Input Device
1) Address Decoder: enables the device to recognize its address when this address
appears on the address-lines (Figure 7.2).
2) Status Register: contains information relevant to operation of I/O-device.
3) Data Register: holds data being transferred to or from processor. There are 2 types:
i) DATAIN  Input-buffer associated with keyboard.
ii) DATAOUT  Output data buffer of a display/printer.

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MECHANISMS USED FOR INTERFACING I/O-DEVICES

1) Program Controlled I/O
• Processor repeatedly checks status-flag to achieve required synchronization b/w processor & I/O
device. (We say that the processor polls the device).
• Main drawback:
The processor wastes time in checking status of device before actual data-transfer takes place.
2) Interrupt I/O
• I/O-device initiates the action instead of the processor.
• I/O-device sends an INTR signal over bus whenever it is ready for a data-transfer operation.
• Like this, required synchronization is done between processor & I/O device.
3) Direct Memory Access (DMA)
• Device-interface transfer data directly to/from the memory w/o continuous involvement by the
processor.
• DMA is a technique used for high speed I/O-device.

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INTERRUPTS
• There are many situations where other tasks can be performed while waiting for an I/O device to
become ready.
• A hardware signal called an Interrupt will alert the processor when an I/O device becomes ready.
• Interrupt-signal is sent on the interrupt-request line.
• The processor can be performing its own task without the need to continuously check the I/O-device.
• The routine executed in response to an interrupt-request is called ISR.
• The processor must inform the device that its request has been recognized by sending INTA signal.
(INTR  Interrupt Request, INTA  Interrupt Acknowledge, ISR  Interrupt Service Routine)
• For example, consider COMPUTE and PRINT routines (Figure 3.6).

• The processor first completes the execution of instruction i.

• Then, processor loads the PC with the address of the first instruction of the ISR.
• After the execution of ISR, the processor has to come back to instruction i+1.
• Therefore, when an interrupt occurs, the current content of PC is put in temporary storage location.
• A return at the end of ISR reloads the PC from that temporary storage location.
• This causes the execution to resume at instruction i+1.
• When processor is handling interrupts, it must inform device that its request has been recognized.
• This may be accomplished by INTA signal.
• The task of saving and restoring the information can be done automatically by the processor.
• The processor saves only the contents of PC & Status register.
• Saving registers also increases the Interrupt Latency.
• Interrupt Latency is a delay between
→ time an interrupt-request is received and
→ start of the execution of the ISR.
• Generally, the long interrupt latency in unacceptable.

Difference between Subroutine & ISR

Subroutine ISR
A subroutine performs a function required by the ISR may not have anything in common with
program from which it is called. program being executed at time INTR is received
Subroutine is just a linkage of 2 or more function Interrupt is a mechanism for coordinating I/O
related to each other. transfers.

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INTERRUPT HARDWARE
• Most computers have several I/O devices that can request an interrupt.
• A single interrupt-request (IR) line may be used to serve n devices (Figure 4.6).
• All devices are connected to IR line via switches to ground.
• To request an interrupt, a device closes its associated switch.
• Thus, if all IR signals are inactive, the voltage on the IR line will be equal to Vdd.
• When a device requests an interrupt, the voltage on the line drops to 0.
• This causes the INTR received by the processor to go to 1.
• The value of INTR is the logical OR of the requests from individual devices.
INTR=INTR1+ INTR2+ . . . . . +INTRn
• A special gates known as open-collector or open-drain are used to drive the INTR line.
• The Output of the open collector control is equal to a switch to the ground that is
→ open when gates input is in ”0‟ state and
→ closed when the gates input is in “1‟ state.
• Resistor R is called a Pull-up Resistor because
it pulls the line voltage up to the high-voltage state when the switches are open.

ENABLING & DISABLING INTERRUPTS

• All computers fundamentally should be able to enable and disable interruptions as desired.
• The problem of infinite loop occurs due to successive interruptions of active INTR signals.
• There are 3 mechanisms to solve problem of infinite loop:
1) Processor should ignore the interrupts until execution of first instruction of the ISR.
2) Processor should automatically disable interrupts before starting the execution of the ISR.
3) Processor has a special INTR line for which the interrupt-handling circuit.
Interrupt-circuit responds only to leading edge of signal. Such line is called edge-triggered.
• Sequence of events involved in handling an interrupt-request:
1) The device raises an interrupt-request.
2) The processor interrupts the program currently being executed.
3) Interrupts are disabled by changing the control bits in the processor status register (PS).
4) The device is informed that its request has been recognized.
In response, the device deactivates the interrupt-request signal.
5) The action requested by the interrupt is performed by the interrupt-service routine.
6) Interrupts are enabled and execution of the interrupted program is resumed.

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HANDLING MULTIPLE DEVICES
• While handling multiple devices, the issues concerned are:
1) How can the processor recognize the device requesting an interrupt?
2) How can the processor obtain the starting address of the appropriate ISR?
3) Should a device be allowed to interrupt the processor while another interrupt is being
serviced?
4) How should 2 or more simultaneous interrupt-requests be handled?

POLLING
• Information needed to determine whether device is requesting interrupt is available in status-register
• Following condition-codes are used:
 DIRQ  Interrupt-request for display.
 KIRQ  Interrupt-request for keyboard.
 KEN  keyboard enable.
 DEN  Display Enable.
 SIN, SOUT  status flags.
• For an input device, SIN status flag in used.
SIN = 1  when a character is entered at the keyboard.
SIN = 0  when the character is read by processor.
IRQ=1  when a device raises an interrupt-requests (Figure 4.3).
• Simplest way to identify interrupting-device is to have ISR poll all devices connected to bus.
• The first device encountered with its IRQ bit set is serviced.
• After servicing first device, next requests may be serviced.
• Advantage: Simple & easy to implement.
Disadvantage: More time spent polling IRQ bits of all devices.

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DIRECT MEMORY ACCESS (DMA)
• The transfer of a block of data directly b/w an external device & main-memory w/o continuous
involvement by processor is called DMA.
• DMA controller
→ is a control circuit that performs DMA transfers (Figure 8.13).
→ is a part of the I/O device interface.
→ performs the functions that would normally be carried out by processor.
• While a DMA transfer is taking place, the processor can be used to execute another program.

• DMA interface has three registers (Figure 8.12):

1) First register is used for storing starting-address.
2) Second register is used for storing word-count.
3) Third register contains status- & control-flags.

• The R/W bit determines direction of transfer.

If R/W=1, controller performs a read-operation (i.e. it transfers data from memory to I/O),
Otherwise, controller performs a write-operation (i.e. it transfers data from I/O to memory).
• If Done=1, the controller
→ has completed transferring a block of data and
→ is ready to receive another command. (IE  Interrupt Enable).
• If IE=1, controller raises an interrupt after it has completed transferring a block of data.
• If IRQ=1, controller requests an interrupt.
• Requests by DMA devices for using the bus are always given higher priority than processor requests.
• There are 2 ways in which the DMA operation can be carried out:
1) Processor originates most memory-access cycles.
 DMA controller is said to "steal" memory cycles from processor.
 Hence, this technique is usually called Cycle Stealing.
2) DMA controller is given exclusive access to main-memory to transfer a block of data without
any interruption. This is known as Block Mode (or burst mode).

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BUS ARBITRATION
• The device that is allowed to initiate data-transfers on bus at any given time is called bus-master.
• There can be only one bus-master at any given time.
• Bus Arbitration is the process by which
→ next device to become the bus-master is selected &
→ bus-mastership is transferred to that device.
• The two approaches are:
1) Centralized Arbitration: A single bus-arbiter performs the required arbitration.
2) Distributed Arbitration: All devices participate in selection of next bus-master.
• A conflict may arise if both the processor and a DMA controller or two DMA controllers try to use the
bus at the same time to access the main-memory.
• To resolve this, an arbitration procedure is implemented on the bus to coordinate the activities of all
devices requesting memory transfers.
• The bus arbiter may be the processor or a separate unit connected to the bus.

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CENTRALIZED ARBITRATION
• A single bus-arbiter performs the required arbitration (Figure: 4.20).
• Normally, processor is the bus-master.
• Processor may grant bus-mastership to one of the DMA controllers.
• A DMA controller indicates that it needs to become bus-master by activating BR line.
• The signal on the BR line is the logical OR of bus-requests from all devices connected to it.
• Then, processor activates BG1 signal indicating to DMA controllers to use bus when it becomes free.
• BG1 signal is connected to all DMA controllers using a daisy-chain arrangement.
• If DMA controller-1 is requesting the bus,
Then, DMA controller-1 blocks propagation of grant-signal to other devices.
Otherwise, DMA controller-1 passes the grant downstream by asserting BG2.
• Current bus-master indicates to all devices that it is using bus by activating BBSY line.
• The bus-arbiter is used to coordinate the activities of all devices requesting memory transfers.
• Arbiter ensures that only 1 request is granted at any given time according to a priority scheme.
(BR  Bus-Request, BG  Bus-Grant, BBSY  Bus Busy).

• The timing diagram shows the sequence of events for the devices connected to the processor.
• DMA controller-2
→ requests and acquires bus-mastership and
→ later releases the bus. (Figure: 4.21).
• After DMA controller-2 releases the bus, the processor resources bus-mastership.

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DISTRIBUTED ARBITRATION
• All device participate in the selection of next bus-master (Figure 4.22).
• Each device on bus is assigned a 4-bit identification number (ID).
• When 1 or more devices request bus, they
→ assert Start-Arbitration signal &

→ place their 4-bit ID numbers on four open-collector lines ARB 0 through ARB 3 .
• A winner is selected as a result of interaction among signals transmitted over these lines.
• Net-outcome is that the code on 4 lines represents request that has the highest ID number.
• Advantage:
This approach offers higher reliability since operation of bus is not dependent on any single device.

For example:
 Assume 2 devices A & B have their ID 5 (0101), 6 (0110) and their code is 0111.
 Each device compares the pattern on the arbitration line to its own ID starting from MSB.
 If the device detects a difference at any bit position, it disables the drivers at that bit position.
 Driver is disabled by placing ”0” at the input of the driver.
 In e.g. “A” detects a difference in line ARB1, hence it disables the drivers on lines ARB1 & ARB0.
 This causes pattern on arbitration-line to change to 0110. This means that “B” has won
contention.

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SPEED, SIZE COST

• The main-memory can be built with DRAM (Figure 8.14)

• Thus, SRAM‟s are used in smaller units where speed is of essence.
• The Cache-memory is of 2 types:
1) Primary/Processor Cache (Level1 or L1 cache)
 It is always located on the processor-chip.
2) Secondary Cache (Level2 or L2 cache)
 It is placed between the primary-cache and the rest of the memory.
• The memory is implemented using the dynamic components (SIMM, RIMM, DIMM).
• The access time for main-memory is about 10 times longer than the access time for L1 cache.

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CACHE MEMORIES
• The effectiveness of cache mechanism is based on the property of „Locality of Reference’.
Locality of Reference
• Many instructions in the localized areas of program are executed repeatedly during some time period
• Remainder of the program is accessed relatively infrequently (Figure 8.15).
• There are 2 types:
1) Temporal
 The recently executed instructions are likely to be executed again very soon.
2) Spatial
 Instructions in close proximity to recently executed instruction are also likely to be executed soon.
• If active segment of program is placed in cache-memory, then total execution time can be reduced.
• Block refers to the set of contiguous address locations of some size.
• The cache-line is used to refer to the cache-block.

• The Cache-memory stores a reasonable number of blocks at a given time.

• This number of blocks is small compared to the total number of blocks available in main-memory.
• Correspondence b/w main-memory-block & cache-memory-block is specified by mapping-function.
• Cache control hardware decides which block should be removed to create space for the new block.
• The collection of rule for making this decision is called the Replacement Algorithm.
• The cache control-circuit determines whether the requested-word currently exists in the cache.
• The write-operation is done in 2 ways: 1) Write-through protocol & 2) Write-back protocol.
Write-Through Protocol
 Here the cache-location and the main-memory-locations are updated simultaneously.
Write-Back Protocol
 This technique is to
→ update only the cache-location &
→ mark the cache-location with associated flag bit called Dirty/Modified Bit.
 The word in memory will be updated later, when the marked-block is removed from cache.
During Read-operation
• If the requested-word currently not exists in the cache, then read-miss will occur.
• To overcome the read miss, Load–through/Early restart protocol is used.
Load–Through Protocol
 The block of words that contains the requested-word is copied from the memory into cache.
 After entire block is loaded into cache, the requested-word is forwarded to processor.
During Write-operation
• If the requested-word not exists in the cache, then write-miss will occur.
1) If Write Through Protocol is used, the information is written directly into main-memory.
2) If Write Back Protocol is used,
→ then block containing the addressed word is first brought into the cache &
→ then the desired word in the cache is over-written with the new information.

MAPPING-FUNCTION
• Here we discuss about 3 different mapping-function:
1) Direct Mapping
2) Associative Mapping
3) Set-Associative Mapping

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DIRECT MAPPING
• The block-j of the main-memory maps onto block-j modulo-128 of the cache (Figure 8.16).
• When the memory-blocks 0, 128, & 256 are loaded into cache, the block is stored in cache-block 0.
Similarly, memory-blocks 1, 129, 257 are stored in cache-block 1.
• The contention may arise when
1) When the cache is full.
2) When more than one memory-block is mapped onto a given cache-block position.
• The contention is resolved by
allowing the new blocks to overwrite the currently resident-block.
• Memory-address determines placement of block in the cache.

• The memory-address is divided into 3 fields:

1) Low Order 4 bit field
 Selects one of 16 words in a block.
2) 7 bit cache-block field
 7-bits determine the cache-position in which new block must be stored.
3) 5 bit Tag field
 5-bits memory-address of block is stored in 5 tag-bits associated with cache-location.
• As execution proceeds,
5-bit tag field of memory-address is compared with tag-bits associated with cache-location.
If they match, then the desired word is in that block of the cache.
Otherwise, the block containing required word must be first read from the memory.
And then the word must be loaded into the cache.

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ASSOCIATIVE MAPPING
• The memory-block can be placed into any cache-block position. (Figure 8.17).
• 12 tag-bits will identify a memory-block when it is resolved in the cache.
• Tag-bits of an address received from processor are compared to the tag-bits of each block of cache.
• This comparison is done to see if the desired block is present.

• It gives complete freedom in choosing the cache-location.

• A new block that has to be brought into the cache has to replace an existing block if the cache is full.
• The memory has to determine whether a given block is in the cache.
• Advantage: It is more flexible than direct mapping technique.
• Disadvantage: Its cost is high.

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SET-ASSOCIATIVE MAPPING
• It is the combination of direct and associative mapping. (Figure 8.18).
• The blocks of the cache are grouped into sets.
• The mapping allows a block of the main-memory to reside in any block of the specified set.
• The cache has 2 blocks per set, so the memory-blocks 0, 64, 128…….. 4032 maps into cache set „0‟.
• The cache can occupy either of the two block position within the set.
6 bit set field
 Determines which set of cache contains the desired block.
6 bit tag field
 The tag field of the address is compared to the tags of the two blocks of the set.
 This comparison is done to check if the desired block is present.

• The cache which contains 1 block per set is called direct mapping.
• A cache that has „k‟ blocks per set is called as “k-way set associative cache‟.
• Each block contains a control-bit called a valid-bit.
• The Valid-bit indicates that whether the block contains valid-data.
• The dirty bit indicates that whether the block has been modified during its cache residency.
Valid-bit=0  When power is initially applied to system.
Valid-bit=1  When the block is loaded from main-memory at first time.
• If the main-memory-block is updated by a source & if the block in the source is already exists in the
cache, then the valid-bit will be cleared to “0‟.
• If Processor & DMA uses the same copies of data then it is called as Cache Coherence Problem.
• Advantages:
1) Contention problem of direct mapping is solved by having few choices for block placement.
2) The hardware cost is decreased by reducing the size of associative search.

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