ATPG and Fault Simulation

Alberto Bosio
[email protected]

1
What is a test?
Fault activation
Combinational Fault effect
circuit
X
1
0
1/0 1/0
Primary 0 Primary outputs
inputs 1 (PO)
(PI) 0
1
X

2
Stuck-at-0 fault Path sensitization

3
What is a test?
Fault activation
Combinational Fault effect
circuit
X
1
0
Primary 1/0 1/0
0 Primary outputs
inputs 1 (PO)
(PI) 0
1
X Test Response
Test Vector Stuck-at-0 fault
4
Path
sensitizatio
n

5
Example
 Generate a test for e stuck-at-1

Sa1
a

b e
c
g

d f

6
Example
 1) Activate the fault

a 0
e
b
c
g

d f

7
Example
 1) Activate the fault

a 0/1
e
b
c
g

d f

8
Example
 1) Activate the fault

Fault Effect

a 0/1
e
b
c
g

d f

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Example
 1) Propagate the fault effect

a 0/1
e 0/1
b
c
g

d f

10
Example
 1) Propagate the fault effect

a 0/1
e 0/1
b
c
g

d f

11
Example
 1) Propagate the fault effect

a 0/1
e 0/1
b 0/1
c
g

d
0
f

12
Example
 1) Propagate the fault effect

a 0/1
e 0/1
b 0/1
c
g

d
0
f

13
Example
 Justification

a 0/1
e 0/1
b 0/1
c
g
0
d
f 0

14
Example
 Justification

a 0/1
1 e 0/1
b 0/1
c
g
1 0
d f 0

15
Example
 Justification

0
a 0/1
1 e 0/1
b 0/1
c
g
1 0
d f 0

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Some Considerations
 Test is easy
 But….

17
Some problems (the complexity)

2.2 Billion Transistors

18
Some problems (the circuit)
 Generate a test for c stuck-at-1

Sa1
a

b e
c
g

d f

19
Some problems (the circuit)
 c stuck-at-1 is an untestable fault

1
a 0/1
e 0/1
0 0/1
b
c
1
g
0 1
d
f 1

20
Goals
 You must use the appropriate tool
 Automatic Test Pattern Generator (ATPG)

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 ATPG Architecture

Circuit Reduced
description Fault Manager
Fault List

TPG
Fault Simulator
Algorith

Fault Test
Coverage Pattern
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 ATPG Architecture

Circuit Reduced
description Fault Manager Fault List
Fault Coverage (FC) = # Detected Faults/#Total Faults

TPG
Fault Simulator
Fault Algorith
Test
Coverage Pattern

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The test plan
 Step 1:
 Identify the set of target faults (complete
fault list).

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The test plan
 Step 1:
 Tools – Fault list generator
 (One of the components of the Fault Manager).

Fault List Generator

Circuit description
Complete Fault List

25
 The test plan (cont’d)
 Step 1:
 Identify the set of target faults (complete
fault list).
 Step 2:
 Identify the minimum set of distinct target
faults (fault collapsing)

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The test plan
 Step 2:
 Tools – Fault collapser (One of the
components of the Fault Manager).

27
Fault Manager

Fault List Generator

Circuit
description
Complete
Fault List

Reduced Fault Collapser

Fault List

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Fault Manager

Circuit description Fault Manager Reduced Fault List

Test Pattern Generator

Test Pattern Fault Coverage

27
 The test plan (cont’d)
 Step 2:
 Identify the minimum set of distinct target
faults (fault collapsing)
 Step 3:
 Generate, at no charge, an initial set of
patterns (manually, from design validation,
randomly, ...)

2
 The test plan (cont’d)
 Step 3:
 Generate, at no charge, an initial set of
patterns (manually, from design validation,
randomly, ...)
 Step 4:
 Update the list of detected faults (fault
simulation)

2
Step 4
 Tools
 Fault Simulators: identify the set of faults
covered by each test pattern.

3
 Fault Simulator
Circuit descriptionReduced Fault List

Fault Simulator
Update

Detected Faults
Fault Coverage Test Pattern

3
 The test plan (cont’d)
 Step 4:
 Update the list of detected faults (fault
simulation)
 Step 5:
 Generate a set of patterns to cover the
uncovered faults (TPG)

3
Step 5
 Tools
 ATPG: Automatic Test Pattern Generator

3
 TPG
Circuit description Reduced
Fault List

Fault Simulator TPG Fault Selector

Algorithm

Fault Coverage Test Pattern Target Fault

Detected Faults

34
 They cycle through three sub-phases:
 target fault selection
 Pattern generation
 Covered fault list updating.

3
 The test plan (cont’d)
 Step 5:
 Generate a set of patterns to cover the
uncovered faults (TPG)
 Step 6 (optional):
 Testability analysis
 Step 7 (optional):
 Compact test pattern set.

3
Step 6
Goal
 Estimate the effort needed to test the UUT:
 Pattern length
 Fault coverage
 CPU time
 ...
 Identify hard-to-test areas
 Tools
 Testability Analyzer
 Experience.
3
 The test plan (cont’d)
 Step 5:
 Generate a set of patterns to cover the
uncovered faults (TPG)
 Step 6 (optional):
 Testability analysis
 Step 7 (optional):
 Compact test pattern set.

3
Testability Analyzer
 High trade-off between result accuracy
and CPU time.

 A Circuit is testable when you ATPG can

manage it!!!!!

3
Fault Simulation*
 Problem and motivation
 Fault simulation algorithms
 Serial
 Parallel
 Deductive

*The lecture has been taken from Prof. Agrawal VLSI test course
(http://www.eng.auburn.edu/~agrawvd/COURSE/E7250_06/
course.html) 40
 Problem and Motivation
 Given
 A circuit
 A sequence of test vectors
 A fault model
 Determine
 Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
 Set of undetected faults

4
 Problem and Motivation
 Motivation
 Determine test quality and in turn product
quality
 Find undetected fault targets to improve
tests

4
Fault Simulation Scenario
 Circuit model: mixed-level
 Mostly logic with some switch-level for high-impedance (Z) and
bidirectional signals
 High-level models (memory, etc.) with pin faults
 Signal states: logic
 Two (0, 1) or three (0, 1, X) states for purely Boolean logic
circuits
 Four states (0, 1, X, Z) for sequential MOS circuits
 Timing:
 Zero-delay for combinational and synchronous circuits
 Mostly unit-delay for circuits with feedback

4
Fault Simulation Scenario (Continued)

 Faults:
 Mostly single stuck-at faults
 Sometimes stuck-open, transition, and path-delay
faults; analog circuit fault simulators are not yet in
common use
 Equivalence fault collapsing of single stuck-at faults
 Fault-dropping -- a fault once detected is dropped
from consideration as more vectors are
simulated; fault-dropping may be suppressed for
diagnosis
 Fault sampling -- a random sample of faults is
4
simulated when the circuit is large

4
Fault Simulation Algorithms
 Serial
 Parallel
 Deductive
 ....

4
Serial Algorithm
 Algorithm: Simulate fault-free circuit and save responses.
Repeat following steps for each fault in the fault list:
 Modify netlist by injecting one fault

 Simulate modified netlist, vector by vector, comparing

responses with saved responses

 If response differs, report fault detection and suspend

simulation of remaining vectors

 Advantages:
 Easy to implement; needs only a true-value simulator,

less memory
 Most faults, including analog faults, can be simulated

4
Serial Algorithm
 Disadvantage: Much repeated computation;
CPU time prohibitive for VLSI circuits
 Alternative: Simulate many faults together

4
Serial Algorithm

4
Serial algorithm
 + very simple
 - not efficient
 Intel I7 is about ~10M gates
 20M faults, 1 simulation = 1s
 20Ms ~= 231 days

5
 Parallel Fault Simulation
 Compiled-code method; best with two-states (0,1)
 Exploits inherent bit-parallelism of logic operations on
computer words
 Storage: one word per line for two-state simulation
 Multi-pass simulation: Each pass simulates w-1 new
faults, where w is the machine word length
 Speed up over serial method ~ w-1
 Not suitable for circuits with timing-critical and non-
Boolean logic

5
Parallel Fault Simulation

5
Parallel algorithm
 + still very simple
 + more efficient than serial
 Intel I7 is about ~10M gates
 20M faults, 1 simulation = 1s
 20Ms ~= 231 days
 Using a 64bits machine
 231/63 ~= 4 days

5
Deductive Fault Simulation
 One-pass simulation
 Each line k contains a list Lk of faults detectable on it
 Following true-value simulation of each vector, fault
lists of all gate output lines are updated using set-
theoretic rules, signal values, and gate input fault lists
 PO fault lists provide detection data
 Limitations:
 Set-theoretic rules difficult to derive for non-Boolean

gates
 Gate delays are difficult to use

5
Deductive Fault Simulation

5
Deductive algorithm
 - complex
 ++ more efficient than parallel
 Intel I7 is about ~10M gates
 20M faults, 1 simulation = 1s
 20Ms ~= 1s
 - it requires a lot of memory

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Exercice
which faults are detected by the input “01110”?

5
 In practice
 Use of Synopsys© Tetramax
Technology_library.v Test_vectors.stil

Fault List
Circuit.v
TMA
X

FaultCoverage 57
 Invoking TetraMax
 source /soft/Synopsys/source_config/.config_tetramax_standalone_vI-2013.12
 tmax

You can
enter
commands
5
Step1
 Read and Compile the circuit description

read_verilog C35.v –library

read_verilog exo1.v
run_build_model
Run_drc

5
Step 2
 Generate the fault list

set_faults -model stuck

add_faults -all

6
Step 3
 Specify the test vectors to be simulated
 We have to use the stil syntax
 Look in the example

Pattern "_pattern_" {
W "_default_WFT_";
"precondition all Signals": C
{ "_pi"=0000; "_po"=XX; }

"pattern 0": Call "capture" {

"_pi"=1010; "_po”=LL; }
} 61
Step 3
 Import the test vector file
set_patterns -external example_exo1.stil
 Now we can run a simulation
run_simulation
 You will got errors:
TEST-T> run_simulation
Begin good simulation of 1 external
patterns.
0 S2 (exp=0, got=1)
Simulation completed: #patterns=1,
#fail_pats=1(0), #failing_meas=1(0),
CPU time=0.00 62
 Step 3
 Tmax has to calculate the gold outputs
before running the fault simulation
run_simulation -override_differences
 Now you can run the fault simulation
run_fault_sim

63