5 4 3 2 1

ALTERA MAX10 Development & Education Board (DE10-Lite)

D PAGE CONTENT PAGE CONTENT D

1 Cover Page 19
2 Block Diagram 20
3 MAX 10 Bank 1 & 2 21
4 MAX 10 Bank 3 & 4 22
5 MAX 10 Bank 5 & 6 23
6 MAX 10 Bank 7 & 8 24
7 MAX 10 Clocks 25
C 8 MAX 10 Configuration 26 C

9 MAX10 Power
10 MAX10 Ground
11 MAX10 Decoupling
12 SDRAM
13 GPIO and Arduino Interface
14 LED, 7'Seg, User IO
15 VGA and Accelerometer
B
16 Power - 5V, 1.2V B

17 Power - 1.8V, 2.5V, 3.3V

18 USB Blaster

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B Cover Page A1

Date: Monday, September 19, 2016 Sheet 1 of 18

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B Block Diagram A1

Date: Monday, September 19, 2016 Sheet 2 of 18

5 4 3 2 1
 5 4 3 2 1

MAX10 Bank 1 & 2

Analog input interface
ADC1IN[8..1]
13

U5A
D VGA D
VGA_R[3..0]
MAX 10 LEFT BANKS
15
VGA_G[3..0] BANK-1A VCCIO = 2.5V BANK-2VCCIO = 3.3V
15
ADC1IN1 F5 P4 VGA_B2
VGA_B[3..0] ADC1IN2 F4 DIFFIO_RX_L1N/ADC1IN1 DIFFIO_RX_L29N P5
15 DIFFIO_RX_L1P/ADC1IN2 DIFFIO_RX_L29P
E4 N3 VGA_HS
E3 DIFFIO_RX_L2N/ADC2IN1 DIFFIO_RX_L37N N2 VGA_B3
VGA_HS ADC1IN3 J8 DIFFIO_RX_L2P/ADC2IN8 DIFFIO_RX_L37P R4
15 DIFFIO_RX_L3N/ADC1IN3 DIFFIO_RX_L39N
ADC1IN4 J9 R5
VGA_VS G4 DIFFIO_RX_L3P/ADC1IN4 DIFFIO_RX_L39P T1 VGA_B1
15 DIFFIO_RX_L4N/ADC2IN3 DIFFIO_RX_L40N
F3 T2 VGA_G1
ADC1IN6 H3 DIFFIO_RX_L4P/ADC2IN4 DIFFIO_RX_L40P N8
ADC1IN5 J4 DIFFIO_RX_L5P/ADC1IN6 DIFFIO_RX_L41N N9
H4 DIFFIO_RX_L5N/ADC1IN5 DIFFIO_RX_L41P P1 VGA_B0
G3 DIFFIO_RX_L6N/ADC2IN5 DIFFIO_RX_L42N N1 VGA_VS
ADC1IN7 K5 DIFFIO_RX_L6P/ADC2IN6 DIFFIO_RX_L42P T3
ADC1IN8 K6 DIFFIO_RX_L7N/ADC1IN7 DIFFIO_RX_L43N U2
J3 DIFFIO_RX_L7P/ADC1IN8 DIFFIO_RX_L43P U1
K4 DIFFIO_RX_L8P/ADC2IN2 DIFFIO_RX_L44N V1 VGA_R1
DIFFIO_RX_L8N/ADC2IN7 DIFFIO_RX_L44P U4
DIFFIO_RX_L45N U5
DIFFIO_RX_L45P U3
BANK-1B VCCIO = 2.5V DIFFIO_RX_L46N
K8 V3
C DIFFIO_RX_L15N DIFFIO_RX_L46P C
D3 P8
D2 DIFFIO_RX_L16N DIFFIO_RX_L47N R7
K2 DIFFIO_RX_L16P DIFFIO_RX_L47P W1 VGA_G0
L2 DIFFIO_RX_L19N DIFFIO_RX_L48N W2
L8 DIFFIO_RX_L19P DIFFIO_RX_L48P R1 VGA_G3
L9 DIFFIO_RX_L20N DIFFIO_RX_L60N R2 VGA_G2
E1 DIFFIO_RX_L20P DIFFIO_RX_L60P M2
F2 DIFFIO_RX_L21N VREFB2N0 M1
H1 DIFFIO_RX_L21P IO_BANK2
J1 DIFFIO_RX_L22N
G1 DIFFIO_RX_L22P
F1 DIFFIO_RX_L23N
M4 DIFFIO_RX_L23P
M3 DIFFIO_RX_L24N
K1 DIFFIO_RX_L24P
L1 DIFFIO_RX_L25N
C1 DIFFIO_RX_L25P
D1 VREFB1N0
IO_BANK1

10M50DAF484

B B

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B MAX 10 Bank 1 & 2 A1

Date: Monday, September 19, 2016 Sheet 3 of 18

5 4 3 2 1
 5 4 3 2 1

MAX10 Bank 3 & 4

GPIO 0
GPIO_[35..0]
7,13

Arduino Digital Interface U5B

Arduino_IO[15..0]
D 13 D
MAX 10 BOTTOM BANKS

BANK-3VCCIO = 3.3V BANK-4VCCIO = 3.3V

GPIO_25 Y7 W11 GPIO_19
GPIO_23 Y8 DIFFIO_RX_B10N DIFFIO_RX_B25N Y11 GPIO_17
Digital Accelerometer GPIO_34 AB2 DIFFIO_RX_B10P DIFFIO_RX_B25P AB10 GPIO_20
GSENSOR_SDI GPIO_32 AB3 DIFFIO_RX_B12N DIFFIO_RX_B27N AB11 GPIO_18
15 DIFFIO_RX_B12P DIFFIO_RX_B27P
GPIO_33 Y3 AB12 GPIO_16
GSENSOR_SCLK GPIO_31 Y4 DIFFIO_RX_B14N DIFFIO_RX_B29N AB13 GPIO_15
15 DIFFIO_RX_B14P DIFFIO_RX_B29P
GPIO_30 AA5 W12 GPIO_14
GSENSOR_INT1 Arduino_IO0 AB5 DIFFIO_RX_B17N DIFFIO_RX_B35N W13 GPIO_13
15 DIFFIO_RX_B17P DIFFIO_RX_B35P
GSENSOR_INT2 Arduino_IO1 AB6 AA14 GPIO_12
15 DIFFIO_RX_B19N DIFFIO_RX_B38N
Arduino_IO2 AB7 AB15 GSENSOR_SCLK
GSENSOR_CS_n GPIO_24 AA8 DIFFIO_RX_B19P DIFFIO_RX_B38P AA15 GPIO_11
15 DIFFIO_RX_B21N DIFFIO_RX_B40N
Arduino_IO3 AB8 Y16
GSENSOR_SDO GPIO_22 AA9 DIFFIO_RX_B21P DIFFIO_RX_B40P AB16 GSENSOR_CS_n
15 DIFFIO_RX_B23N DIFFIO_RX_B42N
Arduino_IO4 AB9 AA16
V4 DIFFIO_RX_B23P DIFFIO_RX_B42P AB19 Arduino_IO10
GPIO_9 V5 DIFFIO_RX_B2N DIFFIO_RX_B44N AB20 Arduino_IO13
VGA_R3 Y1 DIFFIO_RX_B2P DIFFIO_RX_B44P AA19 Arduino_IO11
VGA VGA_R2 Y2 DIFFIO_RX_B4N DIFFIO_RX_B46N Y18
VGA_R[3..0] VGA_R0 AA1 DIFFIO_RX_B4P DIFFIO_RX_B46P AB21 Arduino_IO14
15 DIFFIO_RX_B6N DIFFIO_RX_B50N
GPIO_35 AA2 AA20 Arduino_IO15
C DIFFIO_RX_B6P DIFFIO_RX_B50P C
GPIO_29 Y5 AB17 Arduino_IO8
GPIO_27 Y6 DIFFIO_RX_B8N DIFFIO_RX_B58N AB18
GPIO_3 W9 DIFFIO_RX_B8P DIFFIO_RX_B58P V11 GSENSOR_SDI
GPIO_1 W10 DIFFIO_TX_RX_B11N DIFFIO_TX_RX_B24N V12 GSENSOR_SDO
GPIO_7 W7 DIFFIO_TX_RX_B11P DIFFIO_TX_RX_B24P R12
GPIO_5 W8 DIFFIO_TX_RX_B13N DIFFIO_TX_RX_B26N P12
R10 DIFFIO_TX_RX_B13P DIFFIO_TX_RX_B26P AA11 Arduino_IO6
P10 DIFFIO_TX_RX_B15N DIFFIO_TX_RX_B28N AA12 Arduino_IO7
GPIO_28 AA6 DIFFIO_TX_RX_B15P DIFFIO_TX_RX_B28P V13
GPIO_26 AA7 DIFFIO_TX_RX_B16N DIFFIO_TX_RX_B34N W14
GPIO_10 W5 DIFFIO_TX_RX_B16P DIFFIO_TX_RX_B34P R13
GPIO_8 W6 DIFFIO_TX_RX_B1N DIFFIO_TX_RX_B36N P13
Arduino_IO5 Y10 DIFFIO_TX_RX_B1P DIFFIO_TX_RX_B36P Y13 GSENSOR_INT2
GPIO_21 AA10 DIFFIO_TX_RX_B22N DIFFIO_TX_RX_B37N Y14 GSENSOR_INT1
U6 DIFFIO_TX_RX_B22P DIFFIO_TX_RX_B37P V14
U7 DIFFIO_TX_RX_B3N DIFFIO_TX_RX_B39N W15
W4 DIFFIO_TX_RX_B3P DIFFIO_TX_RX_B39P U15
W3 DIFFIO_TX_RX_B5N DIFFIO_TX_RX_B41N V16
GPIO_6 V7 DIFFIO_TX_RX_B5P DIFFIO_TX_RX_B41P AA17 Arduino_IO9
GPIO_4 V8 DIFFIO_TX_RX_B7N DIFFIO_TX_RX_B43N Y17
R9 DIFFIO_TX_RX_B7P DIFFIO_TX_RX_B43P V15
P9 DIFFIO_TX_RX_B9N DIFFIO_TX_RX_B45N W16
AA3 DIFFIO_TX_RX_B9P DIFFIO_TX_RX_B45P Y19 Arduino_IO12
AB4 VREFB3N0 DIFFIO_TX_RX_B49N W18
B B
IO_BANK3 DIFFIO_TX_RX_B49P AA13
VREFB4N0 AB14
IO_BANK4

10M50DAF484

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B MAX 10 Bank 3 & 4 A1

Date: Monday, September 19, 2016 Sheet 4 of 18

5 4 3 2 1
 5 4 3 2 1

SDRAM
DRAM_ADDR[12..0]
MAX10 Bank 5 & 6
12
DRAM_DQ[15..0]
12

DRAM_CKE U5C
12
DRAM_LDQM
D 12 D
DRAM_UDQM
12 MAX 10 RIGHT BANKS
DRAM_WE_N
12
DRAM_CAS_N BANK-5VCCIO = 3.3V BANK-6VCCIO = 3.3V
12
DRAM_RAS_N DRAM_ADDR4 U19 H21 DRAM_DQ10
12 DIFFIO_RX_R19N DIFFIO_RX_R39N
DRAM_CS_N DRAM_ADDR2 V18 H22 DRAM_DQ11
12 DIFFIO_RX_R19P DIFFIO_RX_R39P
DRAM_BA0 DRAM_ADDR3 U18 J21 DRAM_UDQM
12 DIFFIO_RX_R1P/RUP DIFFIO_RX_R41N
DRAM_BA1 DRAM_ADDR0 U17 J22 DRAM_DQ9
12 DIFFIO_RX_R1N/RDN DIFFIO_RX_R41P
DRAM_DQ5 W22 G19 DRAM_DQ14
DRAM_DQ4 Y22 DIFFIO_RX_R20N DIFFIO_RX_R42N G20 DRAM_DQ13
DRAM_DQ6 W20 DIFFIO_RX_R20P DIFFIO_RX_R42P F22 DRAM_DQ15
DRAM_ADDR1 W19 DIFFIO_RX_R21N DIFFIO_RX_R43N G22 DRAM_DQ12
DRAM_DQ0 Y21 DIFFIO_RX_R21P DIFFIO_RX_R43P M14
DRAM_DQ1 Y20 DIFFIO_RX_R22N DIFFIO_RX_R44N/DQ2R M15
DRAM_CS_N U20 DIFFIO_RX_R22P DIFFIO_RX_R44P/DQ2R E21 HEX32
DRAM_WE_N V20 DIFFIO_RX_R23N DIFFIO_RX_R45N E22 HEX31
DRAM_LDQM V22 DIFFIO_RX_R23P DIFFIO_RX_R45P N19 HEX55
DRAM_DQ7 V21 DIFFIO_RX_R24N DIFFIO_RX_R46N/DM2R N18 HEX53
R14 DIFFIO_RX_R24P DIFFIO_RX_R46P/DQ2R M20 HEX54
R15 DIFFIO_RX_R25N/DQ1R DIFFIO_RX_R47P/DQ2R N20 HEX56
SWITCH DRAM_BA1 T22 DIFFIO_RX_R25P/DQ1R DIFFIO_RX_R47N/DQ2R F20 HEX46
SW[9..0] DRAM_BA0 T21 DIFFIO_RX_R26N DIFFIO_RX_R48N F21 HEX30
14 DIFFIO_RX_R26P DIFFIO_RX_R48P
DRAM_ADDR5 T18 C22 HEX25
DRAM_ADDR6 T19 DIFFIO_RX_R27N/DM1R DIFFIO_RX_R49N D22 HEX37
C DIFFIO_RX_R27P/DQ1R DIFFIO_RX_R49P C
KEY DRAM_ADDR12 R20 L18 HEX52
DRAM_ADDR10 T20 DIFFIO_RX_R28N/DQ1R DIFFIO_RX_R51N/DQ2R M18
KEY[1..0] DRAM_RAS_N U22 DIFFIO_RX_R28P/DQ1R DIFFIO_RX_R51P/DQ2R L20
14 DIFFIO_RX_R29N DIFFIO_RX_R52N/DQ2R
DRAM_CAS_N U21 L19 HEX57
DRAM_DQ2 AA22 DIFFIO_RX_R29P DIFFIO_RX_R52P/DQ2R F18 HEX40
DRAM_DQ3 AA21 DIFFIO_RX_R2N DIFFIO_RX_R53N E19 HEX42
LED P14 DIFFIO_RX_R2P DIFFIO_RX_R53P E20 HEX41
LEDR[9..0] P15 DIFFIO_RX_R30N/DQ1R DIFFIO_RX_R54N F19 HEX45
14 DIFFIO_RX_R30P/DQ1R DIFFIO_RX_R54P
DRAM_CKE N22 K15
DRAM_DQ8 P21 DIFFIO_RX_R31N DIFFIO_RX_R55N/DQSN3R K14
DRAM_ADDR8 P18 DIFFIO_RX_R31P DIFFIO_RX_R55P/DQS3R D19 HEX35
DRAM_ADDR7 R18 DIFFIO_RX_R32N/DQSN1R DIFFIO_RX_R56N C20 HEX34
DRAM_ADDR11 P20 DIFFIO_RX_R32P/DQS1R DIFFIO_RX_R56P J18 HEX43
7-segment Display DRAM_ADDR9 P19 DIFFIO_RX_R33N/DQ1R DIFFIO_RX_R57N/DQ3R K18
HEX0[7..0] L22 DIFFIO_RX_R33P/DQ1R DIFFIO_RX_R57P/DQ3R K20 HEX51
14 DIFFIO_RX_R34N DIFFIO_RX_R58N/DQ3R
M21 K19
HEX1[7..0] M22 DIFFIO_RX_R34P DIFFIO_RX_R58P/DQ3R E17 HEX36
14 DIFFIO_RX_R35N DIFFIO_RX_R59N
N21 F17 HEX47
HEX2[7..0] P22 DIFFIO_RX_R35P DIFFIO_RX_R59P B21 HEX24
14 VREFB5N0 DIFFIO_RX_R60N
R22 B22 HEX26
HEX3[7..0] IO_BANK5 DIFFIO_RX_R60P J15
14 DIFFIO_RX_R61N/DM3R J14
HEX4[7..0] DIFFIO_RX_R61P/DQ3R A21 HEX23
14 DIFFIO_RX_R62N
B B20 HEX20 B
HEX5[7..0] DIFFIO_RX_R62P H18
14 DIFFIO_RX_R63N/DQ3R H19 HEX44
DIFFIO_RX_R63P/DQ3R H20
DIFFIO_RX_R64N/DQ3R J20 HEX50
DIFFIO_RX_R64P/DQ3R E18 HEX12
DIFFIO_RX_R70N/CK#_6 D18 HEX11
DIFFIO_RX_R70P/CK_6 D21
VREFB6N0 C21
IO_BANK6

10M50DAF484

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B MAX 10 Bank 5 & 6 A1

Date: Monday, September 19, 2016 Sheet 5 of 18

5 4 3 2 1
 5 4 3 2 1

MAX10 Bank 7 & 8

7-segment Display
HEX0[7..0]
14
HEX1[7..0]
14
HEX2[7..0]
14
U5D
HEX3[7..0]
D 14 D
HEX4[7..0]
MAX 10 TOP BANKS
14
HEX5[7..0] BANK-7VCCIO = 3.3V BANK-8VCCIO = 2.5V
14
HEX14 A17 C7
HEX15 A18 DIFFIO_RX_T10N DIFFIO_RX_T39N C8
HEX02 C15 DIFFIO_RX_T10P DIFFIO_RX_T39P A6
HEX03 C16 DIFFIO_RX_T15N DIFFIO_RX_T41N B7
SWITCH HEX17 A16 DIFFIO_RX_T15P DIFFIO_RX_T41P D8
SW[9..0] HEX13 B16 DIFFIO_RX_T16N DIFFIO_RX_T42P A4
14 DIFFIO_RX_T16P DIFFIO_RX_T43N
J13 A5
H14 DIFFIO_RX_T17N DIFFIO_RX_T43P E9
LEDR5 C13 DIFFIO_RX_T17P DIFFIO_RX_T44N A2
KEY HEX00 C14 DIFFIO_RX_T18N DIFFIO_RX_T45P A3
KEY[1..0] SW8 B14 DIFFIO_RX_T18P DIFFIO_RX_T45N B3
14 DIFFIO_RX_T19N DIFFIO_RX_T46P
SW7 A14 B4
HEX01 E15 DIFFIO_RX_T19P DIFFIO_RX_T46N B5
HEX04 E16 DIFFIO_RX_T1N DIFFIO_RX_T47P C4
LED E13 DIFFIO_RX_T1P DIFFIO_RX_T47N E8
LEDR[9..0] LEDR7 D14 DIFFIO_RX_T20N DIFFIO_RX_T48P D5
14 DIFFIO_RX_T20P DIFFIO_RX_T49N
E12 C5
LEDR4 D13 DIFFIO_RX_T21P DIFFIO_RX_T49P B1
J12 DIFFIO_RX_T21N DIFFIO_RX_T51N B2
H13 DIFFIO_RX_T22N DIFFIO_RX_T51P C2
C DIFFIO_RX_T22P DIFFIO_RX_T53N C
Arduino Digital Interface SW4 A12 C3
SW6 A13 DIFFIO_RX_T23N DIFFIO_RX_T53P D7
SW2 D12 DIFFIO_RX_T23P VREFB8N0 C6
SW3 C12 DIFFIO_RX_T24N IO_BANK8
Arduino_Reset_n LEDR2 A10 DIFFIO_RX_T24P
13 DIFFIO_RX_T25N
LEDR8 A11
SW0 C10 DIFFIO_RX_T25P
SW1 C11 DIFFIO_RX_T26N
LEDR9 B11 DIFFIO_RX_T26P
SW5 B12 DIFFIO_RX_T27N
J11 DIFFIO_RX_T27P
H12 DIFFIO_RX_T28N
KEY0 B8 DIFFIO_RX_T28P
LEDR1 A9 DIFFIO_RX_T31N
HEX06 C17 DIFFIO_RX_T31P
HEX05 D17 DIFFIO_RX_T2N
C9 DIFFIO_RX_T2P
LEDR3 B10 DIFFIO_RX_T30N
KEY1 A7 DIFFIO_RX_T30P
LEDR0 A8 DIFFIO_RX_T29P
SW9 F15 DIFFIO_RX_T29N
Arduino_Reset_n F16 DIFFIO_RX_T5N
HEX22 B19 DIFFIO_RX_T5P
HEX33 C19 DIFFIO_RX_T6N
B B
HEX16 B17 DIFFIO_RX_T6P
HEX10 C18 DIFFIO_RX_T7N
HEX27 A19 DIFFIO_RX_T7P
HEX21 A20 DIFFIO_RX_T8N
LEDR6 E14 DIFFIO_RX_T8P
HEX07 D15 DIFFIO_RX_T9N
B15 DIFFIO_RX_T9P
A15 VREFB7N0
IO_BANK7

10M50DAF484

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B MAX 10 Bank 7 & 8 A1

Date: Monday, September 19, 2016 Sheet 6 of 18

5 4 3 2 1
 5 4 3 2 1

MAX10 Clock
U5E
UBT_CLK_24
18
MAX 10 CLOCK
GPIO 0
BANK-2 VCCIO = 3.3V
GPIO_[35..0] N4 P3
4,13 DIFFIO_RX_L28N/CLK0N DIFFIO_RX_L38N/DPCLK0
ADC_CLK_10 N5 R3
D M8 DIFFIO_RX_L28P/CLK0P DIFFIO_RX_L38P/DPCLK1 T5 D
M9 DIFFIO_RX_L36N/CLK1N DIFFIO_RX_L59N/PLL_L_CLKOUTN T6
DIFFIO_RX_L36P/CLK1P DIFFIO_RX_L59P/PLL_L_CLKOUTP

BANK-3 VCCIO = 3.3V

GPIO_2 V9
GPIO_0 V10 DIFFIO_TX_RX_B18N/CLK6N
R11 DIFFIO_TX_RX_B18P/CLK6P
SDRAM MAX10_CLK1_50 P11 DIFFIO_TX_RX_B20N/CLK7N
DRAM_CLK DIFFIO_TX_RX_B20P/CLK7P
12

BANK-4 VCCIO = 3.3V

W17
DIFFIO_TX_RX_B57N/PLL_B_CLKOUTN V17
DIFFIO_TX_RX_B57P/PLL_B_CLKOUTP

BANK-6 VCCIO = 3.3V

N15 L15
MAX10_CLK2_50 N14 DIFFIO_RX_R38N/CLK2N DIFFIO_RX_R50N/DPCLK2/DQSn2R L14 DRAM_CLK
K21 DIFFIO_RX_R38P/CLK2P DIFFIO_RX_R50P/DPCLK3/DQS2R G17
K22 DIFFIO_RX_R40N/CLK3N DIFFIO_RX_R69N/PLL_R_CLKOUTN H17
C DIFFIO_RX_R40P/CLK3P DIFFIO_RX_R69P/PLL_R_CLKOUTP C

BANK-8 VCCIO = 2.5V

E10
E11 DIFFIO_RX_T38N/CLK4N
J10 DIFFIO_RX_T38P/CLK4P E6
H11 DIFFIO_RX_T40P/CLK5P DIFFIO_RX_T52N/PLL_T_CLKOUTN D6
DIFFIO_RX_T40N/CLK5N DIFFIO_RX_T52P/PLL_T_CLKOUTP

10M50DAF484

CAD Note: CAD Note:

Place near pin 3 and 5 Place near IC power pin
(C3 & C322) L3 220 ohm, 0.4A
VCC1P8 VCC3P3
C50 C51 C53 C56 C52 C8
0.01u 1n 0.1u 0.1u 0.1u 4.7u
50V 50V 10V 10V 10V 6.3V
B B
10
13
3

U3
C9 4p
VDD

Vddout
Vddout
Vddout

6.3V
DNI Y1
3

24.00MHz 1 17 R57 18.2 UBT_CLK_24 Default: 24MHz

4 2 Xin/Clk Y1
15 Default: 24MHz
20 Y2
1

Xout 14 R17 18.2 ADC_CLK_10

Y3 Default: 10MHz
C11 4p 2
6.3V S0 7 R10 18.2 MAX10_CLK2_50
Y4 Default: 50MHz
DNI 19
S1/SDA 8 R9 18.2 MAX10_CLK1_50
Y5 Default: 50MHz
R19 4.7K 18
S2/SCL 12
VCC3P3 Y6 Default: 50MHz
R18 4.7K 4
Vctrl 11 Default: 50MHz
GND
GND
GND

Y7

CDCE937PWRG4
5
9
16

A Default : I2C Address 0xDA/0xDB A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B MAX 10 Clocks A1

Date: Monday, September 19, 2016 Sheet 7 of 18

5 4 3 2 1
 5 4 3 2 1

MAX10 Configuration
JTAG Interface
JTAG_TCK
18
JTAG_TMS
18
JTAG_TDI
18
JTAG_TDO
D 18 D
JTAG_EN
18

FPGA CONFIG
NCONFIG
18
NSTATUS
18
CONF_DONE
18
CONFIG_SEL
18

VCC2P5

C VCC2P5 VCC2P5 VCC2P5 VCC2P5 VCC2P5 C

U5F

R68 R62 R63 MAX 10 Configuration

10K 10K 10K R79 R78 R74 R24 R28
10K 10K 10K 10K 1K Boot Select
BANK-1B BANK-8 DNI
VCCIO = 2.5V VCCIO = 2.5V JP5
JTAG_EN K9 H9 NCONFIG
JTAG_TCK G2 DIFFIO_RX_L15P/JTAGEN NCONFIG H10 CONFIG_SEL 1
JTAG_TMS H2 DIFFIO_RX_L17P/TCK CONFIG_SEL D9 2
JTAG_TDO L4 DIFFIO_RX_L17N/TMS DIFFIO_RX_T42N/DEV_CLRN D10
R60 R61 JTAG_TDI M5 DIFFIO_RX_L18N/TDI DIFFIO_RX_T44P/DEV_OE F7 R23 DNI
0 1K DIFFIO_RX_L18P/TDO DIFFIO_RX_T48N/CRC_ERROR G9 NSTATUS 10K 1X2 Header
DNI DIFFIO_RX_T50P/NSTATUS F8 CONF_DONE
DIFFIO_RX_T50N/CONF_DONE
Design Note:
C61 Optional termination resistor BOOT Select
12p for JTAG TCK Default Disable (Jumper Open)
DNI 10M50DAF484
CAD Note:
Place near JTAG TCK pin OPEN = configuration image 0 (Low)
SHORT = configuration image 1 (High)
B B

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B MAX 10 Configuration A1

Date: Monday, September 19, 2016 Sheet 8 of 18

5 4 3 2 1
 5 4 3 2 1

MAX10 Power
VCC1P2_VCC VCC1P2_VCCD
L10 30ohm, 3A

C77
D 4.7u D

U5G
Place filter close to VCCIO1A pins.
VCC1P2_VCC VCC1P2_VDDADC MAX 10 POWER
L4 30ohm, 3A VCC1P2_VCC VCC2P5 VCC2P5
L9
N12 L6
N10 VCC VCCIO1A K7
C85 M13 VCC VCCIO1A M6 C86 220 ohm, 0.4A
C16
M12 VCC VCCIO1B L7 0.1u
0.1u VCC VCCIO1B 300mA
10u M11
L12 VCC R6
L11 VCC VCCIO2 P7
L10 VCC VCCIO2 N7
K13 VCC VCCIO2 N6
K11 VCC VCCIO2
CAD Notes: VCC1P2_VCCD VCC U9
VCCIO3 VCC3P3
Place the 10uF cap close to ferrite bead. U8
Place the 0.1uF cap close to MAX10 pin. T7 VCCIO3 T9
G16 VCCD_PLL1 VCCIO3 T11
C VCCD_PLL2 VCCIO3 C
G7 T10
U16 VCCD_PLL3 VCCIO3
VCC2P5_VCCA VCCD_PLL4 U14
REF_VCC2P5 ADC_VREF VCCIO4 VCC3P3
U12
R8 VCCIO4 U11
H15 VCCA1 VCCIO4 T13
R77 1 H8 VCCA2 VCCIO4 T12
VCC1P2_VDDADC T15 VCCA3 VCCIO4
VCCA4 T17
VCC2P5_VCCADC VCCIO5 VCC3P3
CAD Notes: C139 C120 R17
Put the caps J7 VCCIO5 R16
close to MAX10 pin. 10u 1u H7 VCCINT VCCIO5 P16
VCCA_ADC VCCIO5 N16
VCCIO5
ADC_VREF H6 N17 VCC3P3
ADC_VREF VCCIO6 M17
VCCIO6 L16
G5 VCCIO6 K17
J5 ANAIN1 VCCIO6 K16
NC ANAIN2 VCCIO6 J17
VCCIO6 H16
VCCIO6
G14 VCC3P3
VCCIO7 G13
B B
VCC2P5_CORE VCC2P5_VCCA VCCIO7 G12
L11 30ohm, 3A VCCIO7 F14
VCCIO7 F12
VCCIO7
G11 VCC2P5
C122 VCCIO8 G10
C121
VCCIO8 F9
10u 0.1u VCCIO8 F11
VCCIO8

10M50DAF484

VCC2P5_CORE VCC2P5_VCCADC
L12 220ohm, 2.5A

C142 C119

10u 0.1u CAD Notes:

Place the 10uF cap close to ferrite bead.
Place the 0.1uF cap close to MAX10 pin.
A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B MAX10 Power A1

Date: Monday, September 19, 2016 Sheet 9 of 18

5 4 3 2 1
 5 4 3 2 1

MAX10 Ground

D U5H D

MAX 10 GROUND
K12
Y9 GND K10
Y15 GND GND K3
Y12 GND GND J6
W21 GND GND J2
V6 GND GND J19
V2 GND GND J16
V19 GND GND G8
U13 GND GND G6
U10 GND GND G21
T8 GND GND G18 CAD Notes: Place this FB close to MAX10 ADC_VREF.
T4 GND GND G15
T16 GND GND F13 L13 30ohm, 3A
T14 GND GND F10
R21 GND GND E7
R19 GND GND E2
P6 GND GND D4
P2 GND GND D20
P17 GND GND D16
N13 GND GND D11
C GND GND C
N11 B9
M7 GND GND B6
M19 GND GND B18
M16 GND GND B13
M10 GND GND AB22
L5 GND GND AB1
L21 GND GND AA4
L17 GND GND AA18
L13 GND GND A22
GND GND A1
GND
TP3
L3 E5
REFGND H5 DNU NC1 F6
REFGND NC2

10M50DAF484

1. Use REFGND as ground reference.

2. Route analog input signal adjacent to AVSSREF as possible.

B B

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B MAX10 Ground A1

Date: Monday, September 19, 2016 Sheet 10 of 18

5 4 3 2 1
 5 4 3 2 1

MAX10 Decoupling

VCC1P2_VCC
D VCC2P5_VCCA D

C104 C15 C90 C93 C91 C110 C96 C112 C92 C89 C107 C111 C106 C95
C115 C94 C97 C114
10u 10u 1u 1u 1u 1u 1u 1u 1u 1u 22n 22n 10n 10n
0.1u 0.1u 0.1u 0.1u

CAD Note:
Place capacitor near FPGA pins CAD Notes:
Place a 1uF cap close to each MAX10 VCCA pins.

VCC1P2_VCCD

C116 C123 C66 C76

0.1u 0.1u 0.1u 0.1u

C C

CAD Notes:
Place a 0.1uF cap close to each MAX10 VCCD pins.

VCC3P3

C98 C71 C73 C75 C70 C68 C74 C72 C69 C65 C63 C64 C87 C62 C99 C67 C113 C118 C117 C100 C101
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
4.7u 4.7u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 10V 10V 10V 10V 10V 10V 10V 10V

CAD Notes:
Place these caps close to MAX10 VCCIO2, VCCIO3, VCCIO4, VCCIO7 and VCCIO8 pins.

B B

VCC2P5

C156 C126 C124 C125 C143 C88 C105 C109 C108

10u 1u 1u 0.1u 0.1u 0.1u 0.1u 10n 10n

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B MAX10 Decoupling A1

Date: Monday, September 19, 2016 Sheet 11 of 18

5 4 3 2 1
 5 4 3 2 1

CAD Note:
Place near IC power pin

VCC3P3

D D
C14 C103 C27 C25 C12 C102 C13
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
10V 10V 10V 10V 10V 10V 10V

SDRAM VCC3P3
DRAM_ADDR[12..0]
5
DRAM_DQ[15..0]
5

14
27

43
49
1

3
9
U4

VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
DRAM_CLK
7
DRAM_CKE DRAM_ADDR0 23 2 DRAM_DQ0
5 A0 D0
DRAM_LDQM DRAM_ADDR1 24 4 DRAM_DQ1
5 A1 D1
DRAM_UDQM DRAM_ADDR2 25 5 DRAM_DQ2
5 A2 D2
DRAM_ADDR3 26 7 DRAM_DQ3
DRAM_WE_N DRAM_ADDR4 29 A3 D3 8 DRAM_DQ4
5 A4 D4
DRAM_CAS_N DRAM_ADDR5 30 10 DRAM_DQ5
5 A5 D5
DRAM_RAS_N DRAM_ADDR6 31 11 DRAM_DQ6
C 5 A6 D6 C
DRAM_CS_N DRAM_ADDR7 32 13 DRAM_DQ7
5 A7 D7
DRAM_BA0 DRAM_ADDR8 33 42 DRAM_DQ8
5 A8 D8
DRAM_BA1 DRAM_ADDR9 34 44 DRAM_DQ9
5 A9 D9
DRAM_ADDR10 22 45 DRAM_DQ10
DRAM_ADDR11 35 A10 D10 47 DRAM_DQ11
VCC3P3 DRAM_ADDR12 36 A11 SDRAM 32Mx16 D11 48 DRAM_DQ12
DRAM_CLK 38 A12 D12 50 DRAM_DQ13
DRAM_CKE 37 CLK D13 51 DRAM_DQ14
DRAM_LDQM 15 CKE D14 53 DRAM_DQ15
DRAM_UDQM 39 LDQM D15
RN13 4.7K UDQM
1 8 DRAM_CS_N DRAM_WE_N 16
2 7 DRAM_RAS_N DRAM_CAS_N 17 nWE
3 6 DRAM_CAS_N DRAM_RAS_N 18 nCAS
4 5 DRAM_WE_N DRAM_CS_N 19 nRAS
DRAM_BA0 20 nCS
R33 4.7K DRAM_CKE DRAM_BA1 21 BA0
BA1

VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
28
41
54

6
12
46
52
B B

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B SDRAM A1

Date: Monday, September 19, 2016 Sheet 12 of 18

5 4 3 2 1
 5 4 3 2 1

GPIO
GPIO JP1 Arduino UNO Rev3
JP2
GPIO_[35..0] Clock_in GPIO_0 1 2 GPIO_1 Arduino_IO15 SCL
4,7 1
Clock_in GPIO_2 3 4 GPIO_3 JP7 Arduino_IO14 SDA
GPIO_4 5 6 GPIO_5 2
GPIO_6 7 8 GPIO_7 1 3
GPIO_8 9 10 GPIO_9 Arduino_Reset_n 2 Arduino_IO13 4 SCK
Arduino Digital Interface 11 12 3 Arduino_IO12 5 MISO
VCC5 VCC3P3 4 6
Arduino_IO[15..0] GPIO_10 13 14 GPIO_11 Arduino_IO11 MOSI
D 4 VCC5 5 7 D
GPIO_12 15 16 GPIO_13 Arduino_IO10 SS
Arduino_Reset_n GPIO_14 17 18 GPIO_15 L15 30ohm, 3A 6 Arduino_IO9 8
4 7 9
GPIO_16 19 20 GPIO_17 Arduino_IO8
VCC5 8 10
GPIO_18 21 22 GPIO_19
GPIO_20 23 24 GPIO_21 HEADER 8 HEADER 10
GPIO_22 25 26 GPIO_23
Analog input interface GPIO_24 27 28 GPIO_25 JP3
29 30 Arduino_IO7
VCC3P3 1
ADC1IN[8..1] GPIO_26 31 32 GPIO_27 JP8 Arduino_IO6
3 2
GPIO_28 33 34 GPIO_29 ADC_IN0 Arduino_IO5
GPIO_30 35 36 GPIO_31 ADC_IN1 1 Arduino_IO4 3
GPIO_32 37 38 GPIO_33 ADC_IN2 2 Arduino_IO3 4
GPIO_34 39 40 GPIO_35 ADC_IN3 3 Arduino_IO2 5
ADC_IN4 4 Arduino_IO1 6
ADC_IN5 5 Arduino_IO0 7
2x20_BOX_Header 6 8
HEADER 6 HEADER 8

TP1 DNI
ADC_IN6
VCC3P3_VCCA TP_YELLOW
VCC3P3_VCCA
TP2 DNI
C151 ADC_IN7
C VCC3P3_VCCA C
0.1u C148 TP_YELLOW
10V VCC3P3_VCCA 0.1u
U8A 10V
4

U8B VCC5

4
V+ 3 R94 316 ADC_IN1 JP4
+
ADC1IN2 R37 10 1 V+ 5 R91 316 ADC_IN2 Arduino_IO12
+ 1 2
2 ADC1IN3 R36 10 7 Arduino_IO13 Arduino_IO11
V- - 3 4
C135 C153 R93 6 Arduino_Reset_n
V- - 5 6
1n 316 C136 C150 R92
11

1p MCP6244-E/SL 50V 1n 316 HEADER 2x3

11
DNI 1p MCP6244-E/SL 50V
DNI
VCC3P3

VCC3P3_VCCA
VCC3P3_VCCA
U8C
4

U8D R2 R3 R97

4
V+ 10 R90 316 ADC_IN3 2.2K 2.2K 10K
+
ADC1IN4 R35 10 8 V+ 12 R96 316 ADC_IN0 DNI DNI
+
- 9 ADC1IN1 R34 10 14
C137 V- C141 R89 13 Arduino_IO14
V- -
1n 316 C140 C152 R95 Arduino_IO15 Arduino Pin out
11

B 1p MCP6244-E/SL 50V 1n 316 Arduino_Reset_n B

11
DNI 1p MCP6244-E/SL 50V
DNI Pin.1

VCC3P3_VCCA Pin.1
VCC3P3_VCCA
U9A JP2
4

4 U9B JP7
V+ 3 R85 316 ADC_IN5
+
ADC1IN6 R38 10 1 V+ 5 R84 316 ADC_IN6
+
- 2 ADC1IN7 R39 10 7
C134 V- C149 R86 6
V- -
1n 316 C132 C147 R83 Pin.1
11

1p MCP6244-E/SL 50V 1n 316

11

Pin.1

Pin.1
DNI 1p MCP6244-E/SL 50V
DNI
JP4 JP3
JP8
VCC3P3_VCCA
VCC3P3_VCCA
U9C TP1
4

U9D TP2
4

V+ 10 R81 316 ADC_IN7

+
A ADC1IN8 R41 10 8 V+ 12 R87 316 ADC_IN4 A
+
- 9 ADC1IN5 R40 10 14
C129 V- C128 R82 13
V- - Copyright (c) 2016 by Terasic Inc. Taiwan.
1n 316 C131 C130 R88 All rights reserved.
11

1p MCP6244-E/SL 50V 1n 316 No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
11

DNI 1p MCP6244-E/SL 50V Title

DNI DE10-Lite
Size Document Number Rev
B Arduino Expansion Header A1

Date: Monday, September 19, 2016 Sheet 13 of 18

5 4 3 2 1
 5 4 3 2 1

SWITCH
SW[9..0]
User IO, 7-Seg, LED HEX07
HEX02
RN21
1
2
1K
8
7
DP0
C0 A0 10
HEX0
5 a
HEX01 3 6 B0 B0 9 b VCC3P3
HEX00 4 5 A0 C0 8 c
VCC3P3 VCC3P3 VCC3P3 VCC3P3 D0 5 1
KEY SW0 SW1 SW2 SW3 RN22 1K E0 4
d CA1
6
e CA2
KEY[1..0] 4 4 4 4 HEX05 1 8 F0 F0 2
5 f
1 1 1 1 RN15 120 HEX06 2 7 G0 G0 3 g
2 2 2 2 8 1 SW3 HEX04 3 6 E0 DP0 7 dp
LED 3 3 3 3 7 2 SW2 HEX03 4 5 D0
D 5 5 5 5 6 3 SW1 7Segment Display D
LEDR[9..0] 5 4 SW0
5
SLIDE SW SLIDE SW SLIDE SW SLIDE SW RN23 1K
HEX17 1 8 DP1 HEX1
HEX12 2 7 C1 A1 10 a
HEX10 3 6 A1 B1 9 b VCC3P3
HEX11 4 5 B1 C1 8 c
D1 5 d CA1
1
RN24 1K E1 4 e CA2
6
VCC3P3 VCC3P3 VCC3P3 VCC3P3 HEX15 1 8 F1 F1 2 f
SW4 SW5 SW6 SW7 HEX16 2 7 G1 G1 3 g
7-segment Display 4 4 4 4 HEX14 3 6 E1 DP1 7 dp
1 1 1 1 RN19 120 HEX13 4 5 D1
HEX0[7..0] 2 2 2 2 8 1 SW7 7Segment Display
6
3 3 3 3 7 2 SW6
HEX1[7..0] 5 5 5 5 6 3 SW5 RN25 1K
6
5 4 SW4 HEX20 1 8 A2 HEX2
HEX2[7..0] SLIDE SW SLIDE SW SLIDE SW SLIDE SW HEX21 2 7 B2 A2 10
6 a
HEX22 3 6 C2 B2 9 b VCC3P3
HEX3[7..0] HEX27 4 5 DP2 C2 8
6 c
D2 5 d CA1
1
HEX4[7..0] RN26 1K E2 4 6
6 e CA2
HEX25 1 8 F2 F2 2 f
HEX5[7..0] VCC3P3 VCC3P3 HEX26 2 7 G2 G2 3
C 6 g C
SW8 SW9 HEX24 3 6 E2 DP2 7 dp
4 4 HEX23 4 5 D2
1 1 RN20 120 7Segment Display
2 2 8 1 SW9
3 3 7 2 SW8 RN27 1K
5 5 6 3 HEX30 1 8 A3 HEX3
5 4 HEX31 2 7 B3 A3 10 a
SLIDE SW SLIDE SW HEX32 3 6 C3 B3 9 b VCC3P3
HEX37 4 5 DP3 C3 8 c
D3 5 d CA1
1
RN8 1K E3 4 e CA2
6
HEX35 1 8 F3 F3 2 f
HEX36 2 7 G3 G3 3 g
HEX34 3 6 E3 DP3 7 dp
VCC3P3 HEX33 4 5 D3
RN14 100K 7Segment Display
1 8
2 7 RN7 1K
3 6 HEX40 1 8 A4 HEX4
4 5 HEX41 2 7 B4 A4 10 a
HEX42 3 6 C4 B4 9 b VCC3P3
KEY0 HEX47 4 5 DP4 C4 8 c
KEY1 D4 5 d CA1
1
B RN6 1K E4 4 e CA2
6 B
HEX43 1 8 D4 F4 2 f
HEX44 2 7 E4 G4 3 g
KEY0 KEY1 HEX46 3 6 G4 DP4 7 dp
4 3 4 3 HEX45 4 5 F4
C127 C146 7Segment Display
1 2 1 2 1u 1u
10V 10V RN5 1K
TACT SW TACT SW HEX57 1 8 DP5 HEX5
HEX52 2 7 C5 A5 10 a
HEX51 3 6 B5 B5 9 b VCC3P3
HEX50 4 5 A5 C5 8 c
D5 5 d CA1
1
RN4 1K E5 4 e CA2
6
HEX55 1 8 F5 F5 2 f
HEX56 2 7 G5 G5 3 g
HEX54 3 6 E5 DP5 7 dp
HEX53 4 5 D5
7Segment Display

LEDR0 LEDR LEDR4 LEDR LEDR8 LEDR

2 1 2 1 2 1

A LEDR1 LEDR LEDR5 LEDR LEDR9 LEDR A

LEDR0 4 5 2 1 LEDR4 4 5 2 1 LEDR8 4 5 2 1
LEDR1 3 6 LEDR5 3 6 LEDR9 3 6
Copyright (c) 2016 by Terasic Inc. Taiwan.
LEDR2 2 7 LEDR2 LEDR LEDR6 2 7 LEDR6 LEDR 2 7 All rights reserved.
LEDR3 1 8 2 1 LEDR7 1 8 2 1 1 8 No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
RN16 330 LEDR3 LEDR RN17 330 LEDR7 LEDR RN18 330
DE10-Lite
2 1 2 1
Size Document Number Rev
B LED, 7'Segment, User I/O A1

Date: Monday, September 19, 2016 Sheet 14 of 18

5 4 3 2 1
 5 4 3 2 1

VGA
VGA_R[3..0]
VGA and Accelerometer
3
VGA_G[3..0] RN10 2K
3
8 1
VGA_B[3..0] VGA_R0 7 2
3
VGA_R1 6 3
VGA_R2 5 4
VGA_HS VGA_R3
D 3 D
VGA_VS RN1 1K
3
1 8
2 7
3
4
6
5
VGA
RN11 2K J2 VGA
8 1 VGA_R 1
VGA_G0 7 2 VGA_G 2 6
VGA_G1 6 3 VGA_B 3 1 11
VGA_G2 5 4 4
VGA_G3 5
6
RN2 1K 7
1 8 8
2 7 9
3 6 10
4 5 11
12
13
RN12 2K 14 10
8 1 15 5 15
C C
VGA_B0 7 2
VGA_B1 6 3

16

17
VGA_B2 5 4
VGA_B3

RN3 1K
1 8
2 7
3 6
4 5

VGA_HS R21 120

VGA_VS R20 120

Digital Accelerometer
GSENSOR_SDI
4

B
4
GSENSOR_SCLK Digital Accelerometer B
GSENSOR_INT1
4 VCC_Gsensor
GSENSOR_INT2
4 VCC_Gsensor VCC3P3
GSENSOR_CS_n Tie CS_n to high to I2C mode only
4
GSENSOR_SDO C7 C6
4
1u 0.1u R11
10V 10V 2.2K R14 R8 R16
DNI 10K 2.2K 2.2K
DNI
U1
VCC_VS 1 14 R7 0 GSENSOR_SCLK
2 VDD SCL_SCLK 13 R15 0 GSENSOR_SDI
R4 2.2K 3 GND SDA_SDI_SDIO 12 GSENSOR_SDO
VCC3P3 VCC_Gsensor DNI 4 RESERVED SDO_ALT_ADDRESS 11
5 GND RESERVED_1 10
L2 BEAD L1 BEAD 6 GND NC 9 GSENSOR_INT2
7 VS INT2 8 GSENSOR_INT1
C4 C2 C3 CS_n INT1
1u 4.7u 0.1u ADXL345
10V 6.3V 10V R13 R12
2.2K 2.2K
DNI DNI
A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.

GSENSOR_CS_n
Default : I2C Address 0xA6/0xA7 Title
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

DE10-Lite
Size Document Number Rev
B VGA and Accelerometer A1

Date: Monday, September 19, 2016 Sheet 15 of 18

5 4 3 2 1
 5 4 3 2 1

Power - 5V_DCIN / 1.2V

Power up Sequence:
VCC5--->
VCC2P5, VCC3P3 --->
VCC1P2_VCC
VCC5 VCC5 VCC5
D
5V Power from USB Port Overvoltage Protection VCC5 D

Threshold Voltage : 5.4 ~ 5.6V Q2

VCC5_USB D6 AO3415
R71 R69
PMEG2010AEB 470 470
C23 C33 DNI
D7 R29 0.1u 47u
330 C22 R32 10V 10V 1P2_POK R72 0
PMEG2010AEB 1u 100K DNI

2
10V
JP6 R30 6.8K Q1 D4 D3
1 D8 HE8550G LEDG LEDG
2 DNI
PMEG2010AEB Power Good 5V

3
Power - HDR D5
Power LED Power LED

1
D9
Input Power Range:

3
5.4 ~ 5.6 V PMEG2010AEB R31
BZX84C5V1 6.8K VCC1P2_VCC R70 1K 1 Q3 R73
DNI UTC8050 0
DNI

2
C C

Ramp Time
Tsoft-start = 1 msec
Switching Frequency : 2.25MHz
VCC5 U6 1.2V / 3A
14 5 VCC1P2
8 SVIN SW_1 6 VCC1P2 VCC1P2_VCC
C31 C30 C20 C19 9 PVIN_1 SW_2 11 L5 470nH Panasonic
3P3_POK 10u 10u 10u 10u 13 PVIN_2 SW_3 12 1 2 2R5TPE330MAZB R22 0.01
17 PVIN_DRV SW_4
10V 10V 10V 10V

1
R26 C21 + C18 C17
VCC5 R27 100K 1P2_POK 16 180K 22p 330u 100u
DNI PGOOD 2.5V 6.3V
B B

2
VCC5 R42 100K 15 18
DNI 20 RUN VFB
3P3_POK R75 0 2 TRACK/SS
DNI RT/SYNC

PGND_EPAD
VCC2P5_CORE R76 0 19 1 R25
ITH DDR 180K
C32 17
1u MODE SGND
10V
DNI
3

21

LTC3612EUDC#TRPBF

PCB1
MH1 MH2 MH3 MH4

PCB

FID8 FID5 FID6 FID11 FID7 FID1 FID12 FID3 FID2 FID4 FID10 FID9

A A

Copyright (c) 2016 by Terasic Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B Power - 12V, 5V A1

Date: Monday, September 19, 2016 Sheet 16 of 18

5 4 3 2 1
 5 4 3 2 1

Power - 3.3V / 2.5V

Ramp Time
Tsoft-start = 1 msec
Switching Frequency : 2.25MHz
VCC5 U7 3.3V / 3A
14 5 VCC3P3
D 8 SVIN SW_1 6 VCC3P3 VCC3P3 VCC3P3_VCCA D
C24 C35 C34 C26 9 PVIN_1 SW_2 11 L6 470nH Panasonic L14 30ohm, 3A
10u 10u 10u 10u 13 PVIN_2 SW_3 12 1 2 6TPE100MAZB
10V 10V 10V 10V PVIN_DRV SW_4

1
3P3_POK C155 C154
16
R48 C40 + C145 + C29 C28 10u 0.1u
VCC5 R46 100K 3P3_POK 16 165K 100u 100u 100u 6.3V 10V
DNI PGOOD 22p 6.3V 6.3V 6.3V

2
VCC5 R45 100K 15 18
20 RUN VFB
C39 2 TRACK/SS
1u RT/SYNC

PGND_EPAD
10V 19 1 R47
DNI ITH DDR 36.5K
17
MODE

SGND
LTC3612EUDC#TRPBF

21
C C

2.5V / 0.5A VCC2P5_CORE

Ramp Time = 2 msec VCC2P5 R99 0
VCC5 VCC2P5 VCC2P5_CORE
REG1 U13
1 4 5 1
BIAS OUT VIN VOUT
C36 VCC3P3 3 5 R44 52.3K C38 R98 10K 4 3 C41
1u IN ADJ 22u DNI ON OC 2.2u
10V 6 2 6.3V C157 2 10V
SHDN GND 7 R43 4.7u GND
C37 EP_GND 10K DNI TPS22945 DNI
10u LTC3025-1
10V

B B
VCC3P3 R80 10K C144 4.7u

DNI

1.8V / 0.5A
Ramp Time = 2 msec VCC1P8 Voltage Reference
VCC5 VCC1P8
REG2
1 4 VCC3P3_VCCA REF_VCC2P5
BIAS OUT U12
C42 VCC3P3 3 5 R53 33K C45 C46 1 2
1u IN ADJ 22u 2.2u VIN VOUT
10V 6 2 6.3V 10V C138 C133
SHDN GND 7 R52 0.47u 3 0.1u
C44 EP_GND 9.31K 10V GND 10V
10u LTC3025-1 REF3125
10V

A A

VCC3P3 R51 10K C43 4.7u

Copyright (c) 2016 by Terasic Inc. Taiwan.
All rights reserved.
DNI No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DE10-Lite
Size Document Number Rev
B Power - 1.8V, 2.5V, 3.3V A1

Date: Monday, September 19, 2016 Sheet 17 of 18

5 4 3 2 1
 5 4 3 2 1

VCC5 VCC5_UBT VCC3P3 VCC3P3 VCC2P5

L7 30ohm, 3A
VCC3P3 VCC3P3 VCC2P5
VCC5_USB VCC3P3 VCC5_UBT
L8 30ohm, 3A C78 C82 C59 C10 C54 C47
R67 330 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
DNI 10V 10V 10V 10V 10V 10V

63
13

31
45
59
80
94
9
C84 C60 C58 C79 C83 U2
0.1u 10u C81 0.1u 0.1u 10u

VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCINT
VCCINT
10V 10V 0.1u 10V 10V 6.3V

13
30

26
3
D 10V C55 C57 U10 D
0.1u 33n URXF 2 1

VCCIO
AVCC
VCC
VCC
J3 IO-B1-0 IO-B2-0
10V 16V UTXE 3 52
USB B-TYPE IO-B1-1 IO-B2-1
6 25 UD0 UWR 4 53
3 USB_DP R65 100K 3V3OUT D0 24 UD1 URD 5 IO-B1-2 IO-B2-2 54
D+ D- VCC5_USB D1 IO-B1-3 IO-B2-3
2 USB_DM 23 UD2 6 55
R66 100K R58 1.5K 5 D2 22 UD3 7 IO-B1-4 IO-B2-4 56
VCC3P3 RSTOUT# D3 IO-B1-5 IO-B2-5
1 DNI 21 UD4 8 57
4 R56 27 7 D4 20 UD5 UBT_MAX_24 12 IO-B1-6 IO-B2-6 58
GND VBUS
USBDP D5 19 UD6 14 IO-B1-7/GCLK0 IO-B2-7 61
R55 27 8 D6 18 UD7 15 IO-B1-8/GCLK1 IO-B2-8 62
USBDM D7 16 IO-B1-9 IO-B2-9/GCLK2 64
5

17 IO-B1-10 IO-B2-10/GCLK3 66
U11 27 FT245BL 16 URD 18 IO-B1-11 IO-B2-11 67
1 XTIN RD# 15 UWR VCC3P3 19 IO-B1-12 IO-B2-12 68
R1 1M 3 D+ 2 28 WR 14 UTXE 20 IO-B1-13 IO-B2-13 69
GND D- XTOUT TXE# 12 URXF PWRON 21 IO-B1-14 IO-B2-14 70
C1 0.1u TPD2EUSB30 USB_RESETn 4 RXF# 26 IO-B1-15 IO-B2-15 71 CONFIG_SEL
10V RESET# R54 ULED 27 IO-B1-16 IO-B2-16 72 CONF_DONE_DISP
10K CLK_6MHz 28 IO-B1-17 IO-B2-17 73 NCONFIG
R59 EEPDATA 2 USB_RESETn 29 IO-B1-18 IO-B2-18 74 NSTATUS
10K EEPCLK 1 EEDATA 30 IO-B1-19 EPM240T100 IO-B2-19 75 CONF_DONE
CLK_6MHz R64 22 EEPCS 32 EESK 11 SI_WU SI_WU 33 IO-B1-20 IO-B2-20 76
VCC3P3 31 EECS SI/WU 10 PWRON EEPDATA 34 IO-B1-21 IO-B2-21 77
C TEST PWREN# IO-B1-22 IO-B2-22 C

AGND
C80 EEPCLK 35 78 JTAG_TDI

GND
GND
47p EEPCS 36 IO-B1-23 IO-B2-23 81 JTAG_TDO
50V 37 IO-B1-24 IO-B2-24 82
C48 LQFP-32 38 IO-B1-25 IO-B2-25 83 JTAG_TMS

29
9
17
0.1u 39 IO-B1-26 IO-B2-26 84 JTAG_TCK
10V 40 IO-B1-27 IO-B2-27 85 JTAG_EN
DNI 41 IO-B1-28 IO-B2-28 86
X1 UD0 42 IO-B1-29 IO-B2-29 87
1 4 UD1 43 IO-B1-30 IO-B2-30 88
EN VCC UD2 44 IO-B1-31/DEV_OE IO-B2-31 89
2 3 OSC_24 R5 0 UD3 47 IO-B1-32/DEV_CLRN IO-B2-32 90
GND OUT DNI UD4 48 IO-B1-33 IO-B2-33 91
24MHz DNI UBT_CLK_24 R6 22 UBT_MAX_24 UD5 49 IO-B1-34 IO-B2-34 92
UD6 50 IO-B1-35 IO-B2-35 95
C5 UD7 51 IO-B1-36 IO-B2-36 96
47p IO-B1-37 IO-B2-37 97
50V ISP_TCK 24 IO-B2-38 98
ISP_TMS 22 TCK IO-B2-39 99
ISP_TDI 23 TMS IO-B2-40 100
TDI IO-B2-41

GNDINT
GNDINT
ISP_TDO 25

GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
TDO

B B

11
65
10
32
46
60
79
93
Blaster Clock
UBT_CLK_24
7

JTAG to MAX10 (2.5V)

JTAG_TCK
8,18
JTAG_TMS
CPLD ISP VCC3P3
8
RN9 J1
JTAG_TDI 8 1 ISP_TCK
8 GND 1 2
7 2 ISP_TDO
JTAG_TDO 6 3 ISP_TMS 3 4 C49
8 VCC3P3 5 6
5 4 0.1u
JTAG_EN ISP_TDI 7 8 10V
8 9 10
10K
D1 LEDG Header_2x5
VCC3P3 R50 120 2 1 ULED DNI
A A
Configuration LOAD
Copyright (c) 2016 by Terasic Inc. Taiwan.
NCONFIG
8 All rights reserved.
D2 LEDG No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
NSTATUS R49 120 2 1 CONF_DONE_DISP Title
8 VCC2P5
CONF_DONE
DE10-Lite
8 CONF_DONE
Size Document Number Rev
CONFIG_SEL B USB Blaster A1
8
Date: Monday, September 19, 2016 Sheet 18 of 18
5 4 3 2 1