Bharati Vidyapeeth (Deemed to be University) College of

Engineering, Pune Department of Electronics & Telecommunication Engineering

Name of Student: Roll No.:

Experiment No. 5

AIM: To design and implementation of 1 bit and 2-bit comparator

THEORY: -

A magnitude digital Comparator is a combinational circuit that compares two digital or binary
numbers to find out whether one binary number is equal, less than, or greater than the other binary
number. We logically design a circuit for which we will have two inputs one for A and the other for
B and have three output terminals, one for A > B condition, one for A = B condition, and one for A
< B condition .There are different ways to implement a magnitude comparator, such as using a
combination of XOR, AND, and OR gates, or by using a cascaded arrangement of full adders

1 Bit Comparator:

A comparator used to compare two bits is called a single-bit comparator. It consists of two inputs
each for two single-bit numbers and three outputs to generate less than, equal to, and greater than
between two binary numbers.

Block Diagram:

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Truth Table:

A B A<B A=B A>B

K-map and Equations:

Logic Diagram

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2 Bit Comparator:

A comparator used to compare two binary numbers each of two bits is called a 2-bit Magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to, and greater
than between two binary numbers.

Block Diagram:

Truth Table:
A1 A0 B1 B0 A>B A=B A<B

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K Maps and Equations:

K-Map for A>B: K-Map for A=B:

K map for A<B

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Logic Diagram:

CONCLUSION:

Timely Presentation (06) Understanding Total (25) Signature of

5
 Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune
Department of Electronics & Telecommunication Engineering

Name of Student: Roll No.:

Experiment No. 6

AIM: To study and verify the truth table of 4-to-1 Line Multiplexer and Demultiplexer.

THEORY:

Multiplexing means transmitting a large number of information units over a smaller number of
channels or lines to minimize the number of circuits or communication channels.
.
Multiplexer:
A digital multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. The selection of a particular input line is controlled by a set
of selection lines. Normally, there are 2n input lines and n selection lines whose bit combinations
determine which input is selected.
A 4-line to 1-line multiplexer is shown in Fig.1 each of the four input lines, D 0 to D3, is applied to
one input of an AND gate. Selection lines S1 and S0 are decoded to select a particular AND gate.
The Function Table-1 lists the input-to-output path for each possible bit combination of the
selection lines.

Figure 1

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 Table-1

When this MST function is used in the design of a digital system, it is represented in block
diagram form as shown in Fig.2 To demonstrate the circuit operation, consider the case when S 1S0
= 10. The AND gate associated with input D2 has two of its inputs equal to 1 and the third input
connected to D2. The other three AND gates have at least one input equal to 0, which makes their
output equal to 0.

Figure 2

The OR gate output is now equal to the value of D2, thus providing a path from the selected input
to the output. A multiplexer is also called a data selector, since it selects one of many inputs and
steers the binary information to the output line.
The AND gates and inverters in the multiplexer resemble a decoder circuit and, indeed, they
decode the input selection lines. In general, a 2n-to-1 line multiplexer is constructed from an n- to-
2n decoder by adding to it 2n input lines, one to each AND gate.
The outputs of the AND gates are applied to a single OR gate to provide the 1-line output. The
size of a multiplexer is specified by the number 2n of its input lines and the single output line. It is
then implied that it also contains n selection lines. A multiplexer is often abbreviated as

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MUX.

Multiplexer ICs may have an enable input to control the operation of the unit. When the enable
input is in a given binary state, the outputs are disabled, and when it is in the other state (the
enable state), the circuit functions as a normal multiplexer. The enable input (sometimes called
strobe) can be used to expand two or more multiplexer ICs to a digital multiplexer with a larger
number of inputs.
In some cases two or more multiplexers are enclosed within one IC package. The selection and
enable inputs in multiple-unit ICs may be common to all multiplexers.

PROCEDURE:

1. First make sure that toggle switches of input section are Off (i.e. in downward direction).
2. Connect bits I0, I1, I2, I3, I4 and I5 of Input Section to the inputs D0, D1, D2, D3 and selection
lines S1 and S2 of 4-to-1 Line Multiplexer respectively.
3. Connect outputs of the Multiplexer Y to O1 or any other terminal of the Output Section.
4. Connect +5V adaptor on the DC socket provided on the trainer.
5. Switch On the power supply.
6. Now using toggle switches of Input Section provide input to the multiplexer as per below truth
table. (In the observation table)
7. Observe the outputs, record it in observation table and verify & compare the outputs of this
truth table with table 1.
Note:
• When the toggle switch is in the upward direction, LED will glow which represents the Logic
1 (i.e. +5V).
• When the toggle switch is in the downward direction, LED will not glow which represents the
Logic 0 (i.e. 0V).

RESULT:

Inputs Output

D0 D1 D2 D3 S1 S0 Y
1 0 1 0 0 0
0 1
1 0
1 1

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DEMULTIPLEXER:

Demultiplexing is the reverse process of multiplexer. It is to break one data or information stream
into several streams, transfer them simultaneously over several communication channels, and
recreate the original data stream
Demultiplexer:
A demultiplexer is a circuit that receives information on a single line and transmits this
information on one of 2n possible output lines. The selection of a specific output line is controlled
by the bit values of n selection lines. Fig. 1 shows a 1-to-4 Line Demultiplexer.

E line is taken as a data input line and lines S1 and S0 are taken as the selection lines. This is
shown in Fig.2. The single input variable E has a path to all four outputs, but the input
information is directed to only one of the output lines, as specified by the binary value of the two
selection lines S1 and S0. This can be verified from the truth table of this circuit, shown in Table-
1.
If the input value E = 1 then all outputs are maintained at 1 irrespective of the values of selection
lines S1 and S0. E = 1, then all outputs = 1 and if the Selection Lines S 1S0 = 00, then output D0 =
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E, while all other outputs are maintained at1. Selection Lines S 1S0 = 01, then output D1 = E, while
all other outputs are maintained at1. Selection Lines S1S0 = 10, then output D2 = E, while all other
outputs are maintained at1and Selection Lines S 1S0 = 11, then output D3 = E, while all other
outputs are maintained at1.

PROCEDURE:

1. First make sure that the toggle switches of input section are Off (i.e. in downward direction).
2. Connect bits I0, I1 and I2 of Input Section to the inputs E, S1 and S0 of 1-to-4 Line
Demultiplexer respectively.
3. Connect outputs of the Demultiplexer D0, D1, D2 and D3 to O1, O2, O3 and O4 of the Output
Section.
4. Connect +5 V adaptor to the DC socket provided on the trainer.
5. Switch On the power supply.
6. Now using toggle switches of Input Section provide input to the demultiplexer as per below
truth table. (In the observation table)
7. Observe the outputs, record it in observation table and verify & compare the outputs of this
truth table with table 1.
Note:
• When the toggle switch is in the upward direction, LED will glow which represents the Logic
1 (i.e. +5V).
• When the toggle switch is in the downward direction, LED will not glow which represents the
Logic 0 (i.e. 0V).

RESULT:

Inputs Outputs

E S1 S2 D0 D1 D3 D4
1 X X

0 0 0

0 0 1
0 1 0

0 1 1

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CONCLUSION:

Timely Presentation (06) Understanding Total (25) Signature of

11
 Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune
Department of Electronics & Telecommunication Engineering

Name of Student: Roll No.:

Experiment No. 7

AIM: Study of Flip Flops (SR, JK, D, T)

THEORY:

A flip flop in digital electronics is a circuit with two stable states that can be used to store binary
data. The stored data can be changed by applying varying inputs. Flip-flops and latches are
fundamental building blocks of digital electronics systems used in computers, communications, and
many other types of systems. Both are used as data storage elements.

1) SR Flip Flop: -

This is the most common flip-flop among all. This simple flip-flop circuit has a set input (S) and a
reset input (R). In this system, when you Set “S” as active, the output “Q” would be high, and “Q‘”
would be low. Once the outputs are established, the wiring of the circuit is maintained until “S” or
“R” go high, or power is turned off.

Circuit Diagram and Truth Table

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 JK Flip-Flop

Due to the undefined state in the SR flip-flops, another flip-flop is required in electronics. The JK
flip-flop is an improvement on the SR flip-flop where S=R=1 is not a problem. However, the outputs
are the same when one tests the circuit practically. In simple words, If J and K data input are
different (i.e. high and low), then the output Q takes the value of J at the next clock edge. If J and K
are both low, then no change occurs. If J and K are both high at the clock edge, then the output will
toggle from one state to the other. JK Flip-Flops can function as Set or Reset Flip-flops.

Circuit Diagram and Truth Table

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 D Flip-Flop

D flip-flop is a better alternative that is very popular with digital electronics. They are commonly
used for counters and shift registers and input synchronization. In the D flip-flops, the output can
only be changed at the clock edge, and if the input changes at other times, the output will be
unaffected.

Circuit Diagram and Truth Table

T Flip-Flop

A T flip-flop is like a JK flip-flop. These are basically single-input versions of JK flip-flops. This
modified form of the JK is obtained by connecting inputs J and K together. It has only one input
along with the clock input. These flip-flops are called T flip-flops because of their ability to
complement their state i.e. Toggle, hence they are named Toggle flip-flops.

Circuit Diagram and Truth Table

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CONCLUSION:

Timely Presentation Understanding Total (25) Signature of

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