E.G.S. PILLAY ENGINEERING COLLEGE Rev.

0
(An Autonomous Institution, Affiliated to Anna University, Chennai)
COE/2018/QB
Nagore Post, Nagapattinam – 611 002, Tamilnadu.

1902EC405 - MICROPROCESSORS AND MICROCONTROLLERS

Academic Year : 2018-2019 Programme : B.E-ECE
Question Bank
Year / Semester : II / IV Course Coordinator : M. Nuthal Srinivasan

Course Objectives Course Outcomes:

1. To teach the architecture and functions a) Restate hardware ,software and programming concepts of
of 8085 and 8086 Microprocessors Microprocessor
2. To impart the concepts of 8051 b) Summarize architecture, instructions and addressing modes
microcontroller of 8086 Microprocessor
3. To convey aspects of I/O and Memory c) Describe addressing modes, Architecture, pins of 8051
Interfacing circuits Microcontroller
4. To train basic knowledge about d) Illustrate interfacing of Serial, parallel, Keyboard ,Display
advanced processors with Microcontroller
e) apply programming concepts to make assembly language
programs
f) Recall features ,registers of Advanced and Pentium
Processors

PART – A ( 2 Mark Questions With Key)

S.No Questions Mark COs BTL
UNIT I – INTRODUCTION TO MICROPROCESSORS
1 Define Microprocessor 2
Microprocessor is a multipurpose, programmable, clock-driven,
register based electronic device that reads binary instructions from a storage
device called memory. 2 1 K1
It accepts binary data as input and processes data according to those
instructions, and provides as output.

2 Define mnemonics 2
The short-hand form of describing the instructions is called mnemonics. The
mnemonics are given by the manufacturers of microprocessors and
programmable devices 2 1 K1

3 What is the drawback in machine language and 2 1 K1

assembly language programs?
The machine language and assembly language programs are 2
machine dependent. The programs developed using these languages
for a particular machine cannot be directly run on another machine
4 Why data bus is bi-directional? 2 1 K1
The microprocessor has to fetch (read) the data from memory 2
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or input device for processing and after processing, it has to store

(write) the data to memory or output device. Hence the data bus is bi-
directional
5 Write the flags of 8085 2 1 K1
The 8085 has nine flags and they are 2
1. Carry Flag (CF)
2. Parity Flag (PF)
3. Auxiliary carry Flag (AF)
4. Zero Flag (ZF)
5. Sign Flag (SF)
6 What are different types of instruction available in 8085? 2 1 K1
The instructions of 8085 can be categorized into the following five 2
 Data transfer MOV Rd,Rs, STA 16-bit
 Arithmetic ADD R DCR M
 Logical XRI 8-bit RAR
 Branching JNZ CALL 16-bit
Machine control HLT NOP
7 What is the function of the Program Counter in 8085? 2 1 K1
Program is a sequence of instructions. 2
Microprocessor fetches these instructions from memory and executes them
sequentially. The program counter is a special purpose register which, at a
given time, stores the address of the next instruction to be fetched. It acts as a
pointer to next instructions
8 What is the necessary to have two status lines S1 and S0 in 8085? 2 1 K1
It is used to identify the current operations of the data bus. These are listed 2
below
S1 S0 OPERATION
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
9 How the 8085 processor differentiates a Memory access 1 K1
(read/write) and 1/0 access (read/write)? 2
The memory access and 1/0 access is differentiated using IO/M signal. 2
The 8085 processor asserts IO/ M low for memory read/write
operation and 10 I M is asserted high for 1/0 read/write operation
10 What is Software interrupts? 2 1 K1
The Software interrupts are program instructions. These 2
instructions are inserted at desired locations in a program. While
running a program, if software interrupt instruction is encountered
then the processor executes an interrupt service routine
11 What happens to the 8085 processor when it is reset? 2 1 K1
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When the 8085 processor is reset it execute the first 2

instruction at the OOOOH location. The 8085 resets (clears)
instruction register, interrupt mask bits and other registers.
12 What is an ALE? 2 1 K1
The ALE (Address Latch Enable) is a signal used to 2
demultiplex the address and data lines, using an external latch.
It is used to enable the external latch.
13 Draw and specify the complete bit configuration of 8085 flag Register 2 1 K1
D7 D6 D5 D4 D3 D2 D1 D0 2
S Z - AC - P - CY
 S- Sign Flag . If D7 =1 , then sign flag is set,
otherwise rest.
 Z-Zero flag. If ALU operation results in zero, then this
flag is set, Otherwise it is reset.
 AC-Auxilliary flag. In an arithmetic operation ,when a
carry is generated by digit D3 and passed on to digit D4, the
AC flag is set. Otherwise it is reset.
 P-Parity Flag. If the result of an arithmetic or logic
operation has an even number of 1’s then this flag is set.
Otherwise it is reset.
 CY-Carry Flag. If an arithmetic operation results in a
carry, the carry flag is set. Otherwise it is reset.
14 What is Stack Pointer? 2 1 K1
The stack is a reserved area of the memory in the RAM where the 2
temporary information may be stored. A 16-bit stack pointer is used to hold
the address of the most recent stack entry.
15 List the limitations of 8 bit microprocessor 2 1 K1
 Lower Execution Speed 2
 It can address less memory size
Few instructions are available.

PART – B (12 Mark Questions with Key)

S.N Questions Mark COs BTL
o
UNIT I – INTRODUCTION TO MICROPROCESSORS
1 Writing a simple program of adding two hexadecimal numbers 23H and 84H
and saving the result in a register in assembly language is illustrated below 1 K2
12
Algorithm 8
1. Load the 1st number 23H in one register.
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2. Load the 2nd number 84H in another register.

3. Add the contents of the two registers.
4. Save the result in any register.
5. End the program.
Flow Chart
The above steps can be represented in a pictorial format with the help
of flowchart.

PROGRAM:
MVI A, 23H
MVI B, 84H,
4
ADD B
STA 4500
HLT
2 Explain in details about interrupts in 8085 12 1 K2
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 Interrupt is signals send by an external device to the processor, to request the processor to perform a particular
task or work.
 Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and
the microprocessor.
 The processor will check the interrupts always at the 2nd T-state of last machine cycle.
 If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the peripheral.
 The vectored address of particular interrupt is stored in program counter.
 The processor executes an interrupt service routine (ISR) addressed in program counter.
 It returned to main program by RET instruction.
Types of Interrupts:
It supports two types of interrupts.
 Hardware
 Software
Software interrupts:
 The software interrupts are program instructions. These instructions are inserted at desired locations in a
program.
 The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these interrupts can be
6
calculated as follows.
 Interrupt number * 8 = vector address
 For RST 5,5 * 8 = 40 = 28H
 Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.
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Hardware interrupts:
 An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the
processor.
 If the interrupt is accepted then the processor executes an interrupt service routine.
The 8085 has five hardware interrupts
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR

TRAP:
 This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.
 TRAP bas the highest priority and vectored interrupt.
 TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is
acknowledged.
 In sudden power failure, it executes a ISR and send the data from main memory to backup memory.
 The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the
same time then HOLD is recognized first and then TRAP is recognized).
 There are two ways to clear TRAP interrupt.
1. By resetting microprocessor (External signal)
2. By giving a high TRAP ACKNOWLEDGE (Internal signal)
RST 7.5:
 The RST 7.5 interrupt is a maskable interrupt.
 It has the second highest priority.
 It is edge sensitive. ie. Input goes to high and no need to maintain high state until it recognized.
 Maskable interrupt. It is disabled by,
1.DI instruction 2. System or processor reset. 3.After reorganization of interrupt.
 Enabled by EI instruction.
RST 6.5 and 5.5:
 The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until it recognized.
 Maskable interrupt. It is disabled by,
1.DI, SIM instruction 2.System or processor reset. 3.After reorganization of interrupt.
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3 Explain the addressing modes of 8085 12 1 K2

Every instruction of a program has to operate on a data. The method
of specifying the data to be operated by the instruction is called Addressing.
The 8085 has the following 5 different types of addressing.

1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing

1. IMMEDIATE ADDRESSING:
In immediate addressing mode, the data is specified in the instruction
itself. The data will be a part of the program instruction.
 EX. MVI B, 3EH - Move the data 3EH given in the
instruction to B register;
 LXI SP, 2700H.
6
2. DIRECT ADDRESSING:
In direct addressing mode, the address of the data is specified in the
instruction. The data will be in memory. In this addressing mode, the program
instructions and data can be stored in different memory.
 EX. LDA 1050H - Load the data available in memory
location 1050H in to accumulator;
SHLD 3000H
3. REGISTER ADDRESSING:
In register addressing mode, the instruction specifies the name of the
register in which the data is available.
 EX. MOV A, B - Move the content of B register to A
register;
SPHL; ADD C.

4. IMMEDIATE ADDRESSING:
In immediate addressing mode, the data is specified in the instruction
6
itself. The data will be a part of the program instruction.
 EX. MVI B, 3EH - Move the data 3EH given in the
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instruction to B register;
 LXI SP, 2700H.
5. DIRECT ADDRESSING:
In direct addressing mode, the address of the data is specified in the
instruction. The data will be in memory. In this addressing mode, the program
instructions and data can be stored in different memory.
 EX. LDA 1050H - Load the data available in memory
location 1050H in to accumulator;
SHLD 3000H
6. REGISTER ADDRESSING:
In register addressing mode, the instruction specifies the name of the
register in which the data is available.
 EX. MOV A, B - Move the content of B register to A
register;
SPHL; ADD C.
7. REGISTER INDIRECT ADDRESSING:
In register indirect addressing mode, the instruction specifies the
name of the register in which the address of the data is available. Here the
data will be in memory and the address will be in the register pair.
 EX. MOV A, M - The memory data addressed by H L
pair is moved to A register.
LDAX B.
8. IMPLIED ADDRESSING:
In implied addressing mode, the instruction itself specifies the data to
be operated.
 EX. CMA - Complement the content of accumulator;
RAL
4 Explain the various instruction set of 8085? 12 1 K2
The 8085 instruction set can be classified into the following five 6
functional headings.
1. DATA TRANSFER INSTRUCTIONS:
It includes the instructions that move (copies) data between registers
or between memory locations and registers. In all data transfer operations the
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PART – B (12 Mark Questions with Key)

content of source register is not altered. Hence the data transfer is copying
operation.
Ex: (1) Mov A, B (2) MVI C, 45H
2. ARITHMETIC INSTRUCTIONS:
Includes the instructions, which performs the addition, subtraction,
increment or decrement operations. The flag conditions are altered after
execution of an instruction in this group.
Ex: (1) ADD A, B (2) SUI B, 05H
3. LOGICAL INSTRUCTIONS:
The instructions which performs the logical operations like AND, OR,
EXCLUSIVE- OR, complement, compare and rotate instructions are grouped
under this heading. The flag conditions are altered after execution of an
instruction in this group.
Ex: (1) ORA A (2) ANI B, 01H
4. BRANCHING INSTRUCTIONS:
The instructions that are used to transfer the program control from
one memory location to
another memory location are grouped under this heading.
Ex: (1) CALL (2) JMP 4100
5. MACHINE CONTROL INSTRUCTIONS:
It includes the instructions related to interrupts and the instruction used to
stop the program execution.
Ex: (1) NOP (2) END

DATA TRANSFER GROUP:

Explanation of
Opcode Operand Description
Instruction
This instruction copies the contents of the
Rd, Rs source register into the destination register;
the contents of the source register are not
Copy from
altered. If one of the operands is a memory
MOV M, Rs source(Rs) to
location, its location is specified by the
destination(Rd)
contents of the HL registers.
Rd, M
Example: MOV B, C or MOV B, M
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PART – B (12 Mark Questions with Key)

The 8-bit data is stored in the destination
register or memory. If the operand is a
Rd, data
Move immediate 8- memory location, its location is specified
MVI
bit by the contents of the HL registers.
M, data
Example: MVI B, 57H or MVI M, 57H
The contents of a memory location,
specified by a 16-bit address in the
operand, are copied to the accumulator.
LDA 16-bit address Load accumulator
The contents of the source are not altered.

Example: LDA 2034H

The contents of the designated register pair
point to a memory location. This
instruction copies the contents of that
Load accumulator memory location into the accumulator. The
LDAX B/D Reg. pair
indirect contents of either the register pair or the
memory location are not altered.

Example: LDAX B
The instruction loads 16-bit data in the
Load register pair register pair designated in the operand.
LXI Reg. pair, 16-bit data
immediate
Example: LXI H, 2034H or LXI H, XYZ
The instruction copies the contents of the
memory location pointed out by the 16-bit
address into register L and copies the
Load H and L contents of the next memory location into
LHLD 16-bit address
registers direct register H. The contents of source memory
locations are not altered.

Example: LHLD 2040H

The contents of the accumulator are copied
into the memory location specified by the
operand. This is a 3-byte instruction, the
second byte specifies the low-order address
STA 16-bit address 16-bit address
and the third byte specifies the high-order
address.

Example: STA 4350H

The contents of the accumulator are copied
into the memory location specified by the
Store accumulator contents of the operand (register pair). The
STAX Reg. pair
indirect contents of the accumulator are not altered.

Example: STAX B
SHLD 16-bit address Store H and L The contents of register L are stored into
registers direct the memory location specified by the 16-
bit address in the operand and the contents
of H register are stored into the next
memory location by incrementing the
operand. The contents of registers HL are
not altered. This is a 3-byte instruction, the
second byte specifies the low-order address
and the third byte specifies the high-order
address.
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PART – B (12 Mark Questions with Key)

Example: SHLD 2470H
The contents of register H are exchanged
with the contents of register D, and the
Exchange H and L contents of register L are exchanged with
XCHG none
with D and E the contents of register E.

Example: XCHG
The instruction loads the contents of the H
and L registers into
the stack pointer register, the contents of
the H register provide the high-order
Copy H and L
address and the contents of the L register
SPHL none registers to the stack
provide the low-order address. The
pointer
contents of the H
and L registers are not altered.

Example: SPHL
The contents of the L register are
exchanged with the stack location pointed
out by the contents of the stack pointer
register. The contents of the H register are
Exchange H and L
XTHL none exchanged with the next stack location
with top of stack
(SP+1); however, the contents of the stack
pointer register are not altered.

Example: XTHL
The contents of the register pair designated in the
operand are copied onto the stack in the following
sequence. The stack pointer register is decremented
and the contents of the highorder register (B, D, H,
Push register pair A) are copied into that location. The stack pointer
PUSH Reg. pair
onto stack register is decremented again and the contents of
the low-order register (C, E, L, flags) are copied to
that location.

Example: PUSH B or PUSH A

The contents of the memory location
pointed out by the stack pointer register are
copied to the low-order register (C, E, L,
status flags) of the operand. The stack
pointer is incremented by 1 and the
Pop off stack to
POP Reg. pair contents of that memory location are
register pair
copied to the high-order register (B, D, H,
A) of the operand. The stack pointer
register is again incremented by 1.

Example: POP H or POP A

The contents of the accumulator are
Output data from
copied into the I/O port specified by the
accumulator to a
OUT 8-bit port address operand.
port with 8-bit
address
Example: OUT F8H
The contents of the input port designated in
Input data to
the operand are read and loaded into the
accumulator from a
IN 8-bit port address accumulator.
port with 8-bit
address
Example: IN 8CH
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PART – B (12 Mark Questions with Key)

ARITHMETIC INSTRUCTIONS

Explanation of
Operand Description
Opcode Instruction
The contents of the operand
(register or memory) are
added to the contents of the
accumulator and the result
is stored in the accumulator.
If the operand is a memory
R Add register or
location, its location is
ADD memory, to
specified by the contents of
M accumulator
the HL registers. All flags
are modified to reflect the
result of the addition.

Example: ADD B or ADD

M
The contents of the operand
(register or memory) and M
the Carry flag are added to
the contents of the
accumulator and the result
is stored in the accumulator.
R If the operand is a memory
Add register to
ADC location, its location is
accumulator with carry
M specified by the contents of
the HL registers. All flags
are modified to reflect the
result of the addition.

Example: ADC B or ADC

M
The 8-bit data (operand) is
added to the contents of the
accumulator and the result
is stored in the accumulator.
Add immediate to
ADI 8-bit data All flags are modified to
accumulator
reflect the result of the
addition.

Example: ADI 45H

The 8-bit data (operand)
and the Carry flag are
added to the contents of the
accumulator and the result
Add immediate to is stored in the accumulator.
ACI 8-bit data
accumulator with carry All flags are modified to
reflect the result of the
addition.

Example: ACI 45H

LXI Reg. pair, 16-bit data Load register pair The instruction loads 16-bit
immediate data in the register pair
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designated in the operand.

Example: LXI H, 2034H

or LXI H, XYZ
The 16-bit contents of the
specified register pair are
added to the contents of the
HL register and the sum is
stored in the HL register.
Add register pair to H The contents of the source
DAD Reg. pair
and L registers register pair are not altered.
If the result is larger than
16 bits, the CY flag is set.
No other flags are affected.

Example: DAD H
The contents of the operand
(register or memory ) are
subtracted from the
contents of the
accumulator, and the result
is stored in the accumulator.
R Subtract register or If the operand is a memory
SUB memory from location, its location is
M accumulator specified by the contents of
the HL registers. All flags
are modified to reflect the
result of the subtraction.

Example: SUB B or SUB

M
The contents of the operand
(register or memory ) and
M the Borrow flag are
subtracted from the
contents of the accumulator
and the result is placed in
the accumulator. If the
R Subtract source and
operand is a memory
SBB borrow from
location, its location is
M accumulator
specified by the contents of
the HL registers. All flags
are modified to reflect the
result of the subtraction.

Example: SBB B or SBB

M
The 8-bit data (operand) is
subtracted from the
contents of the accumulator
and the result is stored in
Subtract immediate
SUI 8-bit data the accumulator. All flags
from accumulator
are modified to reflect the
result of the subtraction.

Example: SUI 45H

SBI 8-bit data Subtract immediate The contents of register H
from accumulator with are exchanged with the
borrow contents of register D, and
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the contents of register L

are exchanged with the
contents of register E.

Example: XCHG
The contents of the
designated register or
memory) are incremented
by 1 and the result is stored
in the same place. If the
R
Increment register or operand is a memory
INR
memory by 1 location, its location is
M
specified by the contents of
the HL registers.

Example: INR B or INR

M
The contents of the
designated register pair are
incremented by 1 and the
Increment register pair
INX R result is stored in the same
by 1
place.

Example: INX H
The contents of the
designated register or
memory are M decremented
by 1 and the result is stored
in the same place. If the
R
Decrement register or operand is a memory
DCR
memory by 1 location, its location is
M
specified by the contents of
the HL registers.

Example: DCR B or DCR

M
The contents of the
designated register pair are
decremented by 1 and the
Decrement register
DCX R result is stored in the same
pair by 1
place.

Example: DCX H
DAA none Decimal adjust The contents of the
accumulator accumulator are changed
from a binary value to two
4-bit binary coded decimal
(BCD) digits. This is the
only instruction that uses
the auxiliary flag to
perform the binary to BCD
conversion, and the
conversion procedure is
described below. S, Z, AC,
P, CY flags are altered to
reflect the results of the
operation.

If the value of the low-order

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4-bits in the accumulator is

greater than 9 or if AC flag
is set, the instruction adds 6
to the low-order four bits.

If the value of the high-

order 4-bits in the
accumulator is greater than
9 or if the Carry flag is set,
the instruction adds 6 to the
high-order four bits.

Example: DAA

BRANCHING INSTRUCTIONS

Explanation of
Opcode Operand Description
Instruction
The program sequence
is transferred to the
memory location
specified by the 16-bit
16-bit Jump
JMP address given in the
address unconditionally
operand.

Example: JMP
2034H or JMP XYZ

Opcode Description Flag Status The program sequence

JC Jump on Carry CY = 1 is transferred to the
memory location
JNC Jump on no Carry CY = 0 specified by the 16-bit
JP Jump on positive S=0 address given in the
16-bit Jump operand based on the
JM Jump on minus S=1
address conditionally specified flag of the
JZ Jump on zero Z=1 PSW as described
below.
JNZ Jump on no zero Z=0
JPE Jump on parity even P=1 Example: JZ 2034H
JPO Jump on parity odd P=0 or JZ XYZ

Opcode Description Flag Status 16-bit Unconditional The program sequence

address subroutine call is transferred to the
CC Call on Carry CY = 1 memory location
CNC Call on no Carry CY = 0 specified by the 16-bit
address given in the
CP Call on positive S=0 operand. Before the
CM Call on minus S=1 transfer, the address of
the next instruction
CZ Call on zero Z=1 after CALL (the
CNZ Call on no zero Z=0 contents of the program
counter) is pushed onto
CPE Call on parity even P=1 the stack.
CPO Call on parity odd P=0
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Example: CALL
2034H or CALL XYZ
The program sequence
is transferred from the
subroutine to the
calling program. The
two bytes from the top
Return from
of the stack are copied
RET none subroutine
into the program
unconditionally
counter, and program
execution begins at the
new address.

Example: RET
The program sequence
Opcode Description Flag Status is transferred from the
subroutine to the
RC Return on Carry CY = 1 calling program based
RNC Return on no Carry CY = 0 on the specified flag of
the PSW as described
RP Return on positive S=0
Return from below. The two bytes
RM Return on minus S=1 none subroutine from the top of the
conditionally stack are copied into
RZ Return on zero Z=1
the program counter,
RNZ Return on no zero Z=0 and program execution
RPE Return on parity even P=1 begins at the new
address.
RPO Return on parity odd P=0
Example: RZ
The contents of
registers H and L are
copied into the
program counter. The
Load program contents of H are
PCHL none counter with HL placed as the high-
contents order byte and the
contents of L as the
low-order byte.

Example: PCHL
RST 0-7 Restart The RST instruction is
equivalent to a 1-byte
call instruction to one
of eight memory
locations depending
upon the number. The
instructions are
generally used in
conjunction with
interrupts and inserted
using external
hardware. However
these can be used as
software instructions in
a program to transfer
program execution to
one of the eight
locations. The
addresses are:
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Restart
Instruction
Address
RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H

The 8085 has four

additional interrupts
and these interrupts
generate RST
instructions internally
and thus do not require
any external hardware.
These instructions and
their Restart addresses
are:

Restart
Interrupt
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

LOGICAL INSTRUCTIONS

Explanation of
Opcode Operand Description
Instruction
The contents of the operand (register or memory) are
M compared with the contents of the accumulator.
Both contents are preserved . The result of the
comparison is shown by setting the flags of the PSW
R Compare register as follows:
CMP or memory with
M accumulator if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset

Example: CMP B or CMP M

CPI 8-bit data Compare The second byte (8-bit data) is compared with the
immediate with contents of the accumulator. The values being
accumulator compared remain unchanged. The result of the
comparison is shown by setting the flags of the PSW
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as follows:

if (A) < data: carry flag is set

if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset

Example: CPI 89H

The contents of the accumulator are logically
ANDed with M the contents of the operand (register
or memory), and the result is placed in the
Logical AND
R accumulator. If the operand is a memory location, its
register or
ANA address is specified by the contents of HL registers.
memory with
M S, Z, P are modified to reflect the result of the
accumulator
operation. CY is reset. AC is set.

Example: ANA B or ANA M

The contents of the accumulator are logically
ANDed with the
8-bit data (operand) and the result is placed in the
Logical AND
accumulator. S, Z, P are modified to reflect the result
ANI 8-bit data immediate with
of the
accumulator
operation. CY is reset. AC is set.

Example: ANI 86H

The contents of the accumulator are Exclusive ORed
with M the contents of the operand (register or
memory), and the result is placed in the accumulator.
Exclusive OR
R If the operand is a memory location, its address is
register or
XRA specified by the contents of HL registers. S, Z, P are
memory with
M modified to reflect the result of the operation. CY
accumulator
and AC are reset.

Example: XRA B or XRA M

The contents of the accumulator are Exclusive ORed
with the 8-bit data (operand) and the result is placed
Exclusive OR
in the accumulator. S, Z, P are modified to reflect the
XRI 8-bit data immediate with
result of the operation. CY and AC are reset.
accumulator
Example: XRI 86H
The contents of the accumulator are logically ORed
with M the contents of the operand (register or
memory), and the result is placed in the accumulator.
Logical OR
R If the operand is a memory location, its address is
register or
ORA specified by the contents of HL registers. S, Z, P are
memory with
M modified to reflect the result of the operation. CY
accumulator
and AC are reset.

Example: ORA B or ORA M

The contents of the accumulator are logically ORed
with the 8-bit data (operand) and the result is placed
Logical OR
in the accumulator. S, Z, P are modified to reflect the
ORI 8-bit data immediate with
result of the operation. CY and AC are reset.
accumulator
Example: ORI 86H
RLC none Rotate Each binary bit of the accumulator is rotated left by
accumulator left one position. Bit D7 is placed in the position of D0
as well as in the Carry flag. CY is modified
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according to bit D7. S, Z, P, AC are not affected.

Example: RLC
Each binary bit of the accumulator is rotated right by
one position. Bit D0 is placed in the position of D7
Rotate as well as in the Carry flag. CY is modified
RRC none
accumulator right according to bit D0. S, Z, P, AC are not affected.

Example: RRC
Each binary bit of the accumulator is rotated left by
one position through the Carry flag. Bit D7 is placed
Rotate in the Carry flag, and the Carry flag is placed in the
RAL none accumulator left least significant position D0. CY is modified
through carry according to bit D7. S, Z, P, AC are not affected.

Example: RAL
Each binary bit of the accumulator is rotated right by
one position through the Carry flag. Bit D0 is placed
Rotate in the Carry flag, and the Carry flag is placed in the
RAR none accumulator right most significant position D7. CY is modified
through carry according to bit D0. S, Z, P, AC are not affected.

Example: RAR
The contents of the accumulator are complemented.
Complement No flags are affected.
CMA none
accumulator
Example: CMA
The Carry flag is complemented. No other flags are
affected.
CMC none Complement carry
Example: CMC
Set Carry
STC none Set Carry
Example: STC

CONTROL INSTRUCTIONS
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Explanation of
Opcode Operand Description
Instruction
No operation is performed. The instruction is fetched and
NOP none No operation decoded. However no operation is executed.
Example: NOP
HLT none Halt and enter The CPU finishes executing the current instruction and
wait state halts any further execution. An interrupt or reset is
necessary to exit from the halt state.
Example: HLT
The interrupt enable flip-flop is reset and all the interrupts
except the TRAP are disabled. No flags are affected.
DI none Disable interrupts
Example: DI
The interrupt enable flip-flop is set and all interrupts are
enabled. No flags are affected. After a system reset or the
acknowledgement of an interrupt, the interrupt enable
flipflop is reset, thus disabling the interrupts. This
EI none Enable interrupts
instruction is
necessary to reenable the interrupts (except TRAP).

Example: EI
This is a multipurpose instruction used to read the status
of interrupts 7.5, 6.5, 5.5 and read serial data input bit.
The instruction loads eight bits in the accumulator with
the following interpretations.

Example: RIM

Read interrupt
RIM none
mas

This is a multipurpose instruction and used to implement

the 8085 interrupts 7.5, 6.5, 5.5, and serial data output.
The instruction interprets the accumulator contents as
follows.

Example: SIM

Set interrupt
SIM none
mask
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5 Discuss about the timing diagram of 8085 12 1 K2

Timing Diagram is a graphical representation. It represents the execution 6
time taken by each instruction in a graphical format. The execution time is
represented in T-states.

Instruction Cycle:

The time required to execute an instruction is called instruction cycle.

Machine Cycle:

The time required to access the memory or input/output devices is called

machine cycle.

T-State:

The machine cycle and instruction cycle takes multiple clock periods.

A portion of an operation carried out in one system clock period is called as

T-state.

MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 (seven) basic machine cycles. They are

 Opcode fetch cycle (4T)

 Memory read cycle (3 T)

 Memory write cycle (3 T)

 I/O read cycle (3 T)

 I/O write cycle (3 T)

Each instruction of the 8085 processor consists of one to five machine

cycles, i.e., when the 8085 processor executes an instruction, it will execute
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some of the machine cycles in a specific order.

The processor takes a definite time to execute the machine cycles. The
time taken by the processor to execute a machine cycle is expressed in T-
states. One T-state is equal to the time period of the internal clock signal of
the processor. The T-state starts at the falling edge of a clock.

Opcode fetch machine cycle of 8085 :

 Each instruction of the processor has one byte opcode.
 The opcodes are stored in memory. So, the processor executes the
opcode fetch machine cycle to fetch the opcode from memory.
 Hence, every instruction starts with opcode fetch machine cycle.
 The time taken by the processor to execute the opcode fetch cycle is
4T.
 In this time, the first, 3 T-states are used for fetching the opcode
from memory and the remaining T-states are used for internal
operations by the processor.

Memory Read Machine Cycle of 8085: 6

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 The memory read machine cycle is executed by the processor to read

a data byte from memory.
 The processor takes 3T states to execute this cycle.
 The instructions which have more than one byte word size will use
the machine cycle after the opcode fetch machine cycle.

I/O Write Cycle of 8085:

 The I/O write machine cycle is executed by the processor to write a
data byte in the I/O port or to a peripheral, which is I/O, mapped in
the system.
 The processor takes, 3T states to execute this machine cycle.
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6 DRAW AND EXPLAIN THE PINDIAGRAM OF 8085 12 2 K2

The microprocessor is a clock-driven semiconductor device
consisting of electronic logic circuits manufactured by using either a large-
scale integration (LSI) or very-large-scale integration (VLSI) technique. The
microprocessor is capable of performing various computing functions and
making decisions to change the sequence of program execution. In large
3
computers, a CPU implemented on one or more circuit boards performs these
computing functions. The microprocessor is in many ways similar to the
CPU, but includes the logic circuitry, including the control unit, on one chip.
The microprocessor can be divided into three segments for the sake clarity,
arithmetic/logic unit (ALU), register array, and control unit.

8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as
follows
1. Power supply and clock signals
2. Address bus
3. Data bus
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4. Control and status signals

5. Interrupts and externally initiated signals
6. Serial I/O ports

Pin diagram and signal diagram of 8085 2

1. Power supply and clock signals

 Vcc - + 5 volt power supply
 Vss - Ground
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 X1, X2 - Crystal or R/C network or LC network connections to

set the frequency of internal clock generator. The frequency is
internally divided by two. Since the basic operating timing
frequency is 3 MHz, a 6 MHz crystal is connected externally.
 CLK (output) - Clock Output is used as the system clock for
peripheral and devices interfaced with the microprocessor.
2. Address Bus:
 A8 - A15 - (output; 3-state)
 It carries the most significant 8 bits of the memory address or the
8 bits of the I/O address;
3. Multiplexed Address / Data Bus:
 AD0 - AD7 (input/output; 3-state)
 These multiplexed set of lines used to carry the lower order 8 bit
address as well as data bus.
 During the opcode fetch operation, in the first clock cycle, the
lines deliver the lower order address A0 - A7.
 In the subsequent IO / memory, read / write clock cycle the lines
are used as data bus.
 The CPU may read or write out data through these lines.
4. Control and Status signals:
 ALE (output) - Address Latch Enable.
 This signal helps to capture the lower order address presented on
the multiplexed address / data bus.
 RD (output 3-state, active low) - Read memory or IO device.
 This indicates that the selected memory location or I/O device is
to be read and that the data bus is ready for accepting data from
the memory or I/O device.
 WR (output 3-state, active low) - Write memory or IO device.
 This indicates that the data on the data bus is to be written into
the selected memory location or I/O device.
 IO/M (output) - Select memory or an IO device.
 This status signal indicates that the read / write operation relates
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to whether the memory or I/O device.

 It goes high to indicate an I/O operation. & It goes low for
memory operations.
5. Status Signals:
It is used to know the type of current operation of the
microprocessor.

6. Interrupts and Externally initiated operations:

 They are the signals initiated by an external device to request the
microprocessor to do a particular task or work.
 There are five hardware interrupts called,

 On receipt of an interrupt, the microprocessor acknowledges the

interrupt by the active low INTA (Interrupt Acknowledge) signal.
Reset In (input, active low)
 This signal is used to reset the microprocessor.
 The program counter inside the microprocessor is set to zero.
 The buses are tri-stated.
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Reset Out (Output)

 It indicates CPU is being reset.
 Used to reset all the connected devices when the microprocessor
is reset.

7. Direct Memory Access (DMA): 3

 Tri state devices:

 3 output states are high & low states and additionally a high
impedance state.
 When enable E is high the gate is enabled and the output Q can be 1
or 0 (if A is 0, Q is 1, otherwise Q is 0). However, when E is low the
gate is disabled and the output Q enters into a high impedance state.

Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram.

 For both high and low states, the output Q draws a current from the
input of the OR gate.
 When E is low, Q enters a high impedance state; high impedance
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means it is electrically isolated from the OR gate's input, though it is

physically connected. Therefore, it does not draw any current from
the OR gate's input.
 When 2 or more devices are connected to a common bus, to prevent
the devices from interfering with each other, the tristate gates are used
to disconnect all devices except the one that is communicating at a
given instant.
 The CPU controls the data transfer operation between memory and
I/O device. Direct Memory Access operation is used for large volume
data transfer between memory and an I/O device directly.
 The CPU is disabled by tri-stating its buses and the transfer is
effected directly by external control circuits.
 HOLD signal is generated by the DMA controller circuit. On receipt
of this signal, the microprocessor acknowledges the request by
sending out HLDA signal and leaves out the control of the buses.
After the HLDA signal the DMA controller starts the direct transfer
of data.
READY (input)
 Memory and I/O devices will have slower response compared to
microprocessors.
 Before completing the present job such a slow peripheral may not be
able to handle further data or control signal from CPU.
 The processor sets the READY signal after completing the present
job to access the data.
 The microprocessor enters into WAIT state while the READY pin is
disabled.
8. Single Bit Serial I/O ports:
 SID (input) - Serial input data line
 SOD (output) - Serial output data line These signals are used for
serial communication.
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PART – C (20 Mark Questions with Key)

S.N Questions Mark COs BTL
o
UNIT I – INTRODUCTION
1 Briefly explain about 8085 Architecture and its pins 20 1 K3

10

The functional block diagram or architecture of 8085 Microprocessor is

very important as it gives the complete details about a Microprocessor. Fig.1
10
shows the Block diagram of a 8085 Microprocessor ADDRESS BUS:
 The address bus is a group of 16 lines generally identified as A0
to A15.
 The address bus is unidirectional: bits flow in one direction-from
the MPU to peripheral devices.
 The MPU uses the address bus to perform the first function:
identifying a peripheral or a memory location.
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DATA BUS:
 The data bus is a group of eight lines used for data flow.
 These lines are bi-directional - data flow in both directions
between the MPU and memory and peripheral devices.
 The MPU uses the data bus to perform the second function:
transferring binary information.
 The eight data lines enable the MPU to manipulate 8-bit data
ranging from 00 to FF (28 = 256 numbers).
 The largest number that can appear on the data bus is 11111111.
CONTROL BUS:
 The control bus carries synchronization signals and providing
timing signals.
 The MPU generates specific control signals for every operation it
performs. These signals are used to identify a device type with
which the MPU wants to communicate.
REGISTERS OF 8085:
 The 8085 have six general-purpose registers to store 8-bit data
during program execution.
 These registers are identified as B, C, D, E, H, and L.
 They can be combined as register pairs-BC, DE, and HL-to
perform some 16-bit operations.
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ACCUMULATOR (A):
 The accumulator is an 8-bit register that is part of the
arithmetic/logic unit (ALU).
 This register is used to store 8-bit data and to perform arithmetic
and logical operations.
 The result of an operation is stored in the accumulator.
FLAGS REGISTER:
 The ALU includes five flip-flops that are set or reset according to
the result of an operation.
 The microprocessor uses the flags for testing the data conditions.
 They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary
Carry (AC) flags. The most commonly used flags are Sign, Zero,
and Carry.
 The bit position for the flags in flag register is,

1. Sign Flag (S):

After execution of any arithmetic and logical operation, if D7 of the result
is 1, the sig flag is set. Otherwise it is reset.
D7 is reserved for indicating the sign; the remaining is the magnitude of
number.
If D7 is 1, the number will be viewed as negative number. If D7 is 0, the
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number will be viewed as positive number.

2. Zero Flag (z):
If the result of arithmetic and logical operation is zero, then zero flag is
set otherwise it is reset.
3. Auxiliary Carry Flag (AC):
If D3 generates any carry when doing any arithmetic and logical
operation, this flag is set.
Otherwise it is reset.
4. Parity Flag (P):
If the result of arithmetic and logical operation contains even number of
1's then this flag will be set and if it is odd number of 1's it will be reset.
5. Carry Flag (CY):
If any arithmetic and logical operation result any carry then carry flag is
set otherwise it is reset.
ARITHMETIC AND LOGIC UNIT (ALU):
 It is used to perform the arithmetic operations like addition,
subtraction, multiplication, division, increment and decrement and
logical operations like AND, OR and EX-OR.
 It receives the data from accumulator and registers.
 According to the result it set or reset the flags.
PROGRAM COUNTER (PC):
 This 16-bit register sequencing the execution of instructions.
 It is a memory pointer. Memory locations have 16-bit addresses, and
that is why this is a 16-bit register.
 The function of the program counter is to point to the memory
address of the next instruction to be executed.
 When an opcode is being fetched, the program counter is incremented
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 by one to point to the next memory location.

STACK POINTER (SP):
 The stack pointer is also a 16-bit register used as a memory pointer.
 It points to a memory location in R/W memory, called the stack.
 The beginning of the stack is defined by loading a 16-bit address in
the stack pointer (register).

TIMING AND CONTROL UNIT:

 It has three control signals ALE, RD (Active low) and WR (Active
low) and three status signals IO/M(Active low), S0 and S1.
 ALE is used for provide control signal to synchronize the components
of microprocessor and timing for instruction to perform the operation.
 RD (Active low) and WR (Active low) are used to indicate whether
the operation is reading the data from memory or writing the data into
memory respectively.
 IO/M(Active low) is used to indicate whether the operation is belongs
to the memory or peripherals.

TEMPORARY REGISTER:
It is used to hold the data during the arithmetic and logical operations.
INSTRUCTION REGISTER:
When an instruction is fetched from the memory, it is loaded in the
instruction register.
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2 Write Programs to sort out given numbers in ascending and descending 20 1 K3

order in ‘n’ numbers
To write a program to sort given ‘n’ numbers in ascending order
Algorithm:
Step 1 : Start the microprocessor
Step 2 : Accumulator is loaded with number of
values to sorted and it is saved
Step 3 : Decrement 8
register (N-1) Repetitions) 10
Step 4 : Set ‘HL’
register pair as data array
Step 5 : Set ‘C’ register as counter for (N-1)
repetitions
Step 6 : Load a data of the array in accumulator
Step 7 : Compare the data pointed in ‘HL’ pair
Step 8 : If the value of accumulator is smaller
than memory, then jump to step 10.
Step 9 : Otherwise exchange the contents of
‘HL’ pair and accumulator
Step 10 : Decrement ‘C’ register, if the of ‘C’ is
not zero go to step 6
Step 11 : Decrement ‘B’ register, if value of ‘B’ is
not zero, go step 3
Step 12 : Stop the program execution
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Mnemonics :

LDA 4500
MOV B,A
DCR B
LXI H, 4500
MOV C,M
DCR C
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INX H
MOV A,M
INX H
CMP M
JC
MOV D,M
MOV M,A
DCX H
MOV M,D
INX H
DCR C
JNZ Loop 1
DCR B
JNZ Loop 2
HLT
To write a program to sort given ‘n’ numbers in descending order 10
Algorithm:
Step 1 : Start the microprocessor
Step 2 : Load the number of values into
accumulator and save the
number of values in register ‘B’
Step 3 : Decrement register ‘B’ for (N-1)
Repetitions
Step 4 : Set ‘HL’ register pair as data array
address pointer and load the data of
array in accumulator
Step 5 : Set ‘C’ register as counter for (N-1)
repetitions
Step 6 : Increment ‘HL’ pair (data address
pointer)
Step 7 : Compare the data pointed by ‘HL’ with
accumulator
Step 8 : If the value of accumulator is larger
than memory, then jump to step 10,
otherwise next step.
Step 9 : Exchange the contents of memory
pointed by ‘HL’ and
accumulator
Step 10 : Decrement ‘C’ register, if the of ‘C’
is not zero go to step 6, otherwise
next step.
Step 11 : Decrement ‘B’ register, if ‘B’ is not
zero, go step 3, otherwise
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next step.
Step 12 : Stop the program execution

Mnemonics:

LDA 4500
MOV B,A
DCR B
LXI H, 4500
MOV C,M
DCR C
 E.G.S. PILLAY ENGINEERING COLLEGE Rev.0
(An Autonomous Institution, Affiliated to Anna University, Chennai)
COE/2018/QB
Nagore Post, Nagapattinam – 611 002, Tamilnadu.

INX H
MOV A,M
INX H
CMP M
ICE, Loop 1
MOV D,M
MOV M,A
DCX H
MOV M,D
INX H
DCR C
JNZ Loop 2
DCR B
JNZ Loop 3
HLT