PERIPHERAL INTERFACING

Unit No 2
INTRODUCTION
• Interfacing of the one or more peripheral devices for the purpose of
communication with various input and output devices connected to
it.

• Early days of the microprocessor revolution, these techniques

required complex hardware consisting of Medium scale integration
devices making the design highly complex and time consuming.
INTRODUCTION
• INTEL have developed a large number of general and special purpose
peripheral devices most of them being single chip circuits.

• They are also programmable devices.

• Hence these peripheral devices are found to be of tremendous use to

a system designer.
• Peripheral devices can broadly be classified into two categories.

• (a) General purpose peripherals and

• (b) Special purpose peripherals (Dedicated function peripherals)

General purpose peripheral devices
• Devices that perform a task but may be used for interfacing a variety
of I/O devices to microprocessor.
• The general purpose devices are given below:
• Simple I/O- Non Programable
• Programmable peripheral Interface (PPI) - (8255)
• Programmable Interrupt Controller- (8259)
• Programmable DMA Controller - (8237/8257)
• Programmable Communication Interface - (8251)
• Programmable Interval Timer - (8253/8254)
Special function peripherals
• Devices that may be used for interfacing a microprocessor to a
specific type of I/O device.

• These peripherals are more complex and therefore, relatively more

expensive than general purpose peripherals.

• The special function peripherals (Dedicated function peripherals) are

Special function peripherals
• Programmable CRT Controller
• Programmable Floppy Disc Controller
• Programmable Hard Disc Controller
• Programmable Keyboard and display interface.

• The functioning of these devices varies depending on the type of I/O

device they are controlling.
8255 - PROGRAMMABLE PERIPHERAL
INTERFACING(8255 - PPI)
• For most of the applications 8086 needs parallel input ,output data
to/from the peripherals.
• 8255 is a widely used, low cost, programmable, parallel I/O device.
• It can be programmed to transfer data under various conditions from
simple I/O to interrupt I/O.
• INTEL introduced this programmable peripheral interface (PPI) chip
8255A for interfacing peripheral devices to the 8085/8086 system.
8255 - PROGRAMMABLE PERIPHERAL
INTERFACING(8255 - PPI)
• 8255A is used as a general purpose peripheral device for parallel data
transfer between microprocessor and a peripheral device by interfacing the
device to the system data bus.

• The PPI has three programmable parallel I/O ports viz., Port A, Port B and
Port C each of 8 bit width in one package.

• Port C can be treated as two ports –

• Port C upper (PC7-4) and
• Port lower (PC3 – 0).
• These two can be independently programmed as INPUT or OUTPUT ports
also.
Pin Diagram of 8255
Selection of Ports
Salient Features
• i. It is a general purpose programmable I/O device which is
compatible with all INTEL processors and also most other processors.
• ii. It provides 24 I/O pins which may be individually programmed in
two groups or groups of 8/12 pins.
• iii. This chip is also completely TTL compatible.
• Iv . It is available in 40 pin DIP and 44 pin plastic leaded chip carrier
(PLCC) packages.
• v. It has three 8 bit ports. Port A, Port B and Port C. Port C is treated
as two 4 bit ports also.
Salient Features
• vi. This 8255 is mainly programmed in two modes (a) the I/O mode
and (b) The bit set/reset mode (BSR) mode.

• The I/O mode is further divided into three modes:

• Mode 0, Mode 1, and Mode 2.

• vii. An 8 bit control resister is used to configure the modes of 8255.

Control Word Format
Control Word Format
Example
Problem-1
• Write a control word to configure port A as input port in mode 0 and
port B in mode 1 as output port for 8255A.
Solution
Problem-2
• A control word is given CDH. Explain the conditions of ports of 8255A.
Solution
Interfacing with 8086
PIN CONFIGURATION OF 8255
• D0-D7 (Data Bus): Bidirectional, tri-state, data bus lines connected to
the system data bus. They are used to transfer data and control word
from microprocessor to 8255 or receive data or status word from
8255 to 8085.
• PA0-PA7(Port A): These 8-bit bidirectional I/O pins are used to send
or receive data from O/P or I/P device.

• PB0-PB7(Port B): These 8-bitbidirectional I/O pins are used to send or

receive data from O/P or I/P device.
PIN CONFIGURATION OF 8255
• PC0- PC7(port C): These 8-bit bidirectional I/O pins are divided into two groups
PCL (PC0- PC3)and PCU (PC4- PC7). These groups can individually transfer data in
or out when programmed I/O. When programmed in bidirectional or handshake
modes these bits are used as handshake signals.
• RD’ (Read): MPU or CPU reads data in the ports or the status word through data
buffer.
• WR’ (Write): MPU or CPU writes data in the ports or the control register through
data Buffer.
• CS’ (Chip Select): It is an active low input which can be used to enable 8255 for
data transfer operation between CPU (MPU) and 8255.
• RESET: It is an active high input used to reset 8255. When reset input is high, the
control register is cleared and all the ports are set to the input mode.
• A0&A1: These input signals along with RD’, WR’ inputs control the selection of
control / status word registers or one of three ports.
Description
• Data Bus buffer : Tri-state bidirectional buffer is used to interface the
internal data bus of 8255 to the system data bus. Output data from the
MPU to the ports or control register and the input data to the MPU from
the ports or status register are all pushed through the buffer.
• Control Logic : This block accepts control bus signals as well as inputs from
the address bus and issues commands to the individual group control
blocks (Group A Control and Group B Control)as shown in Fig.2.
• Group A Control and Group B Control : Group A control block controls Port
A and PC7-PC4. Group B controls block controls Port B and PC3- PC0.
Description
• Port A: This has 8-bit latched and buffered output and an 8-bit input
latch. It can be programmed in three modes: Mode 0: Simple I/O
mode, Mode 1: I/O with Handshaking mode, Mode 2: Bidirectional
data transfer mode.
• Port B: This has 8-bit I/O latch/buffer and an 8-bit data input buffer.
It can be programmed in mode 0 or mode 1.
• Port C: This has 8-bit unlatched input buffer and an 8-bit output
latch/buffer. Port C can be splitted into two parts and each bit can be
used as control signals for Port A and Port B in handshake mode. It
can be programmed for BSR (Bit Set / Reset mode) operation.
Modes of Operation
• 1. BSR mode
• 2. I/O mode : Further divided into Mode 0, Mode 1 and Mode 2.

• Mode 0: Simple I/O mode

• Mode 1 : I/O with Handshaking mode

• Mode 2: Bidirectional data transfer mode

BSR (Bit Set/Reset) Mode
• Individual bits of Port C can be set or reset by sending out a single
OUT instruction to the control register.

• When Port C is used for control/status operation, this feature of BSR

Mode can be used to set or reset individual bits. For BSR mode
control word is given below.
Example
Bit Set / Reset (BSR) Mode
BSR (Bit Set/Reset) Mode
• A BSR word is to be written for each bit that is to be set or reset.

• The BSR word can also be used for enabling or disabling the interrupt
signals generated by Port c when 8255 is programmed for mode 1 or
mode 2 operation.
Control Word for I/O mode
Mode 0 : Basic Input/output
• This mode provides simple input and output operations for each of the
three ports. Data is simply written to or read from a specified port.
• Basic functional definition
• In mode 0:
• There are two 8-bit ports (A and B) and two 4-bit ports [C (lower)] and [C
(upper)].
• Any port can be an input port or an output port.
• Outputs are latched.
• Inputs are not latched.
• 16 different input/output configurations are possible in this mode.
Mode1: Strobed Input/Output
• It provides means for transferring I/O data to or from a specified port
in conjunction with strobes or hand-shaking signals.

• Port A and port B use the lines on port C for handshaking signals.
Basic functional definition
• In mode1:
• There are two groups (Group A and B).
• Each group contains one 8-bit data port and one 4-bit control data
port.
• The 8-bit data port can be either an input port or an output port.
Both inputs and outputs are latched.
• The 4-bit port is used for control as well as for status of the 8-bit data
port.
Mode2 : Strobed Bidirectional Bus
• This functional configuration provides a means for communicating
with a peripheral device or Structure on a single 8-bit bus for both
transmitting and receiving data. Handshaking signals are provided to
maintain a proper bus flow discipline.

• Interrupt generation and enable/disable functions are also available.

Basic functional definition
• In mode 2 (used in Group A only):

• There is one 8-bit bidirectional bus port (port A) and a 5-bit control
port (port C).

• Both inputs and outputs are latched.

• The 5-bit control port (port C) is used for control as well as for status
of the 8-bit bidirectional bus port (port A).