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Lecture 2 MIPS Architecture

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Lecture 2 MIPS Architecture

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Jothika
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22AIE113

Elements of Computing Systems-II


MIPS Architecture

Ms. Sreelakshmi K, Assistant Professor


Center for Computational Engineering and Networking (CEN)
Amrita School of Engineering, Coimbatore

Acknowledgment: Prof. Noam Nisan, Prof. Shimon Schocken

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 1


Basic Computer Architecture
● Set of rules and methods used to describe the functionality, organization and
implementation of a computer system.

● Let’s start building a Computer

– In order to build a computer we need a model

– One such model is Von Neumann Model

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 2


Von Neumann Model
● John Von Neumann Proposed a fundamental model in 1946

● Consists of 5 parts
– Memory
– Processing Unit
– Input
– Output
– Control Unit
● Examples: LC-3, MIPS
– Microprocessor without Interlocked Pipeline stages Burks AW, Goldstine HH, Von Neumann J. Preliminary discussion of the
logical design of an electronic computing instrument.

22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 3


Von Neumann Model

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 4


Memory
● Data memory and Program memory

● MIPS memory consists of an array of bytes


– Each byte is accessed using unique address
• MIPS is byte addressable
– Each byte can hold 8 bit patterns
– 8 bits from a byte

● There are 2 ways of accessing memory:


– Read/load
– Write/store

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 5


Von Neumann Model

22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 6


Processing Unit
● The processing unit consists of many functional units

● Lets start with the simple one - ALU


– Arithmetic and Logic unit
– MIPS – add, sub, mult, and, nor, sll, srl, …………

● Registers – Temporary storage


– 32 register each of size 32 bit
– Each 4 bytes constitute a word
– So the word size of MIPS architecture is 4 bytes or 32 bits
– Each register has a unique address
– Since there are 32 registers the register address is 5 bit
• Eg: 10111 means register number 23
– Among the 32 registers R0 always hold value 0.

22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 7


Von Neumann Model

22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 8


Inputs and Outputs
● Input and output devices are also called peripherals
● Input devices
– Keyboard
– Mouse
– Scanner
– Disks etc.,
● Output devices
– Monitor
– Printer etc.,

22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 9


Von Neumann Model

22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 10


Control Unit
● It conducts the step by step process of execution of every instruction in a program

● It keeps track of the instructions being executed with an Instruction register (IR),
which contains the instructions.

● Another register contains the address of the next instruction to execute. It is called
the program counter (PC) or Instruction pointer (IP)

22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 11


MIPS Registers
• MIPS has a total of 32 general
purpose registers
• Each register holds 32 bits of data

22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 12


MIPS Instruction Types

● R Instructions – Computational (Arithmetic, logical, shift)


● I Instructions - Load/Store
● J Instructions – Jump and Branch

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 13


● R Instructions
R Type Instruction
– These type of instructions are used when all the data values are located in registers
– All R-type instructions have the format:
– Opcode (6 bit) : The opcode is the machine code representation of the instruction mnemonic. For R-type
instruction it is always 0
– rs, rt, rd (5 bit) : The numeric representations of the source registers and the destination register
• Rd-destination and rs and rt source
– shamt (5 bit) : Shift Used with the shift and rotate instructions, this is the amount by which the source
operand rs is rotated/shifted.
– Funct (6bit) : function code identifies the specific R-format instruction

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 14


R Type Instruction
● Add, sub are signed instructions
● Addu, subu are unsigned instructions
● Unsigned instructions do not generate overflow exceptions

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 15


I Type Instruction
● These instructions have 2 registers and a constant value immediately present in the instruction.

● All I type instructions have the format :


– rs- source and rt- target

● Each operation has unique opcode

rt - t2
rs - s3

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 16


I Type Instructions

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 17


J Type Instruction
● J instructions are used when a jump needs to be performed.
● The J instruction has the most space for an immediate value, because addresses are
large numbers.
● J instructions are called in the following way: OP LABEL
– Where OP is the mnemonic for the particular jump instruction, and LABEL is the target address to jump to.
– Example: J target

dropping the high-order 4 bits of the address and the low-order 2 bits

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 18


Problem 1

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 19


Problem 2

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 20


Branches

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 21


Tests, Jumps

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 22


Problem 3

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 23


Problem 4

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 24


For Loop

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 25


Problem 5
li s0,0
li t0,0

For loop:

slti t1,t0,10 (if t0<10 t1=1 else t1=0)


beq t1,0, stoploop
add s0,s0,t0
addi t0,t0,1
j For loop
slti – set on less than immediate
beq – branch on equal stoploop:

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 26


Thank You

30 January 2024 22AIE113|EOC-2|B.TECH CSE (AI)|CEN|Ms. Sreelakshmi 27

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