Registers

• MIPS has 32 general purpose registers and

32 floating point registers
• Each register is 32 bits wide
• MIPS is a 32-bit architecture
• All instructions and addresses are 32-bits
long – 4GB RAM limit
• Most modern architectures are 64-bit
• E.g. x86-64/AMD64, ARM64
• They have 64-bit words
• Newer MIPS has been developed to 64
bits
17
MIPS Registers
Number Name Comments

$0 $zero, $r0 Built into the hardware to ALWAYS be 0

$1 $at Reserved for assembler

$2, $3 $v0, $v1 First and second return values, respectively. Used for syscalls

$4, ..., $7 $a0, ..., $a3 First four arguments to functions. Often used with syscalls
$8, ..., $15 $t0, ..., $t7 Temporary registers

$16, ..., $23 $s0, ..., $s7 Saved registers

$24, $25 $t8, $t9 More temporary registers

$26, $27 $k0, $k1 Reserved for kernel (operating system)
$28 $gp Global pointer

$29 $sp Stack pointer

$30 $fp Frame pointer

$31 $ra Return address
$f0, …, $f31 Single precision floating point registers

18
Memory
• Operations only performed on registers;
need to move values to registers before use

Load word Register Memory

lw $t0, address

Store word
Register Memory
sw $t0, address

19
Memory Address
• A 1D array
• Compiler keeps a look-up table
• Maps each variable in the array

20
Words & Bytes

• Memory addressing is at a byte level

• Consecutive addresses are a byte apart
• Addresses of consecutive words will be
4 bytes apart

21
Byte Order

• Words use 32 bits (4 bytes)

• Little endian – the least significant
digits are stored in the lower addresses
• Big endian – the most significant digits
are store in the lower addresses

22
 Little endian Big endian

Byte Order Address Value Address Value

20 20

Number in $t0
19 19
18 18

0x65676361 17
16
17
16
15 65 15 61
Address in $s0 14 67 14 63

12 13
12
63
61
13
12
67
65
11 11
10 10
9 9
8 8
7 7
6 6
Instruction 5 5
sw $t0, 0($s0) 4 4
3 3
2 2
1 1
0 0

23
Memory
Memory loading and storing format

Load word
lw $t0, 4($t3)

Destination Offset Source

Store word
sw $t0, -4($t3)

24
Stack
• Need to free registers for use, but
retain their values
• Push values from registers onto the
stack
• Pop values from the stack to retrieve
them
• Stack grows from top-down
• Stack pointer: $sp

25
Stack Address
20
Value

19
18
Push 2 words. $sp is initially at 12: 17
1. addi $sp, $sp, -8 16
2. sw $t0, 4($sp) 15
3. sw $t1, 0($sp) 14
13
Initial $sp 12
11
10
1. Decrement $sp by 8 bytes
9
2. Store $t0 at address $sp+4
8
3. Store $t1 at address $sp
7
6
5
Final $sp 4
3
2
1
0
26
Stack Address
20
Value

19
18
Pop 2 words. $sp is initially at 4: 17
lw $t3, 0($sp) 16
lw $t4, 4($sp) 15
addi $sp, $sp, 8 14
13
Final $sp 12
11
10
1. Load value from address $sp into $t3
9
2. Load value from address $sp+4 into $t4
8
3. Increment $sp by 8 bytes
7
6
5
Initial $sp 4
3
2
1
0
27
Data Transfer Instructions
Instruction E.g. Meaning Comments

Load word lw $1,100($2) $1=Memory[$2+100] Copy from memory to register

Store word sw $1,100($2) Memory[$2+100]=$1 Copy from register to memory

Load upper lui $1,100 $1=100x2^16 Load constant into upper 16 bits. Lower
16 bits are set to zero.
immediate
Load address la $1,label $1=Address of label Pseudo-instruction (provided by
assembler, not processor) Loads
computed address of label (not its
contents) into register

Load immediate li $1,100 $1=100 Pseudo-instruction (provided by

assembler, not processor) Loads
immediate value into register

Move from hi mfhi $2 $2=hi Copy from special register hi to general

register

Move from lo mflo $2 $2=lo Copy from special register lo to general

register

Move move $1,$2 $1=$2 Pseudo-instruction (provided by

assembler, not processor) Copy from
register to register

28