Instruction format of 8086

• The machine code/language of instructions has one or more

number of fields.
• The first field is called Operation code field or Opcode field
which indicates the type of operation to be performed by the
processor/CPU.
• The other fields of the instruction are known as operand fields
• The length of the instruction may vary from one to six bytes.
 One-byte Instructions
• This instructions is only one byte long.
• It may have implied data or register as operands
• Least significant 3 bits of the code is used to specify the register operand,
if any. Otherwise, all the 8 bits form an opcode and operands are implied.

Example: Format 1:
Implied Addressing Mode –
CLC, CLD, STC, CMC, CBW, DAA, DAS, AAA, AAS, RET, CLI, HLT
REP, REPZ, REPE, REPNE/REPNZ, LOCK, LODS/LODSB/LODSW
One-byte Instructions (Contd…)
Format 2:
Register Addressing Mode
INC Reg (16 bit) Opcode Reg
DEC Reg (16 Bit) 11111 Reg (3 Bits)
INC BX
DEC CX

NB: INC /DEC for 8-bit Register is 2-byte instruction.

 Common Instruction format of 8086

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPCODE D W MOD REG R/M

6 bit 1 1 2 bit 3 bits 3 bits
bit bit

1st Byte 2nd Byte

Codes of different registers for the REG field in Byte2

OPCODE D W MOD REG R/M

OPCODE D W MOD REG R/M
Codes for the MOD field corresponding to different addressing
modes are as follows

CODE EXPLANATION

00 Memory Mode, no displacement follows

01 Memory Mode, 8-bit displacement follows

10 Memory Mode, 16-bit displacement follows

11 Register Mode (no displacement)

Addressing modes and corresponding codes with effective address
 Two Byte Instructions
These Instructions use two operands. There are two formats for such
instructions.

Format 1: Register to Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPCODE D W MOD REG R/M

6 bit 1 1 2 bit 3 bits 3 bits
bit bit 11

1st Byte 2nd Byte

 Two Byte Instructions

Format 2: Register to / from memory with no displacement

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPCODE D W MOD REG R/M

6 bit 1 1 2 bit 3 bits 3 bits
bit bit 00

1st Byte 2nd Byte

Three Byte Instructions
2. Immediate Operand (8-bits Data) to Register

1 Byte
Displacement
Three Byte Instructions
• There are two formats for these types of Instructions
• 1. Immediate operand to Register.
 Generate code for the following Instructions
OPCODE D W MOD REG R/M
1. SUB BX, [DI]
The 6 bit opcode of SUB is 001010
2. MOV 1234 (BP), DX
BX is destination register. Therefore, D is 1.
3. ADD OFABE [BX][DI], DX
W should be 1 to represent 16 bit data operation
4. MOV AX, [BX]
Mod → 00
REG →011
R/M → 101
OPCODE D W MOD REG R/M
Therefore, machine code is 001010 1 1 00 011 101

2B1D
 Generate code for the following Instructions
OPCODE D W MOD REG R/M
2. MOV 1234 (BP), DX The 6 bit opcode of MOV is 100010
DX is source register. Therefore, D is 0.
W should be 1 to represent 16 bit data operation
Mod → 10 ; REG →010; R/M → 110
Therefore, machine code is
OPCODE D W MOD REG R/M LB HB
Displacement Displacement

100010 0 1 10 010 110 34 12

89 96 34 12 H
 Generate code for the following Instructions
OPCODE D W MOD REG R/M
3. ADD OFABE [BX][DI], DX The 6 bit opcode of ADD is 000000
DX is source register. Therefore, D is 0.
W should be 1 to represent 16 bit data operation
Mod → 10 ; REG →010; R/M → 001
Therefore, machine code is
OPCODE D W MOD REG R/M LB HB
Displacement Displacement

000000 0 1 10 010 001 BE FA

01 91 BE FAH
 Generate code for the following Instructions
OPCODE D W MOD REG R/M
4. MOV AX, [BX] The 6 bit opcode of MOV is 100010
AX is destination register. Therefore, D is 1.
W should be 1 to represent 16 bit data operation
Mod → 00 ; REG →000; R/M → 111
Therefore, machine code is
OPCODE D W MOD REG R/M
8B 07H
100010 1 1 00 000 111
 Instruction set of 8086
I. Data copy/ transfer instructions

II. Arithmetic &logical instructions -

III. Brach instructions – call, jump, interrupt, return

IV. Loop instructions - LOOP, LOOPNZ, LOOPZ

V. Machine control instructions – NOP, HLT, WAIT, LOCK

VI. Flag manipulation instructions - CLI, STI, CLD, STD

VII. Shift and rotate instructions

VIII. String instructions – load, move, scan, compare

 1. Data copy/ transfer instructions
All the store, move, load, exchange, input & output instruction come in this category
 Loading Segment Register with Immediate data is not possible
Ex. Load DS with 5000H Examples of MOV instructions for
different addressing mode are
MOV DS, 5000H; Not permitted
1. MOV AX, 5000H Immediate
MOV AX, 5000H 2. MOV AX, BX Register

MOV DS, AX 3. MOV AX, [SI] Indirect

4. MOV AX, [2000H] Direct

Based relative with

5. MOV AX, 50H[BX]
50H displacement
PUSH
Physical SS = 2000H
Address SP
Examples:
PUSH AX PUSH DS
AH AL 22H 2FFFD FFFD PUSH [5000H]

55 22 55H 2FFFE FFFE

XX 2FFFF FFFF
POP
Physical SS = 2000H
Address SP
Examples:
POP AX POP DS
AH AL 22H 2FFFD FFFD POP [5000H]
55H 2FFFE FFFE
55 22
XX 2FFFF FFFF
XCHG-Exchange

XCHG Destination, Source

XCHG [5000H], AX

XCHG BX, AX
IN – data input to μp from a port

IN Accumulator, Port Address

IN AL, 08H

MOV DX, 0804H

IN AX, DX
OUT- data out from μp to a port
OUT Port Address, Accumulator
LEA-load effective address

LEA Register, Source Label

LEA BX, ADR

LEA SI, ADR[BX]
LDS/LES-load DS/ES and the destination register from Source
memory

LDS/LES Register, Memory address

LDS BX, 5000H /LES BX, 5000H

LAHF-Load lower byte of flag register to AH
SAHF- Store AH to lower byte of flag register
PUSHF
POPF
 Logical Instructions
Mnemonic Meaning Format Operation Flags Affected
OF, SF, ZF, PF, CF
AND Logical AND AND D, S (S) · (D) → (D)
AF undefined
OR Logical Inclusive OR OR D,S (S)+(D) → (D) OF, SF, ZF, PF, CF
AF undefined
XOR Logical Inclusive OR XOR D,S (S) (D)→(D) OF, SF, ZF, PF, CF
AF undefined
NOT LOGICAL NOT NOT D (D) → (D) None

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Shift and Rotate Instructions

31
 Logical vs Arithmetic Shifts
• A logical shift inserts the new vacant bit position with zero:

0
CF

• An arithmetic shift inserts the new vacant bit

position by copying sign bit or MSB

CF

32
 Shift Instructions
Mnemo Meaning Format Operation Flags Affected
-nic
SAL/SHL Shift SAL/SHL D, Count Shift the destination operand left CF,PF,SF,ZF
arithmetic by the number of bit positions AF undefined
Left/shift equal to count and fill the OF undefined if
Logical left vacated bits positions on the right count ≠1
with zeros
SHR Shift logical SHR D, Count Shift the (D) right by the number CF,PF,SF,ZF
right of bit positions equal to count AF undefined
and fill the vacated bits positions OF undefined if
on the left with zeros count ≠1

SAR Shift SAR D, Count Shift the (D) right by the number CF,PF,SF,ZF
arithmetic of bit positions equal to count AF undefined
right and fill the vacated bits positions OF undefined if
on the left with the original most count ≠1
significant bit

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 Rotate Instructions
Mnem Meaning Format Operation Flags Affected
-onic
ROL Rotate Left ROL D,Count Rotate the (D) left by the number of bit CF
positions equal to Count. Each bit shifted OF undefined if
out from the left most bit goes back into count ≠ 1
the rightmost bit position.

ROR Rotate Right ROR D,Count Rotate the (D) right by the number of bit CF
positions equal to Count. Each bit shifted OF undefined if
out from the rightmost bit goes back into count ≠ 1
the leftmost bit position.
RCL Rotate Left RCL D,Count Same as ROL except carry is attached to CF
through (D) for rotation. OF undefined if
Carry count ≠ 1
RCR Rotate right RCR D,Count Same as ROR except carry is attached to CF
through (D) for rotation. OF undefined if
Carry count ≠ 1

34
ROL Instruction
• ROL (rotate) shifts each bit to the left
• The highest bit is copied into both the Carry flag and
into the lowest bit
• No bits are lost

CF

MOV Al,11110000b
ROL Al,1 ; AL = 11100001b

MOV Dl,3Fh
ROL Dl,4 ; DL = F3h
35
ROR Instruction
• ROR (rotate right) shifts each bit to the right
• The lowest bit is copied into both the Carry flag and into
the highest bit
• No bits are lost

CF

MOV AL,11110000b
ROR AL,1 ; AL = 01111000b

MOV DL,3Fh
ROR DL,4 ; DL = F3h
36
 RCL Instruction
• RCL (rotate carry left) shifts each bit to the left
• Copies the Carry flag to the least significant bit
• Copies the most significant bit to the Carry flag

CF

CLC ; CF = 0
MOV BL,88H ; CF,BL = 0 10001000b
RCL BL,1 ; CF,BL = 1 00010000b
RCL BL,1 ; CF,BL = 0 00100001b
37
RCR Instruction
• RCR (rotate carry right) shifts each bit to the right
• Copies the Carry flag to the most significant bit
• Copies the least significant bit to the Carry flag

CF

STC ; CF = 1
MOV AH,10H ; CF,AH = 00010000 1
RCR AH,1 ; CF,AH = 10001000 0

38
Flag control instructions
MNEM- MEANING OPERATION Flags
ONIC Affected
CLC Clear Carry Flag (CF)  0 CF
STC Set Carry Flag (CF)  1 CF
CMC Complement (CF)  (CF)l CF
Carry Flag
CLD Clear Direction (DF)  0
Flag SI & DI will be auto incremented while DF
string instructions are executed.
STD Set Direction (DF)  1
Flag SI & DI will be auto decremented DF
while string instructions are executed.
CLI Clear Interrupt (IF)  0 IF
Flag
STI Set Interrupt (IF)  1 IF
Flag
39
Compare Instruction, CMP
Mnemo Meaning Format Operation Flags
nic Affected

CMP Compare CMP D,S (D) – (S) is used in CF, AF, OF,
setting or resetting the PF, SF, ZF
flags

Allowed Operands
Destination Source
(D) = (S) ; ZF=1
Register Register
(D) > (S) ; ZF=0, CF=0 Register Memory
(D) < (S) ; ZF=0, CF=1 Memory Register
Register Immediate
Memory Immediate
Accumulator Immediate
40
String Manipulation Instructions

41
 REP: Repeat Instruction prefixes

Prefix Option Used for Significance

REP MOVS Repeat until CX ≠ 0
STOS CX is automatically decremented at each
iteration
REPE/REPZ CMPS Repeat while not end of string and strings
SCAS are equal. CX ≠ 0 and ZF = 1
REPNE/REPNZ CMPS Repeat while not end of string and strings
SCAS are not equal. CX ≠ 0 and ZF = 0

42
 MOVSB/MOVSW: Move String Byte or String Word
Mnemonic meaning format Operation Flags
effect-ed

MOVS Move string MOVSB/M ((ES)*10+(DI))  ((DS)*10+(SI)) none

DS:SI →ES:DI OVSW (SI)  (SI) ± 1 or 2
(DI)  (DI) ± 1 or 2

43
 CMPSB/CMPSW: Compare String Byte or String Word
Mnemonic meaning format Operation Flags
effect-ed

Based on the result the flag

status bits are set
Compare string CMPSB/ ((DS)*10+(SI)) - ((ES)*10+(DI)) All status
CMPS
DS:SI →ES:DI CMPSW (SI)  (SI) ± 1 or 2 flags
(DI)  (DI) ± 1 or 2

44
CMPSB/CMPSW: Compare String Byte or String Word
Mnemo- meaning format Operation
Nic
SCAS Scan string SCASB/ Set flags as per
AX – ES:DI SCASW (AL or AX) - ((ES)0+(DI))
(DI)  (DI) ± 1 or 2

LODS Load string LODSB/ (AL or AX)  ((DS)0+(SI))

DS:SI → AX LODSW (SI)  (SI) ± 1 or 2

STOS Store string STOSB/ ((ES)0+(DI))  (AL or A) ± 1 or 2

ES:DI  AX STOSW (DI)  (DI) ± 1 or 2

45
CMPSB/CMPSW: Compare String Byte or String Word
Mnemo- meaning format Operation
Nic
SCAS Scan string SCASB/ Set flags as per
AX – ES:DI SCASW (AL or AX) - ((ES)0+(DI))
(DI)  (DI) ± 1 or 2

LODS Load string LODSB/ (AL or AX)  ((DS)0+(SI))

DS:SI → AX LODSW (SI)  (SI) ± 1 or 2

STOS Store string STOSB/ ((ES)0+(DI))  (AL or A) ± 1 or 2

ES:DI  AX STOSW (DI)  (DI) ± 1 or 2

46
CMPSB/CMPSW: Compare String Byte or String Word
Mnemo- meaning format Operation
Nic
SCAS Scan string SCASB/ Set flags as per
AX – ES:DI SCASW (AL or AX) - ((ES)0+(DI))
(DI)  (DI) ± 1 or 2

LODS Load string LODSB/ (AL or AX)  ((DS)0+(SI))

DS:SI → AX LODSW (SI)  (SI) ± 1 or 2

STOS Store string STOSB/ ((ES)0+(DI))  (AL or A) ± 1 or 2

ES:DI  AX STOSW (DI)  (DI) ± 1 or 2

47