COMPUTER SYSTEM ARCHITECTURE

UNIT-1
Computer Architecture is abstract model and are those attributes
that are visible to programmer like instructions sets, no of bits used
for data, addressing techniques. It describes what the computer
does.

A computer's organization expresses the realization of the

architecture. OR how features are implemented like these registers
,those data paths or this connection to memory. contents of CO are
ALU, CPU and memory and memory organizations. It describes
how the computer performs.
BASIC STRUCTURE OF COMPUTER
REGISTER
A register is a group of flip-flops with each flip-flop capable of
storing one bit of information.
A-n bit register has a group of flip flops and is capable of storing
any binary information of n-bits.
The transfer of new information into a register is referred as loading
the register.
REGISTER TRANSFER LANGUAGE
The operations that are executed on data stored in registers are called
micro operations.
A micro operation is an elementary operation performed on the
information stored in one or more registers.
The result of the operation may replace the previous binary
information of a register or may by transferred to another register.
Examples of micro operations are shift, count, clear and load.
The symbolic notation used to describe the micro operation transfer
among registers is called a register transfer language.
The term “register transfer” implies the availability of hardware
logic circuits that can perform stated micro operation and transfer
the results to the operation to the same or another register.
Register transfer language
⚫ A symbolic language
⚫ A convenient tool for describing the internal organization of
digital computers
⚫ Can also be used to facilitate the design process of digital
systems.
It is a kind of hardware description language (HDL) used in
describing the registers of a computer or digital electronic system,
and the way in which data is transferred between them.
DESIGNATION OF REGISTERS

Computer Registers are designated by capital letters, (sometimes

followed by numbers) to denote the function of registers.
For example:
⚫ MAR- register that holds an address for memory unit also called as
memory address register.
⚫ PC- A program counter (PC) is a CPU register in
the computer processor which has the address of the next
instruction to be executed from memory.
⚫ IR- an instruction register (IR) is the part of a CPU's
control unit that holds the instruction currently being
executed.
Registers and their contents can be viewed and represented in
various ways
⚫ A register can be viewed as a single entity:

MAR

⚫ Registers may also be represented showing the bits of data they contain

7 6 5 4 3 2 1 0
REPRESENTATION OF REGISTERS IN BLOCK DIAGRAM

The most common way to represent a register is by a rectangular

box with the name of register inside:

R1

(a) Register R1
The individual bits can be distinguished as follows:

R : High Low
76543210

(b) Showing individual bits

The numbering of bits in a 16-bit register can be marked on top of
the box as shown:

15 0
R2

(c) Numbering of bits in R2

A 16 bit register is partitioned into tow parts. Bits 0 through 7 are

assigned the symbol L (for low byte) and bits 8 to 15 are assigned
the symbol H (for high byte).

15 87 0
The symbol PC(0-7) or
PC (H) PC (L) PC(L) refers to low-order
byte

(d) PC register divided into a

High and a Low part The symbol PC(8-15) or
PC(H) refers to
high-order byte
REGISTER TRANSFER
Information transfer from one register to another is designated in
symbolic form by means of a replacement operator. The statement

R2 ← R1

Denotes a transfer of the content of register R1 into register R2.

Also, the contents of R1 are not altered by copying (loading) them to
R2 i.e., this is a non- destructive.
A simultaneous transfer of all bits from the source R1 to the destination
register R2, during one clock pulse
CONTROL FUNCTIONS
Sometimes actions are need to only occur if a certain condition is
true
This is similar to an “if” statement in a programming language.
When we want transfer to occur only under a predetermined control
condition it can be shown by means of if-then statement.
If (P=1) then (R2 R1)
In digital systems, this is often done via a control signal, called a
control function
⚫ If the signal is 1, the action takes place
This is represented as
P: R2 ← R1
The control condition is terminated with a colon.
It symbolizes that the transfer operation is executed by hardware
only if P=1.
HARDWARE IMPLEMENTATION FOR CONTROLLED TRANSFER

Figure on right shows block diagram that depicts transfer from R1

R2.

The letter n represents any number of bits for register.

Register R2 has load input that is activated by control variable P.
It is assumed that control variable P is synchronized with the same
clock as applied to register.
Timing diagram:

P is activated by the rising edge of a clock pulse at time t.

The next positive transition of clock at time t+1 finds load input
active and the data is being loaded into R2.
Registers are assumed to use positive-edge-triggered flip-flops
SIMULTANEOUS OPERATIONS
If two or more operations are to occur simultaneously, they are
separated with commas
T: R2 R1, R1 R2

The above statement denotes that exchanges the contents of two

registers during one common clock pulse when the control function
T=1.

What does following statement means?

P: R3 ← R5, MAR ← IR
Following Table denotes the basic symbols of the register transfer
notation:

Also note, ^ symbol is AND

V is OR if it occurs in condition
But, + is “plus” if occurs in register transfer statements
RTL EXAMPLE-

Register Transfer Language (RTL)

If (condition) then (register-transfer)
is written as
condition: register-transfer

T1 ^ p4: R1 R2

This is read as :
⚫ If (T1 ^ p4) then R1 R2
⚫ If T1 and p4, then R1 gets the contents of R2
RTL SYNTAX

Bits are numbered from the rightmost bit 0 (least significant) to

leftmost bit n-1 (most significant)
R1(0 - 3) denotes bits R13, R12, R11, and R10
R1 ← M[AR] denotes that register R1 gets the data from memory
“pointed to” by the contents of the address register i.e., AR
⚫ A register transfer language statement has a one-to-one correlation with
hardware connections
HOW TO CONNECT REGISTERS?
A typical digital computer has many registers, and paths must be
provided to transfer information from one register to another.
The number of wires will be excessive if separate lines are used
between each registers and all other registers in the system.
For example:- To completely connect n registers n(n-1) lines are
needed i.e., O(n2) cost
⚫ This is not a realistic approach to use in a large digital system
Instead, take a different approach
⚫ Have one centralized set of circuits for data transfer – the bus.
⚫ Have control circuits to select which register is the source, and which is
the destination
BUS AND BUS TRANSFER
Bus is a path(of a group of wires) over which information is
transferred, from any of several sources to any of several
destinations.
A bus structure consists of a set of common lines, one for each bit of
a register through which binary information is transferred one at a
time.
Control signals determine which register is selected by the bus
during each particular register transfer.
From a register to bus: BUS R

Register A Register B Register C Register D

Bus lines
One way of connecting a common bus system is with multiplexers.
The multiplexers select the source register whose binary information
is placed on the bus.
The construction of a bus system for four registers is shown below:
Each register has 4 bits, numbered 0 to 3.
The bus consists of four 4 x1 multiplexers each having four data inputs , 0
through 3, and two selection inputs, S1 and S0 .
Output 1 of register A is connected to input 0 of MUX 1 because this
input is labeled A1.
MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes
the four 1 bits of the registers and similarly for the other two bits.
BUS SELECTION:
The two selection lines S1 and S0 are connected to the selection
inputs of all 4 multiplexers.
Consider the table:

S1 S2 Register Selected
0 0 A
0 1 B
1 0 C
1 1 D

When S1 S0 = 00, the 0 data inputs of all 4 multiplexers are selected

& applied to outputs that from the bus. Thus the bus lines receive the
content of register A.
Similarly Register B is selected if S1 S0 = 01 and so-on.
HOW MANY NO. OF MULTIPLEXERS DO WE NEED?
In general a bus system will multiplex k registers of n bits each to
produce an n-line common bus.
The number of multiplexers needed to construct the bus ins equal to
n, the number of bits in a register.
The size of each multiplexer must be k x 1 since it multiplex k data
lines.

Example- A common bus for eight registers of 16 bits need to be

constructed. How many multiplexers & of what size will be
required?
Answer- 16 multiplexers are needed, one for each line in a bus.
Each multiplexers must have 8 data input lines and 3 selection lines.
BUS TRANSFER IN RTL

The symbolic statement for a bus transfer may mention the bus or its
presence may be implied in the statement.
When the bus is includes in the statement, the register transfer is
symbolized as follows:
BUS C, R1 BUS

The content of register C is placed on the bus, and the content of the
bus is loaded into register R1.
If the bus is known to exist in the system, it may be convenient just
to show the direct transfer.
R1 C
THREE- STATE BUS BUFFERS
A bus system can also be constructed with three-state gates instead
of multiplexers.
Three-state gate- It is a digital circuit that exhibits 3 states. Two of
the states are logic 1 and logic 0 as in conventional gate. The third
state is high-impedance state. The high-impedance state behaves
like an open circuit, which means that the output is disconnected and
does not have a logic significance.

Essentially, the buffer unit “holds” the value stored in the Flip flop.
 The graphic symbol of a three-state buffer gate is shown as below:

Normal Output Y=A if C=1

input A High-impedance if C=0

Control
input C
When the control input=1, the output is enabled and the gate
behaves likes normal buffer with the output equal to normal input.
When the control input is 0, the output is disabled and the gate goes
to high-impedance state, regardless of the value in normal input.
BUS SYSTEM THROUGH THREE-STATE BUFFER

The construction of a bus system with 3 state buffer is demonstrated

in below figure:

Bus line for bit 0

R0

R1
R2
R3

S0 0
Select { S1
2x4
decoder 1
2
Enable E 3
BUS SYSTEM THROUGH THREE-STATE BUFFER

The construction of a bus system with 3 state buffer is demonstrated

in below figure:

Bus line for bit 0

R0

R1
R2
R3

1
S0 0
Select {
0 S1 2x4
decoder 1
1 2
Enable E 3
The outputs of four buffers are connected together to form a single bus line.
The control inputs to the buffer determines which of the four normal inputs
will communicate with the bus line.
No more than one buffer may be in active state at any given time.
One way to ensure that no more than one control input is active at any given
time is to use a decoder (as shown in diagram).
When enable=0, all of its four output are 0 due to which bus-line is in high
impedance state.
When enable input is=1 (active), one of the 3-state buffer will be active,
depending on the binary value in the selected inputs.
Consider the table:

Enable S1 S0 Register Selected

1 0 0 R0
1 0 1 R1
1 1 0 R2
1 1 1 R3
0 X X High-impedance state
COMPLETE DIAGRAM FOR A BUS SYSTEM USING DECODER
& TRI-STATE BUFFER
HOW MANY DECODERS & 3-STATE BUFFERS ARE NEEDED?
To construct a common bus for four registers of n bits each using
3-state buffers, we need n circuits with four buffers.
Each group of four buffers receives one significant bit from the four
registers.
Only one decoder is necessary to select between four registers.
MEMORY(RAM)
Memory (RAM) can be thought as a sequential circuits containing
some number of registers.
These registers hold the words of memory
Each of the r registers is indicated by an address.
These addresses range from 0 to r-1.
Each register (word) can hold n bits of data.
Assume the RAM contains r = 2k words. It needs the following
⚫ n data input lines
⚫ n data output lines data input lines
⚫ k address lines
n
⚫ A Read control line
⚫ A Write control line address lines
k
RAM
Read
unit
Write
n
data output lines
MEMORY TRANSFER
Collectively, the memory is viewed at the register level as a device, M.
A memory word will be symbolized by the letter M.
Since it contains multiple locations, we must specify which address in
memory we will be using, by enclosing the address in square brackets
following the letter M.
Eg: M[AR] – this specifies the memory unit that receives the address from
a register AR.
Memory is usually accessed in computer systems by putting the desired
address in a special register, the Memory Address Register (MAR, or AR)
When memory is accessed, the contents of the MAR get sent to the
memory unit’s address lines

Rea
Memor
A d
y
R unit Writ
e

Data Data
out in
MEMORY READ
The transfer of information from a memory word to the outside
environment is called a read operation.
To read a value from a location in memory and load it into a register,
the register transfer language notation looks like this:

R1 ← M[AR]
This causes the following to occur:
⚫ The contents of AR are being put on address lines.
⚫ Activate the memory read control signal on the control bus.
⚫ Wait for the memory to retrieve the data from the address memory
location and put it on data lines.
⚫ Read the data from the data bus and load into register R1.
MEMORY WRITE
The transfer of new information to be stored into the memory is
called write operation.
The write operation can be stated symbolically as follows:

M[AR] R1

This causes the following to occur-

⚫ The contents of AR are being put on address lines.
⚫ Activate the memory write control signal on the control bus.
⚫ The values in register R1 are put over the bus to the data input lines of the
memory.
⚫ The values get loaded into the specified address in the memory
SUMMARY OF REGISTER TRANSFER
MICRO-OPERATIONS
Operation Description
A←B Transfer content of reg. B into reg. A
AR ← DR(AD) Transfer content of AD portion of reg. DR into reg. AR

A ← constant Transfer a binary constant into reg. A

ABUS ← R1, Transfer content of R1 into bus A and, at the same time, transfer
content of bus A into R2
R2 ← ABUS
AR Address register
DR Data register
M[R] Memory word specified by reg. R
M Equivalent to M[AR]

DR ← M Memory read operation: transfers content of memory word

specified by AR into DR
M ← DR Memory write operation: transfers content of DR into memory
word specified by AR