Module 5:

CMOS Combinational Circuit Design

 Outline

Static CMOS
Ratioed Logic
Cascode voltage Switch Logic
Dynamic circuits
Pass Transistor Circuits
 Introduction

What makes a circuit fast?

I = C dV/dt -> tpd  (C/I) V
low capacitance B 4
high current A 4
Y
small swing 1 1
Logical effort is proportional to C/I
pMOS are the enemy!
High capacitance for a given current
Can we take the pMOS capacitance off the input?
Various circuit families try to do this…
 Static CMOS: Bubble Pushing

Start with network of AND / OR gates

Convert to NAND / NOR + inverters
Push bubbles around to simplify logic
Remember DeMorgan’s Law
 Static CMOS: Compound Gates

Logical Effort of compound gates

 Input Order
Our parasitic delay model was too simple
Calculate parasitic delay for Y falling
• If A arrives latest? 2
• If B arrives latest? 2.33 2 2 Y
A 2 6C

B 2x 2C

if input A rises last, node x will initially be at 0 V because it was discharged through the
nMOS transistor on input B. No charge must be delivered to node x
R(6C) = 6RC = 2 

If input B rises last, node x will initially be at VDD because it was pulled up through the
nMOS transistor on input A.
(R/2)(2C) + R(6C) = 7RC = 2.33 
 Inner & Outer Inputs

Inner input is closest to output (A)

Outer input is closest to rail (B)

If input arrival time is known

Connect latest input to inner terminal to reduce delay
 Asymmetric Gates
Asymmetric gates favor one input over another
Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance)
Boost size of noncritical input
A
So total resistance is same reset
Y

gA = 10/9
gB = 2 2 2
Y

gtotal = gA + gB = 28/9 A 4/3

reset 4

Asymmetric gate approaches g = 1 on critical input

But total logical effort goes up
 Skewed Gates

Skewed gates favor one edge over another

Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor
HI-skew unskewed inverter unskewed inverter
inverter (equal rise resistance) (equal fall resistance)

2 2 1
A Y A Y A Y
1/2 1 1/2

Calculate logical effort by comparing to unskewed

inverter with same effective resistance on that edge.
gu = 2.5 / 3 = 5/6
gd = 2.5 / 1.5 = 5/3
 HI- and LO-Skew

Def: Logical effort of a skewed gate for a particular

transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.

Skewed gates reduce size of noncritical transistors

HI-skew gates favor rising output (small nMOS)
LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction
But larger for the other direction
 Catalog of Skewed Gates
Inverter NAND2 NOR2

2 2 B 4
Y
2 A 4
A 2
unskewed A Y Y
1 gu = 1 B 2 gu = 4/3 1 1 gu = 5/3
gd = 1 gd = 4/3 gd = 5/3
gavg = 1 gavg = 4/3 gavg = 5/3

2 2 B 4
Y
2 A 4
A 1
HI-skew A Y Y
1/2 g = 5/6 B 1 gu = 1 1/2 1/2 gu = 3/2
u
gd = 5/3 gd = 2 gd = 3
gavg = 5/4 gavg = 3/2 gavg = 9/4
1 1 B 2
Y
1 A 2
A 2
LO-skew A Y Y
1 gu = 4/3 B 2 gu = 2 1 1 gu = 2
gd = 2/3 gd = 1 gd = 1
gavg = 1 gavg = 3/2 gavg = 3/2
Logical Effort of Skewed NAND Gate
Logical Effort of Skewed NAND Gate
 Ratioed Logic: Pseudo-nMOS
In the old days, nMOS processes had no pMOS
Instead, use pull-up transistor that is always ON
In CMOS, use a pMOS that is always ON
Ratio issue: The pMOS transistor widths are 1/4 the
strength (i.e., 1/2 the effective width) of the nMOS
pulldown network
1.8

load 1.5
P/2
1.2
P = 24
Ids Vout 0.9
Vout
0.6
16/2 P = 14
Vin 0.3
P=4

0
0 0.3 0.6 0.9 1.2 1.5 1.8
Vin
Static Power Dissipation: PMOS always ON
 Pseudo-nMOS Gates
Design for unit current on output to compare with unit inverter.
The logical effort for each transition is computed as the ratio of the input
capacitance to that of a complementary CMOS inverter with equal current
for that transition. Y
inputs
A complementary CMOS unit inverter delivers current I in both rising and
falling transitions. The pMOS transistors produce I/3 and the nMOS f
networks produce 4I/3. Output current is (4I/3 – I/3) = I.
Logical effort for a falling transition of the pseudo-nMOS inverter is the ratio of its input
capacitance (4/3) to that of a unit complementary CMOS inverter (3), i.e., 4/9.
gu is three times as great because the current is 1/3 as much.
Inverter NAND2 NOR2

gu = 4/3 gu = 8/3 gu = 4/3

gd = 4/9 2/3 g = 8/9 gd = 4/9
gavg = 8/9 Y gd = 16/9 gavg = 8/9
2/3 avg 2/3
A 8/3
Y pu = 6/3 pu = 10/3 Y pu = 10/3
A 4/3 pd = 6/9 B 8/3 pd = 10/9 A 4/3 B 4/3 pd = 10/9
pavg = 12/9 pavg = 20/9 pavg = 20/9
Pseudo-nMOS Gates
Pseudo-nMOS Gates
 Cascode Voltage Switch Logic
Cascode Voltage Switch Logic seeks the benefits of ratioed circuits without the static
power consumption. It uses both true and complementary input signals and computes both
true and complementary outputs using a pair of nMOS pulldown networks

For any given input pattern, one of the pulldown networks will be ON and the other OFF.
The pulldown network that is ON will pull that output low.
This low output turns ON the pMOS transistor to pull the opposite output high.
When the opposite output rises, the other pMOS transistor turns OFF so no static power
dissipation occurs.
 Dynamic Logic
Dynamic circuits circumvent these drawbacks by using a
clocked pullup transistor rather than a pMOS that is
always ON.
Two modes: precharge and evaluate

2 2/3  1
A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

 Precharge Evaluate Precharge

Y
 Dynamic Logic

 Precharge Evaluate Precharge

During precharge, the clock is 0, so the clocked pMOS is ON and initializes the output
Y high.

During evaluation, the clock is 1 and the clocked pMOS turns OFF. The output may
remain high or may be discharged low through the pulldown network.

Dynamic circuits are the fastest commonly used circuit family because they have lower
input capacitance and no contention during switching. They also have zero static
power dissipation.
 Dynamic Logic

precharge transistor
 Precharge Evaluate Precharge 
Y
A
Y
foot

If the input A is 1 during precharge, contention will take place because both the pMOS
and nMOS transistors will be ON.
When the input cannot be guaranteed to be 0 during precharge, an extra clocked
evaluation transistor can be added to the bottom of the nMOS stack to avoid contention.
The extra transistor is called a foot.
 Logical Effort

Inverter NAND2 NOR2

 1
Y
 1  1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = 1/3 gd = 2/3 gd = 1/3
pd = 2/3 pd = 3/3 pd = 3/3

 1
Y
 1  1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = 2/3 gd = 3/3 gd = 2/3
2 pd = 3/3 3 pd = 4/3 2 pd = 5/3
 Monotonicity

Dynamic gates require monotonically rising inputs

during evaluation
0 -> 0 

0 -> 1 A

1 -> 1
But not 1 -> 0 violates monotonicity
during evaluation
A

 Precharge Evaluate Precharge

Output should rise but does not

 Monotonicity Woes

But dynamic gates produce monotonically falling

outputs during evaluation
Illegal for one dynamic gate to drive another!

A=1

  Precharge Evaluate Precharge

Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot
 Domino Gates

Follow dynamic stage with inverting static gate

Dynamic / static pair is called domino gate
Produces monotonic outputs
 Precharge Evaluate Precharge

domino AND
W

W X Y Z X
A
Y
B C

Z

dynamic static
 
NAND inverter  
A W X A X
H Y =
B H Z B Z
C C
 Dual-Rail Domino
Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR Y_l  Y_h
Dual-rail domino solves this problem inputs
f f
Takes true and complementary inputs

Produces true and complementary outputs

sig_h sig_l Meaning

0 0 Precharged

0 1 ‘0’

1 0 ‘1’
 Pass Transistor Circuits
Use pass transistors like switches to do logic
Inputs drive diffusion terminals as well as gates

CMOS + Transmission Gates:

2-input multiplexer
Gates should be restoring

S S

A A

S Y S Y

B B

S S
Sizing of Complex Gates
Sizing of Complex Gates
Sizing of Complex Gates
Sizing of Complex Gates