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FAST FOURIER TRANSFORM BY VERILOG

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 FAST FOURIER TRANSFORM BY VERILOG
Hina Magsi Ali Hassan Sodhro
Department Of Electrical Engineering Department Of Electrical Engineering
Sukkur Institute of Business Administration, University Sukkur Institute of Business Administration, University
Sukkur, Pakistan Sukkur, Pakistan and DISP LAB, University Lumiere
[email protected] Lyon2, Lyon, France
[email protected], [email protected]

Abstract—The paper presents the Verilog coding of Fast and amplitude would be difficult to analyze in time domain
Fourier transform implementation on Vivado. The butterfly [19]. Due to this reason the signal would be converted into
diagram used to design the Fast Fourier transform of given input frequency domain to get the complete information. In IoMT
signals. The FFT is useful and efficient tool in digital signal (Internet of Medical Things) FFT plays an important role. As
processing especially in the area of digital signal and image
EEG and ECG are highly noisy and difficult for processing.
processing. It has also been used in new technologies like internet
of medical things for extracting desired information from signal. That’s why extraction information form this signal is the main
The Verilog implementation of FFT which includes complex issue. To extract the detailed and meaningful information from
numbers addition and multiplication due to twiddle factor. It is noisy signal in order to get the best analytics FFT is used. It
an efficient and fast method which requires less computations converts the noisy data into desired information and reduces
and produces output in short time. the noise level. It provides the detailed information in
frequency domain. The frequency domain representation of
Keywords— fast fourrier trasnsform(FFT) ,dicrete fourier signals educes the computational complexity of various digital
transform(DFT),twiddle factor. processing systems. In the field of ultrasonic echo signals FFT
increased the computational speed and accuracy which makes
I. INTRODUCTION the system performance better. The FFT is the center part in
The main purpose in digital signal processing is to reduce the Doppler blood flow spectrum analysis and also used in
requirements of hardware and increased the computation. The Doppler imaging system [1]. The results of DFT and FFT are
Fast Fourier transform (FFT) is an algorithm which samples same only difference is the reduction in the calculations. FFT
the signal over some space and splits them into frequency
points. This method is used to get the discrete Fourier
transform of the signal and it converts the signal into its
frequency domain. It has advantage over DFT because it
reduces the complexity of DFT from O(N^2) to O(NlogN)
where N represents the data points. The fast method to
compute the DFT (Discrete Fourier transform) is the FFT (fast
Fourier transform). It has many applications like spectral
analysis, matched filtering, image processing and disease
extractions. When FFT was developed the real time digital
signal become realized in many fields such as radar and
communications. There are many situations where FFT Fig: 2 Bit Reversal [11]
computation is required to face the real-time data like medical
diagnosis and earthquake monitoring and so on [17]. The divides the data into smaller sets (even and odd) [12]. There
detailed information about spectrum of signal in frequencies are two types of division known division in time and division
in frequency. The division in time requires bit reversed output
and produces normal output order while division is frequency
takes normal input order and generates bit reversed output
[14]. This paper uses the division in time method. Each stages,
the results of previous stage are combined. The Fig. 1 shows
the butterfly diagram of 8-point FFT [9]. The butterfly is part
of the FFT computation which combines smaller DFT point
into larger points. The name butterfly implies that the shape of
the flow of data as shown in Fig. 1. In every stage first inputs
are multiplied by twiddle factor and add or subtract to other
input. The points defines the stages of butterfly like 8-point
have 3 stages, 16-point have 4 stages and so on. In FFT

Fig. 1 Butterfly Representation [9]

calculation there is concept of bit reversal the inputs are to be Song Yu et al proposed [3] the FFT algorithm by using
bit reversed to produce the outputs bits in the normal order. rotation factor and data address of the node. They uses Verilog
The input bits are divided into even and odd parts and these HDL platform for design and realization of data address and
parts are divided into even and odd parts. This process is also compilation is done on PLD software. They concludes that
continued till only two points left [11]. In the paper the input FFT with FPGA is easy for expansion and it has real-time data
sequence is (x0,x1,x2,x3,x4,x5,x6,x7) and after bit reversed capability.
the sequence becomes (x0,x4,x2,x4,x1,x5,x3,x7) . This is Athira et al introduced the FFT application in telemetry
shown in Fig. 2[11]. data processing applications [4]. They uses vedic mathematics
The main contribution of this paper is to design FFT for multiplications. The Urdhva Tiryakbhyam sutra method is
algorithm using radix-2 Verilog code, implemented and used because it reduces the computation complexity of
verified on vivado. The block diagram implemented on multipliers. They proposed the 24 bit floating point
Vivado is shown in Fig.3. implementation using IEEE754 multiplication on vedic
Remaining part of this paper is organized as follow. mathematics and compare the results with conventional
Section II discussed the literature review, Section III explained method. The carry adder or ripple carry adder improved the
the proposed algorithm on Vivado, results are shown in performance of addition part. The design was done on Verilog
Section IV and finally the paper is concluded in Section V. while simulations stage was carried out using Modelsim.
Zakir et al presents the Q format constant multipliers for
FFT processors with implementation on hardware improves the
speed of the multipliers [5]. The common sub expression
elimination (CSE) method and canonical signed Digit (CSD) is
used to reduce number of adder which also reduces hardware
specifications. They presented the design for 8bits, 10 bits and
16bits using Verilog and implement this system on Altera
device.
Ibrahim at al proposed the radix-2 FFT algorithm to be
implemented and investigated on FPGA and Graphic
Processing Units (GPU). [6] The Verilog HDL is used for
FPGA and Open Computing Language is used for GPU. They
compares both results and concludes that FFT of small sizes
produces faster result on FPGA while GPU can used for larger
sizes of FFT. Also FPGA implementations is faster than built-
in IP core Xilinx.
Archna et al presents the [7] importance of Hilbert
algorithm in digital signal processing like modulation,
Fig: 3 RTL diagram frequency analysis and audio production. They proposed the
realization of this algorithm by radix 2^2 single path delay
II. LITERATURE REVIEW feedback (SDF) pipelined FFT processor which can be used in
There are many researchers who have worked on FFT envelope detection. The system has implemented on Xilinx
Verilog code.
algorithm and implement the different methods. Some of the
work are discussed below. Ravi et al proposed the bit-reversal part of FFT. The
Zhou et al proposed the FFT processor for high speed and proposed system is simple and efficient for reordering of
real time signal processing [1]. They present FFT design on parallel data formation [8]. They used the parallel pipelined
field programmable gate array (FPGA) by using radix-2 FFT processors. The system has been implemented using
algorithm and also pipeline structure for butterfly algorithm Verilog HDL and simulated on Modelsim.
and Ping-Pone for memory unit. They compared the theoretical
Anup et al compares the [9] DFT and FFT in the field of
and practical values in their paper. This structure is very easy
and expandable by changing the twiddle factor and some digital signal processing. They said that FFT is efficient
changes in timings of ping-pone operations. method to compute DFT with larger points. They implemented
FFT algorithm on Verilog by using floating point. They
Sridhanya et al presents the [2] application of FFT in concluded that the FFT reduced the cost and complexity of
MIMO-OFDM (multiple input multiple output orthogonal adders and multipliers.
frequency division multiplexing) systems. They used radix Ns
(number of data streams) butterflies for every stage. Memory Miao et al described the powerful tool FFT used in signal
scheduling and multipath delay commutator is used as processing [10]. The FFT method reduces the computational
hardware implementation which reduced the storage and complexity from O(n^2) to O(NlogN). It is important tool for
provides efficient saving for power. They replaced the twiddle real time data and used in many applications like IoMT. The
factor with complex multiplier and presents the advantages in dot product engine (DPE) method is used for computing FFT
terms of power consumption.
and compared the results with real multiplication operation. 
The DPE cluster can be used for many applications like IoMT. Y (k )   x ( n)e
n 
 j 2 kn / N

Vinodh et al proposed the implementation of FFT pruning where x(n) represents the inputs and exponential part is known
algorithm on FPGA [13]. The FFT reduced the time for k
computation when zero valued number outstrips the non-zero
as twiddle factor( w n
) which includes complex numbers. N is
valued due to excessive computations. This is achieved by the number of data points. The paper proposed implementation
pruning algorithm of FFT and is implemented in hardware. of DIT radix-2 algorithm Fast Fourier Transform using
The computational time consumption is observed. The FFT Verilog on VIVADO software. The design includes the
implementation on FPGA would reduce the computation time implementation of DIT radix-2 8-point FFT butterfly
and easily calculates the DFT [20]. algorithm. The butterfly comprises of three stages. Every stage
is connected with each other to get final output. It takes input
Atin et al [15] proposed the area efficient architecture of sequence and twiddle factor and produces the final desired
radix-2 FFT processor. The algorithm reused the units of output. The twiddle factor is calculated manually and initialize
single stages of butterfly units which reduces the area. The in Vivado. The design includes adders and multipliers of
simulation has been taken on VHDL. The system has been complex numbers. The Fig. 4 illustrated the FFT design radix-
implemented and verified on FPGA. The FFT processor 2. The RTL diagram for radix-2 FFT algorithm is shown in
performance can be increased b recording the size and Fig. 6.The adder and multiplier of radix-2 FFT is shown in
improving SNR of the system [18]. The proposed system Fig.5. It takes 8 bit inputs as (x0,x1,x2,x3,x4,x5,x6,x7),
provides the better results than conventional system of FFT initialize twiddle factor as real (wr) and imaginary part (wi)
processor. and produces the final output after three stages as 8 bit real
Josue et al explained the 16 and 32 bit vertex 6 FFT and imaginary part(𝑦0, 𝑦1,y2,y3,y4,y5,y6,y7). The initial
algorithm on VHDL [16]. The design proposed had used short input values are x0=1, x1=2, x2=4, x3=8, x5=16, x7=64,
area and increase of input-output block can be reduced by x7=128, and the twiddle factors are calculated below and
using parallel in serial out and serial in parallel out shift manual calculations are shown in Table. I.
registers. TABLE I. Manual Calculations
Calculations
Stage 1 output Stage 2 output Stage 3 output

=1+ (1)16=17. =17+ (1)68=85. =85+ (1)170=255.

=1-(1)16=15. =-15+ (-j)-60=-15+j60.
= [-15+j60] + (0.707-j0.707) (-30+j120) = 48+j165.

=4+ (1)64=68. =17- (1)68=-51. =-51+ (-j) (-102) =-

51+j102.

=4-(1)64=-60. =-15-(-j)-60=-15-j60.
= [-15-j60] + (-0.707-j0.707) (-30-j120) =-78+j45.
=2+ (1)32=34 =34+ (1)136=170. =85-(1)170=-85.
=2-(1)32=-30. =-30+ (-j)-120=- =
30+j120. = [-15+j60]-(0.707-j0.707) (-30+j120) =-78-j45.
=8+(1)128=136. =34-(1)136=-102. ==-51-(-j) (-102) =-51-
j102.
=8-(1)128=-120. =-30-(-j)-120=-30-
j120. = [-15-j60] + (-0.707-j0.707) (-30-j120) =48-j165.
 j 2 k / N
e
k
III. PROPOSED FFT ALGORITHM w n
Where N=8

 e  j 2 (0)/8  e0  1
The mathematical representation of Fast Fourier transform [9] 0

is given as: w 8

1 j
 e j 2 (1)/8  e j /4 
1
w 8
2
 e  j 2 (2)/8  e  j / 2   j
2
w 8

(1  j )
 e j 2 (3)/8  e j 3 /4 
3
w 8
2

Fig. 4 DIT Radix-2 FFT

 Fig. 7 Vivado Result

The Fig. 7 shows the waveform result and each stage

output is shown in Table. II.The waveform have been shown
Fig. 5 Adder & Multiplier which includes real and imaginary output.
V. CONCLUSION

FFT has the benefit over DFT because it has less

computations. FFT takes inputs and through adding and
multiplication process produces the output. While DFT has to
make O (N^2) addition and multiplication for higher number of
points. Implemented butterflies algorithm on VIVADO reduces
calculations and makes system more efficient and fast. The
FFT algorithm is used information extracting for ECG, EEG
signals. It is also powerful tool for new technology IoMT. The
future work will to reduce the complexity of multiplications in
FFT to make system more efficient.

ACKNOWLEDGMENT
Fig. 6 RTL diagram of DIT radix-2 FFT This work is funded by HEC Pakistan under the START-
UP RESEARCH GRANT PROGRAM (SRGP) #21-
1465/SRGP/R&D/HEC/2016, and Sukkur IBA University,
IV. RESULTS Sukkur, Sindh, Pakistan.

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