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19CS303 - Embedded System - Midterm Answer Key

The document contains 6 questions related to 8085 microprocessor, ARM architecture and RISC vs CISC processors. Question 1 has two parts related to machine code and address lines. Question 2 describes the sequence of values written during instruction execution. Question 3 contains an assembly language program with sub-questions. Question 4 demonstrates big and little endian storage. Question 5 asks to design a memory interfacing circuit. Question 6 covers RISC vs CISC, ARM features, CPSR access and register values after instructions.

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Navami Sunil
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32 views4 pages

19CS303 - Embedded System - Midterm Answer Key

The document contains 6 questions related to 8085 microprocessor, ARM architecture and RISC vs CISC processors. Question 1 has two parts related to machine code and address lines. Question 2 describes the sequence of values written during instruction execution. Question 3 contains an assembly language program with sub-questions. Question 4 demonstrates big and little endian storage. Question 5 asks to design a memory interfacing circuit. Question 6 covers RISC vs CISC, ARM features, CPSR access and register values after instructions.

Uploaded by

Navami Sunil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Qn (Answer All Questions) Marks

No
1 3+2
a). Write the machine code for the instruction LHLD AF7CH in 8085 microprocessors. (Hint: Opcode of LHLD
is 2AH)
Machine Code: Stored in the memory as 2A, 7C, AF (1.5M)
Binary Code: 0010 1010 0111 1100 1010 1111 (1.5M)

b) How many address bits are required to address 256GB Memory?


= (28 x 230) = (1M)
=38 address lines (1M)
2 5
An 8085 microprocessor executes an instruction “STAX H” with starting address location 1FFEH. While the
instruction is fetched and executed, what will be the sequence of values written at the Program Counter, address
bus, data bus? Mention the corresponding control signals generated.

Address bus – 1FFEH -1M


Data Bus – Machine code of STAX H -1M
Program counter – 1FFFH -1M
Memory Read control signal will be inserted Low -1M
(if block diagram is shown give 5M)
3 4+3+3
a). Consider the assembly language program (ALP) given below.
LXI H, 3000H
LXI D, 5000H
MVI B, 0FH
LOOP: MOV A, M
STAX D
INX H
INX D
DCR B
JNZ LOOP
HLT
i). Mention the addressing mode and instruction size of each instruction in the ALP. (0.5M each)
Instruction Addressing Modes
LXI H, 3000H Immediate Addressing Modes
LXI D, 5000H Immediate Addressing Modes
MVI B, 0FH Immediate Addressing Modes
LOOP: MOV A, Register Addressing Modes
M
STAX D Indirect Addressing Modes
INX H Register Addressing Modes
INX D Register Addressing Modes
DCR B Register Addressing Modes
JNZ LOOP Direct Addressing Modes
HLT Implicit Addressing Modes

ii). How many locations are required to store the above program in memory? 17 memory location
(Specify how many locations for each instruction) – 3 M
iii). What is the overall logic of the program? Transferring 15 memory location data from 3000H to 5000H. –
3M
4 5+5
a). Consider the array given as
Array DCD 0xAABCDEFF
If the starting address of an array is 0X0000000F, then show how the bytes of the 32-bit array elements are
stored in the memory:
a. If the computer system is Big endian
b. If the computer system is Little endian
a)
Memory Data
Address
0X0000000F 0xA
A
0X00000010 0XB
C
0X00000011 0XD
E
0X00000012 0XF
F
b)
Memory Address Data
0X0000000F 0xFF
0X00000010 0XDE
0X00000011 0XBC
0X00000012 0XAA

Address- 2M
Table – 3M
b). In ARM, let register R0 has the value 0xDFACEBA. Predict the output for the following operations? Write
the respective ARM instruction for the following operations.
i. Logical Right Shift by 5-bits
ii. Arithmetic Left Shift by 3-bits

Binary – 0000 1101 1111 1010 1100 1110 1011 1010 – 1M


(i) 0000 0000 0110 1111 1101 0110 0111 0101 – 0x006FD675 -1M
(ii) 0110 1111 1101 011 0111 0101 1101 0000 – 0X6FD675D0 -1M
5 10
a). Design a memory interfacing circuit for the microprocessor-controlled temperature system (MCTS). The
components listed are:
1) 74LS138 :3 to 8 decoders
2) 2732 (4K x 8): EPROM – address range should begin at 0000H and additional 4K memory space should
be available for future expansion
3) 6116 (2K x 8): CMOS R/W memory
6 3+3+2+2
a). Which is better, RISC or CISC? Justify your answer? [3M]
 Major Computer manufacturing firms Apple and Intel have always been arguing on
importance of hardware and software in CPU architecture designs.
 Intel supporters want the hardware to bear more responsibility and software on the easier
side. This would impact the hardware designing to be more complex but software coding
would be relatively easy.
 On the other hand, Apple supporters want the hardware to be simple and easy and
software to take the major role.
 Intel’s hardware oriented approach is termed as Complex Instruction Set Computer while
that of Apple is Reduced Instruction Set Computer

b). List the enhanced RISC features added to ARM processors? [3M}
 Control over ALU and shifter for every data processing operations to maximize their usage.
 Auto increment and decrement addressing modes to optimize program loops
 Load and store multiple instructions to maximize data throughput.
 Conditional execution of instruction to maximize execution throughput.

c). What type of access is provided to CPSR during Privileged and Non privileged modes? [2M]
 Processor Modes determines
 Which registers are Active
 Access Rights to CPSR Register itself
 Each Processor Mode is either
 Privileged :
• Full Read-Write access to the CPSR
 Non-Privileged :
• Only Read access to the Control Field of
CPSR but Read-Write access to the Condition Flags

d). Find the value in R3 and R5 after execution of the following instructions? [2M]
MOV R1, #0x0A
MOV R2, #0x05
ADD R3, R1, R2 – R3=0x0F
BIC R5, R1, R2 - R5=0xFA

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