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/ 332
SUBJECT CODE : 210254
As per Revised Syllobus of
SAVITRIBAI PHULE PUNE UNIVERSITY
Choice Based Credit System (CBCS)
S.E. (Computer) Semester - IV
MICROPROCESSOR
Atul P Godse
M.S, Software Systems (BITS Pilani)
B.E. Indusirial Elecironics
Formerly Lecturer in Department of Electronics Engg.
Vishwakarma Institute of Technology
Pune
Dr. Deepali A. Godse
ME., Ph.D. (Computer Engg.)
Head of Information Technology Department,
Bharati Vidyapeeth's College of Engineering for Women,
Pune
=> TECHNICAL
sens Pu Bi Thrust for Knowledge MICROPROCESSOR
Subject Code : 210254
S.E. (Computer Engineering) Semester - IV
© Copyright with Authors
All publishing rights (printed ond ebook version) reserved with Technical Publications. No part of this book
should be reproduced in ary form, Electronic, Mechanical, Photocopy or any information storage and
retrieval system without prior permission in writing, from Technical Publicotions, Pune.
Published by :
==>" TECHNICAL) “° ®22e"2% Ofc No-1, 412, Shorr Path,
Pune - 411030, M.S. INDIA, Ph.: +91-020-24495496/97,
Email: [email protected] Website : wwvw.technicalpublications.org
au
Yosis| Printers & Binders
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Ghule Industial Estate, Nanded Vilage Road,
Tal. - Haveli, Dist. - Pune - 411041
ISBN 978-81-947993-9.9
881941799399
9788194799399 (1) ay PREFACE
The importance of Microprocessor is well known in various engineering fields.
Overwhelming response to our books on various subjects inspired us to write this book.
The book is structured to cover the Rey aspects of the subject Microprocessor.
The book uses plain, lucid language to explain fundamentals of this subject. The
book provides logical method of explaining various complicated concepts and stepwise
methods to explain the important topics. Each chapter is well supported with necessary
illustrations, practical examples and solved problems. All the chapters in the book are
arranged in a proper sequence that permits each topic to build upon earlier studies. All
care has been taken to make students comfortable in understanding the basic concepts
of the subject.
Representative questions have been added at the end of each section to help the
students in picking important points from that section.
The book not only covers the entire scope of the subject but explains the philosophy
of the subject. This makes the understanding of this subject more clear and makes it
more interesting. The book will be very useful not only to the students but also to the
subject teachers. The students have to omit nothing and possibly have to cover nothing
more.
We wish to express our profound thanks to all those who helped in making this
book a reality. Much needed moral support and encouragement is provided on
numerous occasions by our whole family, We wish to thank the Publisher and the
entire team of Technical Publications who have taken immense pain to get this book
in time with quality printing
Any suggestion for the improvement of the book will be acknowledged and well
appreciated
Authors
A.D. Godse
Dr. D. A. Godse
Dedicated to Neha & Ruturaj.
ai SYLLABUS
Microprocessor - (210254)
Credit Scheme | Examination Scheme and Marks:
Mid_Semester (TH) : 30 Marks
03
End_Semester (TH) : 70 Marks
UnitI Introduction to 80386
Brief History of Intel Processors, 80386 DX Features and Architecture, Programmers Model,
Operating modes. Addressing modes and data types.
Applications Instruction Set : Data Movement Instructions, Binary Arithmetic Instructions.
Decimal Arithmetic Instructions, Logical Instructions, Control Transfer Instructions, String and
Character Transfer Instructions, Instructions for Block Structured Language, Flag Control
Instructions, Coprocessor Interface Instructions, Segment Register Instructions, Miscellaneous
Instructions, (Chapters - 1, 2)
Unit II Bus Cycles and System Architecture
Initialization ~ Processor State after Reset. Functional pin Diagram, functionality of various
ation (Memory banks). Basic memory read and wi
cycles with timing diagram.
Systems Architecture - Systems Registers (Systems flags, Memory Management registers,
Controf registers, Debug registers, Test registers), System Instructions. (Chapter - 3)
Unit III Memory Management
Global Descriptor Table, Local Descriptor Table, Interrupt Descriptor Table, GDTR, LDTR, IDTR.
Formats of Descriptors and Selector. Segment Translation, Page Translation, Combining
Segment and Page Translation. (Chapter - 4)
ww UnitIV_ Protection
Need of Protection, Overview of 80386DX Protection Mechanisms : Protection rings and levels,
Privileged Instructions. Concept of DPL. CPL. RPL. EPL. Inter privilege level transfers using Call
gates, Conforming code segment, Privilege levels and stacks. Page Level Protection, Combining
Segment and Page Level Protection. (Chapter - 5)
UnitV Multitasking and Virtual 8086 Mode
Multitasking - Task State Segment, TSS Descriptor, Task Register, Task Gate Descriptor, Task
Switching. Task Linking, Task Address Space.
Virtual Mode - Features. Memory management in Virtual Mode . Entering and leaving Virtual
mode. (Chapters- 6, 7)
Unit VI Interrupts, Exceptions, and Introduction
to Microcontrollers
Interrupts and Exceptions : Identifying Interrupts, Enabling and Disabling Interrupts, Prior
among Simultaneous Interrupts and Exceptions, Interrupt Descriptor Table (IDT), IDT
Descriptors, Interrupt Tasks and Interrupt Procedures, Error Code, and Exception Conditions.
Introduction to Microcontrollers ; Architecture of typical Microcontroller, Difference
between Microprocessor and Microcontroller, Characteristics of microcontrollers, Application
‘of Microcontrollers. (Chapters - 8. 9)
© TABLE OF CONTENTS
ee
Chapter-1 Introduction to 80386 (1-1) to (1 - 24)
1-2
1.1 Brief History of Intel Processors ..
1.2 80386Dx Features... 1-5
1,3 BO38EDX Architecture...........scssssseeersssnnnessenssnnnserseerssnnnaneeereesesene worsened = 6
1.4 Programmers Model.... 1-9
1.4.1 General Purpose / Multipurpose Registers .... fesse we 1-10
1.4.2 Special - Purpose Registers 1-11
LAB EFLAGS. 02 eee cece eee cee e eee e cette nen eeeee eens 1-41
1.4.4 Segment Registers 1-14
1.4.4.1 CS (Code Segment] and CS Register... a
1.4.4.2 DS (Data Segment) and DS Register 1-14
1.4.4.3 ES (Extra Segment) and ES Register. . re cre)
1.4.4.4 85 (Stack Segment) and SS Register. - : 4-15
14.45 FSandGS.. . 1-15
1.4.5 Segments and Offsets........ : cee : 1-15
1.5 Operating Modes
1.6 Addressing Modes.......
1.6.1 Immediate Operands ........ : cee : 1-17
1.6.2 Register Operands .........cccecceeeeseeeeeeeeeeeeeeeeeeeeeeeeee es Le 18
1.6.3 Memory Operands ............ 0005 cee eeee eee ce 1-18
1,7 Data Types
Chapter-2 Applications Instruction Set (2-1) to (2 - 58)
2.1 Introduction... 2-2
2.1.1 Data Movement Instructions 2-2
ww 2.1.2 Binary Arithmetic Instructions. ......... : ce vee te eeee eee 222
2.1.3 Decimal Arithmetic Instructions ...........00666ceeee ee seeeeeeee eee 2-2
2.1.4 Logical Instructions..........6cceee08 : sete veeeeeee ee 203
2.1.5 Control Transfer Instructions.........++ : cece veeeeeee ee 203
2.1.6 String and Character Translation Instructions ..........0060eceeee eee 2-3
2.1.7 Instructions for Block-Structured Languages ...... vee veces
2.1.8 Flag Control Instructions .........6sseeeeeveeeee seen teeeeee ee Dod
2.1.9 Coprocessor Interface Instructions ......... 0066665 cee eeeee ees 2-4
2.1.10 Segment Register Instructions. . . seeeeee 2d
2.1.11 Miscellaneous Instructions .........+ cee cee eieeeeee ee Ded
2.2 Instruction Set of 80386.
Chapter - 3 Bus Cycles and System Architecture (3 - 1) to (3 - 36)
3.1 Initialization ..
3.2 Processor State after Reset. eo . . 3-2
3.3 Functional Pin Diagram...
3.3.1 Memory/O Interface Signals... : cee 3-3
3.3.2 Interrupt Interface Signals 3-7
3.3.3 DMA Interface Signals ........ 6.0. ceeee cence ce eeeee ees 3-8
3.3.4 Coprocessor Interface Signals . : : : cere 3-8
3.4 I/O Organization ....
3.4.1 1/0 Mapped I/O.
3.4.2 Memory Mapped 1/0...
3.5 Memory Organization (Memory Banks)...
3.6 Basic Memory Read and Writes Cycles with Timing Diagram ..
3.6.1 Non-Pipelined Bus Cycles............620.020e0e200e
3.6.2 Pipelined Bus CYCleS... 2. seeccseeeeeeesseeenseeeess
3.6.3 Idle State in Pipelined Bus Cycles .
3.6.4 Bus Cycle with Wait State .....
(wi 3.6.5 Non-Pipelined Read Cycle ...........2+ vee eeeeeeeees se..3-20
3.6.6 Non-Pipelined Write Cycle...........ce ccc cece eeeeeeeeeeeeeeeeeeeee 3-22
3.6.7 Non-Pipelined Read / Write Cycles...... vevteeveeees we 3-28
3.7 Systems Architecture...
3.8 Systems Registers ...ascscsssseenseetn 3-27
3.8.1 System Flags -EFLAGS 62.0... cece ccc ee cece cee eeeeeeeeeeeeeeeeeeeees Bo 27
3.8.2 Memory-Management (System Address) Registers .........2.2.2022005 3-27
3.8.3 Control Registers. 3-27
3.8.4 Debug Registers . 3-29
3.8.5 Test Registers 2.2.26... cece eee cece cece eee eeeeeeeeeeeeeeeeeeeee 3-31
3.9 Systems Instructions ..scssssesssstsnaeissnstnenseieans -35
Un in
Chapter-4 Memory Management (4-1) to (4 - 28)
4.1 Address Translation Overview .....ccssisessescesseseisseneenneseseeseenseeis 4-2
4.2 Segment Translation
4.2.1 Selector ..
4.2.1.4 Index Part 4-3
4.2.1.2 Requester's Privilege Level (RPL) : : : 4-3
4.2.1.3 Table Indicator (TI) cee : - 2 aed
4.2.2 Global Descriptor Table (GDT) and Local Descriptor Table (LDT) ...........4-4
4.2.3 Segment Descriptor beet eeteeeees : sete eeeeee en 4-6
4.2.4 General Format of Descriptor ....... 0660s ccee ees eceeeee ee seeeeees 4-6
4.2.5 Types of Segment Descriptors and Their Formats . see eveeeeee ee 8
4.2.5.1 Non-system (Code and Data) Segment Descriptor. cee 4-8
4.2.5.2 System Segment Descriptors . : : . 4-1
4.2.6 Descriptor Tables - GDT, IDT and LOT... bette veenees seve 4-12
4.2.7 Descriptor Registers - GDTR, LOTR and IDTR : ce ce Ao 1d
4.2.7.1 Global Descriptor Table Register (GDTR) . : . 4-14
4.2.7.2 Interrupt Descriptor Table Register (/OTR) 4-15
iil) 4.2.7.3 Local Descriptor Table Register (LOTR) 4-15
4.2.8 Segment Registers and Segment Descriptor Cache... 000.2200 00eeee 4-17
4.3 Page Translation ...ssssssssssrusessesnseuneennernseeneeen 4-20
4.3.1 Page Tables 0.0... 0. ee eeeee ce : : wee A=22
4.3.2 PDE Descriptor... 006... eee cee cece eeeee ee teeeeee ee neeees 4-22
4.3.3 PTE Descriptor ......ee.eeeee wes beet eveeeees vee A 24
4.3.4Translation Lookaside Buffer/Page Translation Cache ce we A= 25
4.4 Combining Segment and Page Translation
Chapter-5 Protection (6 - 1) to (5 - 20)
5.1 Need of Protection
5-2
5.2 Overview of 80386DX Protection Mechanisms.....
5.3 Segment Level Protection.
5.3.1 Type Checking
5.3.2 Limit Checking... . 0606. cec cece eceeee ee ete eee eeee et eeeeeee eens 5-4
5.3.3 Protection Levels - Privilege Level Protection ...........000eeeeeeeeeeeee 5-4
5.3.4 Concept of DPL, CPL, RPLand EPL....... : cee SS
5.3.4.1 Restricting Access to Data 5-6
5.3.4.2 Accessing Data in Code Segments 5-7
5.3.4.3 Restricting Control Transfers 5-8
5.3.5 Changing Privilege Levels... ......ecceeeseeeeeeesereeeeeeeeeeeeee ee 5-8
5.3.5.1 Conforming Code Segment 5-8
5.3.5.2 Inter Privileged Level Transfers using Call Gates 5-9
5.3.6 Stack Switching... ....0ccc esses eeeeeeeteeeeeee ee teeeeeeeeeeeeeee S213
5.4 Page Level Protection ..
5.4.1 Restricting Addressable Domain 5-16
5.4.2 Type Checking....... 000 eee eee cece ect eeee eee eeereee eee 5916
5.5 Combining Segment and Page Level Protection.......
5.6 1/0 Protection .. 5.6.1 1/0 Privilege Level. .
5.6.2 1/0 Permission Bit Map... 0.0... 0. 06ceecc cee eeeeeeeeeeeeeeeeeee ees
5.7 Privilege and I/O Sensitive Instructions...
5.7.1 Privileged Instructions ........... 000005
5.7.2 IOPL Sensitive Instructions.
Chapter-6 Multitasking (6 - 1) to (6 - 16)
6.1 Introduction .. so ~ 2.
6.2 Task State Segment........ eee See ee eee eee 6-3
6.3 TSS Descriptor. 6-5
6-6
6.4 Task Register
6.5 Task Gate Descriptor. 6-8
6.6 Task Switching .... 16-9
6.6.1 Task Switching without Task Gate. ....... 0... 0 ccc cv eeeeeeee eee oo 6°9
6.6.2 Task Switching with Task Gate.......... Sieieesvease ee 6-11
6.7 Task Linking...
6.8 Task Address Space... 6-13
6.8.1 Task Linear-to-Physical Space Mapping ..........s000ccecseeevseeeees 6-14
6.8.2 Task Logical Address Space .........0.0c0sccceceeeeveeeeeeeseeeaee 6-15
Chapter-7 Virtual 8086 Mode (7 - 1) to (7 - 10)
7.1 Features. 7-2
7.2 Executing 8086 Code ....
7.2.1 Registers 7-3
T.22INSUCLIONS oo occ ec ce cece e esc eeeeeee ee eeseeeees estes esseeees eres D3,
7.3 Memory Management in Virtual Mode..
7.3.1 Linear Address Formation .
7.3.2 Structure Of V86 TASK... 0.0.0 eee ceee ee eeeeeeeeeneeseeeeeeeeees 7-5 7.3.3 Using Paging for V86 Tasks............+ : vive cteeeeeees e768
7.3.4 Protection within a V86 Task...... 2.6.6.0 06sec eee cence ee eee 7-6
7.4 Entering and Leaving Virtual 8086 Mode ..
7.4.1 Entering 8086 Virtual Mode. ........ 002.00 ceeeeeee este eeee es ee DT
7.4.2 Leaving 8086 Virtual Mode .... . : : coven DoT
7.5 Difference between Real, Protected and Virtual 8086 Modes.
Un
M38
Chapter-8 Interrupts and Exceptions (8 - 1) to (8 - 20)
8.1 Introduction ...........c0s000 recess * sineaetane ‘1 ateoanaa sessuneis 8-2
8.2 Identifying Interrupts... 8-3
8.3 Enabling and Disabling Interrupts. 8-4
8.3.1 NMI Masks Further NMIs........--.. 00000 ceeee eee ceee eee eee . 8-4
8.3.2 IF Masks INTR ..... eee ee . . wees 8-4
8.3.3 RF Masks Debug Faults............00c0csceeeecsseeeeeeecsseeseee ss: Bo4
8.3.4 MOV or POP to SS Masks Some Interrupts and Exceptions ......... . 8-4
8.4 Priority Among Simultaneous Interrupts and ExceptionS.....csrescenteeeerenB= 5
8.5 Interrupt Descriptor Table.......
8.6 Interrupt Tasks and Interrupt Procedures ..
8.6.1 Interrupt Procedures ............eeceeeseeeeeessseeeeeeenees
8.6.1.1 Stack of Interrupt Procedure oe : . 8-9
8.6.1.2 Trap Gate Vs Interrupt Gate... . . : a 8-9
8.6.1.3 Returning from an interrupt Procedure 8-10
8.6.2 Interrupt Tasks
8.7 Error Code.
8.8 Exception Conditions...
Chapter-9 Introduction to Microcontrollers (9 - 1) to (9 - 32)
9.1 Microcontrollers and Embedded Processors.......- w= 2
we 9.1.1 Comparison between Microprocessor and Microcontroller...........2....9°3
9.1.2 Different Types of Microcontrollers ...........2.0000ceeeeseeeeeeeees 9-4
9.1.2.1 Embedded Microcontrollers... . : - 2 94
9.1.2.2 External Memory Microcontrollers... 6... ee O58
9.1.3 Criteria for Selecting Microcontroller .....0..... 000 0cceeeeeeveeeeee ee 965
9.1.4 Applications of Microcontroller. .....s06sceeeeeereveeeeeeeeeeeeee ss 9-6
9.2 Features of 8051 Microcontroller.
9.3 Block Diagram of 8051 Microcontroller.
9.4 Register Organization of 8051 Microcontroller
9.4.1 Aand BRegisters .......66cceeeeeeeees
9.4.2 Data Pointer (DPTR)
9.4.3 Program Counter ..
9.4.4 8051 Flag Bits/PSW Registers
9.4.5 Special Function Registers ........0..00cccccsseeeeeeeereseeeeeees
9.4.6 Stack and Stack Pointer
9.5 Pin Diagram of 8051
9.6 Memory Organization.
9.6.1 Internal RAM Organization ..... vee cece tieeeeeeeeeeeeeee 9219
96.1.1 8051 Register Banks (Working Registers) . . . 9-20
9.6.1.2 Bit /Byte Addressable... . cee - 9-21
9.6.1.3 General Purpose RAM... . « sae ee O21
9.6.2 ROM Space in the 8051 ........ ce bette veeteeeeeeeeeeee 9°21
9,7 External Memory Interfacing...
9.7.1 External Program Memory.
9.7.2 External Data Memory.
9.7.3 Accessing External Data Memory in 8051C ........ 000.02. .0 cece eee 9°26
Microprocessor Laboratory (L- 1) to (L- 62)
Solved SPPU Question Papers (S- 1) to (S- 10)
Solved Model Question Papers (S- 11) to (S- 14)
(x UNIT - I
| 1 | Introduction to 80386
Syllabus
Brief History of Intel Processors, 80386 DX Features and Architecture, Programmers Model,
Operating modes, Addressing modes and data types.
Contents
1.1. Brief History of Intel Processors
1.2 80386DX Features . . May-10,13,
1.3. 80386DX Architecture May-2000,06,11,12,13,
: - Dec.-05,11,13, Nov.-12,
1.4 Programmers Model Dec.-03, 14,19,
- May-10,13,19,
1.5. Operating Modes
1.6 Addressing Modes . . Dec.-14,17, May-18,
1.7 Data Types May-14,19, -
a-n ‘Microprocessor 1-2 Introduction to 80386
Brief History of Intel Processors
* The world’s first microprocessor, the Intel 4004, was a 4bit microprocessor.
(A bit is a binary digit with a value zero or one and 4-bit microprocessor
means the microprocessor can process 4-bit word in one cycle. It has 12-bit
address lines to access 4096 4-bit wide memory locations. The 4004 microprocessor
has only 45 instructions.
* The Intel released the 4040, as updated version of 4004 with enhancement in
speed, and without any improvement in word length and memory size.
* In 1972 announced the 8008, 8-bit and faster version of 4004. This version came up
with expanded memory size upto 16 kbytes and additional instructions to make
total of 48 instructions. (A byte is 8-bit binary number and a K is 1024).
* In 1974 Intel came out with 8080 was a considerable improvement over its
predecessors.
© The 8080 had a much larger instruction set and since NMOS technology used, it is
much faster than 8008.
* In 1977, Intel introduced updated version of 8080-8085.
© The Table 1.1.1 shows the improvement of 8080 over 8008 and 8085 over 8080.
Parameter Processor
8008 8080 8085
Speed Requires 20 us for Requires 2 ps for Requires 1.3 us for
execution one execution one execution of one
instruction instruction instruction
(10 times faster)
Memory size 16 kbytes 64 kbytes 64 kbytes.
(4 times more)
TTL compatibility Not directly compatible | Compatible Compatible
Interfacing, More costly and Easier and less More easier and less
complex expensive expensive as it contains
internal clock generator
and internal system
controller
Table 1.1.1
* The next generation was 8086 processor, a 16-bit processor, with advanced
architecture and instruction set. At the same time Intel introduced processor 8088.
The 8088 is an 8bit version of the 8086 which has fewer data lines but retains all
of the processing features of the 8086. The programs that run on 8088 will also
run, without modification on the 8086. The 8086/88 pair were the first members of
TECHNICAL PUBLICATIONS® - An up thrust for knowledge Microprocessor 1-3 Introduction to 80386
iAPX 86, family of microprocessors. This pair has 20 address lines to address upto
1 Mbyte of memory (1 Mbyte = 1024 kbyte) and also supported with 4 or 6 byte
instruction queue to implement pipelining feature. (Feature of fetching the next
instruction while the current instruction is executing is called pipelining). This pair
belongs to CISC (complex instruction set computers) because of the number and
complexity of instructions
* In 1983 the next version was announced, the 80186/88 very similar to 8086/8088
pair. The 80186/88 included many useful peripheral 1/O functions as an integral
part of the microprocessor. The improved instruction set of 80186/88 supports
these peripheral 1/O functions. Although the 80186 provided increased
functionality, it maintained compatibility with the 8086, ensuring that it could
execute 8086 programs.
* After 80186/88, Intel has announced 80286, which is 16-bit processor like 8086. The
80286 was the first family member designed specifically for use as a CPU in a
multi-user microcomputer. It contains many advanced modes of operations not
supported by 8086, The 80286 boosted a new mode of operation-protected mode.
Due to this the entire concept of memory segmentation was changed. The virtual
memory management circuitry were included in the 80286, which allow an 80286
to operate in either real address mode or protected virtual address mode.
* In 1986, the next advanced processor, the 80386DX, was introduced. As expected,
80386DX is faster than any of its predecessors, with a minimum operating
frequency of 16 MHz. It is an 32-bit processor with 32-bit register set, address bus
and data bus.
Internal Chip —_Introduction Data bus Address bus Number of
cache instructions executed
memory per second
- 4008 a7 4 5 50000
= 008 1972 8 8 0000
- 8080 1974 8 16 500000,
- 8085 1977 8 16 769230
- 8086/88 1978 16/8 20 2.5 million
- 80186/188 1982, 16/8 20
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-4 Introduction to 80386
. 80286 1983, 16 24 4.0 million
- 80386DX 1986 22 32 25 million
80386SX 1988, 16 24 25 million
8K 80486DX 1989, 32. 2 50 million,
(With
coprocessor)
8K 804865X 1989 32. 2 50 million,
(Without
coprocessor)
Table 1.1.2 80X86 family tree
During 1988, an “economy version” of the 80386, called the 80386SX was introduced
by Intel. This processor had the same outside connections as the 80286, but inside it was
a 386-processor supporting the 386’s expanded instruction set and various operating
modes. The Table 1.1.2 shows the 80X86 family tree.
Early in 1989, Intel introduced the 80486DX, the more highly integrated
microprocessor with built-in coprocessor. Meanwhile, Intel has also developed step-down
version 80486SX (without coprocessor and lower clock speed).
‘The Pentium, introduced in 1993, was similar to the 80386 and 80486 microprocessors.
It contained larger internal cache and data bus width is extended to 64-bit,
The Table 1.1.3 shows the comparison between various pentium processors.
Processor Released Databus Memory Licache 12 Bus
year width size Data-Code cache transfer
speed
Pentium 60 MHz 1993 ot 4GByte = 8K-8K = = ~— 60-66 MHz
66 MHz
120 MHz
133 MHz
233 MHz
Pentium Pro 1995 ot 64 GByte = 8K-8K 256K 60-66 MHz
150-166 MHz
Pentium 11350MHz 1997 ot 64GByte 16K-16K 512K 100 MHz
400 MHz.
450 MHz
Pentium It Xeon 1998 ot 64 GByte 16K-16K 512K or 100 MHz
1M
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-5 Introduction to 80386
Pentium IIT 1 GHz 1998 ct 64GByte 16K-16K 512K 100 MHz
Slot 1 version
Pentium Il 1 GHz 1998 oF 64GByte 16K-16K 256K 100 MHz
Flip chip version
Pentium III 1 GHz. 1998 6 64 GByte 16K-16K 256K 66 MH.
Celeron
Pentium 1V13GHz 2000 ot 64.GByte 16K-16K 256K 100 MHz
1.4 GHz
1.5 GHz
Table 1.1.3 Comparison between pentium processors
Pentium IV uses the RAMBUS memory technology in place of SDRAM technology
used in other pentium processors.
ROCA)
1. Explain in brief history of Intel Processors.
2. Give comparison between 8008, 8080 and 8085 Processors,
3. Give comparison between various Intel Processors.
EE] 80326Dx Features
‘The 80386 processor is available in two different versions, the 80386DX and the
80386SX. The 80386DX has 32-bit address bus and a 32-bit data bus. However, 80386SX
has only 24-bit address bus and a 16-bit data bus.
1. The 80386DX is a 32-bit processor. The 32-bit ALU allows to process 32-bit data.
2. It has 32-bit address bus. So it can access up to 4 Gbyte (2° ) physical memory or
64 terabyte (2"°) of virtual memory.
stru
3. The 80386DX runs with speed up to 20 MH: ms per second.
4, The pipelined architecture of the 80386DX, allows simultaneous instruction fetching,
decoding, execution and memory management. Instruction pipelining, a high bus
bandwidth and on-chip address translation significantly shorten the average
instruction execution time of 80386DX. These architectural design features enable
the 80386DX to execute 3 to 4 million instructions per second.
5. It allows programmers to switch between different operating systems such as
PC-DOS and UNIX.
6. It can operate on 17 different data types.
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-6 Introduction to 80386
7. It has built-in virtual memory management circuitry and protection circuitry
required to operate an 80386DX in these modes.
8. The 80386DX can operate in real mode, protected mode or a variation of protected
mode called virtual 8086 mode. In real mode it functions basically as a fast 8086 or
real_ mode 80286. The protection mode operation provides paging, virtual
addressing, multilevel protection and multitasking and debugging capabilities.
9. The 80386DX microprocessor is compatible with their earlier 8086, 8088, 80186,
80188 and 80286 chips, Virtually anything that runs under these microprocessors
will also run under the 80386.
ROUCuAC TC)
1. List the features of 80386DX.
EE] 80386Dx Architecture
‘The Internal Architecture of 80386DX is divided into 3 sections :
* Central Processing Unit (CPU)
= Execution unit
= Instruction decode unit
* Memory Management Unit (MMU)
= Segmentation unit
= Paging unit
* Bus Control Unit
The central processing unit is further divided into execution unit and instruction unit.
The Memory management unit consists of a segmentation unit and a paging unit. These
units operate in parallel. Fetching, decoding, execution, memory management and bus
accesses for several instructions are performed simultaneously. This parallel operation is
called pipelined instructions processing.
Execution U
‘The execution unit reads the instruction from the instruction queue and executes the
instructions. It consists of three subunits : Control unit, data unit and protection test
unit.
4. Control unit: It contains microcode and special hardware. The microcode and
special hardware allows 80386DX to reduce time required for execution of multiply and
divide instructions. It also speeds the effective address calculation.
2. Data unit: The data unit contains the ALU, eight 32-bit general purpose registers
and a 64-bit barrel shifter. The barrel shifter is used for multiple bit shifts in one clock.
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-7 Introduction to 80386
Thus it increases the speed of all shift and rotate operations. The multiply/divide logic
implements the bit-shift-rotate algorithms to complete the operations in minimum time.
The entire data unit is responsible for data operations requested by the control unit.
3. Protection test unit: The protection test unit checks for segmentation violations
under the control of the microcode.
Instruction Decode Unit
The instruction decode unit takes instruction bytes from the code prefetch queue and
translates them into microcode. The decoded instructions are then stored in the
instruction queue. They are passed to the control section for deriving the necessary
control signals.
Segmentation Unit
The segmentation unit translates logical addresses into linear addresses at the
request of the execution unit, The segmentation unit compares the effective address for
the length limit specified in the segment descriptor. The segment unit adds the segment
base and the effective address to generate linear address. Before calculation of linear
address it also checks for access rights. It provides a 4 level protection mechanism for
protecting and isolating the system code and data from those of the application
program.
Paging Unit
When the 80386DX paging mechanism is enabled, the paging unit translates linear
addresses generated by the segmentation unit or the code prefetch unit into physical
addresses. If paging, unit is not enabled, the physical address is the same as the linear
address, and no translation is necessary. The paging unit gives physical address to the
Bus Interface Unit to perform memory and 1/O accesses. It organizes the physical
memory in terms of pages of 4 kbytes size each.
The control and attribute PLA checks the privileges at the page level. Each of the
pages maintains the paging information of the task. The limit and attribute PLA checks
segment limits and attributes at segment level to avoid invalid accesses to code and data
in the memory segments.
Bus Control Unit
The Bus Control Unit is the 80386DX’s communication with the outside world. It
provides a full 32-bit bi-directional data bus and 32-bit address bus. The bus control unit
is responsible for following operations :
1. It accepts internal requests for code fetch and for data transfers from the code fetch
unit and from the execution unit. It then prioritize the request with the help of
prioritizer and generates signals to perform bus cycles.
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Introduction to 80386
Microprocessor
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Fig. 1.3.1 80386DX architecture
, data and control signals to communicate with memory and I/O
devices. The address driver drives the bus enable and address signal Ag - Aj)
TECHNICAL PUBLICATIONS® - An up thrust for knowledge
and the transreceiver interface the internal data bus with the system bus.
2. It sends addres Microprocessor 1-9 Introduction to 80386
3. It controls the interface to external bus masters and coprocessors.
4. It also provides the address relocation facility.
Instruction Prefetch Unit
The instruction prefetch unit fetches sequentially the instruction byte stream from the
memory. It uses bus control unit to fetch instruction bytes when the bus control unit is
not performing bus cycles to execute an instruction. These prefetched instruction bytes
are stored in the 16-byte code queue. A 16-byte code queue holds these instructions until
the decoder needs them. The prefetcher always fetches instructions in the order in which
they appear in the memory. In fact, the prefetcher simply reads code one double word
at a time, not caring whether it’s bringing in complete instructions or pieces of two
When jump or call instructions are executed, the contents
of the prefetched and decode queues are cleared out. In this case, prefetcher again starts
filling up its queue.
instructions with each acct
Instruction Predecode Unit
The instruction predecode unit takes instruction bytes from the instruction prefetch
queue and translates them into microcode. The decoded instructions are then stored in
the instruction queue.
ROA)
1. Drmw the functional block diagram of 80386DX and explain the main functional units.
Explain the function of central processing unit of 80386DX.
Explain the function of memory management unit of 80386DX.
What is the necessity of prefetch quewe ? SSE
5. What is BIU in 80386 processor ? What are the functions of BIL ?
Sasa
6. How does queue work in JUMP and CALL instruction execution ?
SU See
Draw the functional block diagram of 80386DX and explain the main functional nits
aos eed
EE Programmers Model SPPU ; Dec.-03,14,19, May-10,13,19
+ The programming model of the 80386DX considered to be program visible because
its registers are used during application programming and are specified by the
instructions. Other registers, are considered to be program invisible because they
TECHNICAL PUBLICATIONS® « An up thrust for knowledge ‘Microprocessor 1-10 Introduction to 80386
are not addressable directly during 31 80386DX 9
applications programming, but may «EP [Ee
be used indirectly during system
programming. Some of them are
used to control and operate the
protected memory system
cs
Ds
ss
ES
FS
Fig. 1.4.1 illustrates the programming, 6s
model of the 80386DX. 31 ‘57 °
EAX aX
Tt consists of EBX BX
ECX cx
= General purpose / Multi-purpose EDX Dx
registers 3t 18 0
ESP SP
= Special purpose registers ESP BP
a ESI SI
= EFLAGS register EDI DI
= Segment registers 31 0
crass
Fig. 1.4.1 80386 register set
General Purpose / Multipurpose Registers
EAX (accumulator) : EAX is referenced as a 32-bit register (EAX), as a 16-bit
register (AX), or as either of two 8-bit registers (AH and AL). Note that if an 8- or
16-bit register is addressed, only that portion of the 32-bit register changes without
affecting the remaining bits. The accumulator is used for instructions such as
multiplication, division, and some of the adjustment instructions. For these
instructions, the accumulator has a special purpose, but is generally considered to
be a multipurpose register. The EAX register may also hold the offset address of a
location in the memory system
EBX (base index) : EBX is addressable as EBX, BX, BH, or BL. The BX register
sometimes holds the offset address of a location in the memory system. The EBX
also can address memory data.
ECX (count) : ECX is a general-purpose register that also holds the count for
various instructions, The ECX register also can hold the offset address of memory
data. Instructions that use a count are the repeated string instructions
(REP/REPE/REPNE); and shift, rotate, and LOOP/LOOPD instructions. The shift
and rotate instructions use CL as the count, the repeated string instructions use
CX, and the LOOP/LOOPD instructions use either CX or ECX.
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-11 Introduction to 80386
* EDX (data) : EDX is a general-purpose register that also holds a part of the result
from a multiplication or part of the dividend before a division. This register can
also address memory data.
+ EBP (base pointer) : EBP points to a memory location for memory data transfers.
‘This register is addressed as either BP or EBP.
* EDI (destination index) : EDI often addresses string destination data for the string
instructions. It also functions as either a 32-bit (EDI) or 16-bit (DI) general-purpose
register.
* ESI (source index) : ESI is used as either ESI or SI. The source index register often
addresses source string data for the string instructions. Like EDI, ESI also
functions as a general-purpose register. As a 16-bit register, it is addressed as SI;
as a 32-bit register, it is addressed as ESI
Special - Purpose Registers
© The special-purpose registers include EIP, ESP, EFLAGS; and the segment registers
CS, DS, ES, $8, FS, and GS,
+ EIP (instruction pointer) : EIP addresses the next instruction in a section of
memory defined as a code segment. This register is IP (16 bits) when the
microprocessor operates in the real mode and EIP (32 bits) when the 80386 operate
in the protected mode. The instruction pointer, which points to the next instruction
in a program, is used by the microprocessor to find the next sequential instruction
in a program located within the code segment. The instruction pointer can be
modified with a jump or a call instruction.
+ ESP (stack pointer) : ESP addresses an area of memory called the stack. ‘The stack
memory stores data through this pointer. This register is referred to as SP if used
as a 16-hit register and ESP if referred to as a 32-bit register.
EFLAGS
A Flag is a flip-flop which indicates some condition produced by the execution of an
instruction or controls certain operations of the EU. The EFLAG register contains thirteen
flags. Fig 1.4.2 shows the bit pattern of the EFLAG register.
‘These flags can be categorized in three different groups.
4. Status flags : These flags reflect the state of a particular program.
2. Control flags : These flags directly affect the operation of few instructions.
3, System flags : These flags reflect the current status of the machine and which are
usually used by operating system than by application programs.
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-12 Introduction to 80386
= mu 7
(7) vm CF (0)
(16) RF PF Q)
(1) NT AF (a)
a:
(12,43) (op, ——— ZF)
(11) OF ‘SF (7)
(10) OF TF)
IF (9)
Be reserves New flags
Fig, 1.4.2 Bit pattern of EFLAG register
Status Flags: The status flags are : CF (Carry Flag), PF (Parity Flag ), AF (Auxiliary
carry Flag), ZF (Zero Flag), SF (Sign Flag), and OF (Overflow Flag). These flags indicate
some condition produced by the execution of arithmetic or logical instructions. These
flags provide necessary information for arithmetic and logical control decisions.
CF (Carry flag) : This bit is set by arithmetic instructions that generate either a carry or
a borrow. This bit can also be set, cleared, or inverted with the STC, CLC or CMC
instructions, respectively. Carry flag is also used in shift and rotate instructions to
contain the bit shifted or rotated out of the register.
PF (Parity flag) : ‘The parity bit is set by most instructions if the least significant 8-bit
of the result contain even number of one’s,
AF (Auxiliary carry flag) : This bit is set when there is a carry or borrow after a nibble
addition or subtraction, respectively. The programmer can’t access this bit directly, but
this bit is internally used for BCD arithmetic.
ZF (Zero flag) : Zero flag is set to 1, if the result of an operation is zero.
SF (Sign flag) : The signed numbers are represented by combination of sign and
magnitude. The Most Significant Bit (MSB) indicates sign of the number. For negative
number MSB is 1. Sign flag is set to 1, if the result of an operation is negative (MSB = 1).
OF (Overflow flag) : In 2's complemented arithmetic,
most significant bit is used to represent sign and
remaining bits are used to represent magnitude of a
< Magnitude
number (see Fig. 1.4.3). This flag is set if the result of a ., . is
Fig. 1.4.3 Sign and magnitude
signed operation is too large to fit in the number of bits representation
available (7-bits for 8-bit number) to represent it.
For example, if you add the 8-bit signed number 01110110 (+118 decimal) and the
8-bit signed number 00110110 (+54 decimal). The result will be 10101100 (+172 decimal),
5 ——~—
TECHNICAL PUBLICATIONS® - An up thrust for knowledge Microprocessor 1-13 Introduction to 80386
which is correct binary result. But in this case, it is too large to fit in the 7-bits allowed
for the magnitude in an 8-bit signed number. The overflow flag will be set after this
operation to indicate that the result of the addition has overflowed into the sign bit.
Control Flags
DF ( Direction flag) : The direction flag controls the direction of string operations.
When the D flag is cleared these operations process strings from low memory up
towards high memory. This means that offset pointers (usually SI and DI) are
incremented by 1 after each operation in the string instructions when D flag is cleared. If
the D flag is set, then SI and DI are decremented by 1 after each operation to process
strings from high to low memory.
System Flags
VM (Virtual Memory) flag : This flag indicates operating mode of 80386. When VM
flag is set, 80386 switches from protected mode to virtual 8086 mode.
R (Resume) flag/Restart flag : This flag, when set allows selective masking of some
exceptions at the time of debugging.
NT (Nested flag): This flag is set when one system task invokes another task.
(ie. nested task).
IOPL (UO Privilege level) : The two bits in the IOPL are used by the processor and the
operating system to determine your application’s access to I/O facilities. It holds
privilege level, from 0 to 3, at which the current code is running in order to execute any
1/O related instruction.
IF (Interrupt Flag): When interrupt flag is set, the 80386 recognizes and handles
external hardware interrupts on its INTR pin. If the interrupt flag is cleared, 80386
ignores any inputs on this pin, The IF flag is set and cleared with the STI and CLI
instructions, respectively.
TF (Trap Flag): Trap flag allows user to single-step through programs. When an
80386 detects that this flag is set, it executes one instruction and then automatically
generates an internal exception 1. After servicing the exception, the processor executes
the next instruction and repeats the process. This single stepping continues until
program code resets this flag for debugging programs single step facility is used.
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-14 Introduction to 80386
Segment Registers
‘The 80386 has a 1 Mbyte address gi 15 Bito
space in real mode, But all of this. ———————
memory cannot be active at one CS Code segment
time. The 80386 supports _ six Ds Data segment
simultaneously accessible _ memory ss Stack segment
blocks called segments. ES Extra segment
A segment represents an Be Extra segment
Gs Extra segment
independently accessible block of
memory consisting of 64K Fig, 1.4.4 Segment registers
consecutive byte-wide storage
locations. These segments are addressed by 16-bit registers : CS, DS, ES, $5, FS
and GS. These registers are called segment registers, generate memory addresses
when combined with other registers in the microprocessor.
A segment register functions differently in the real mode when compared to the
protected mode operation of the 80386DX.
Fig. 1.4.4 shows the segment registers.
CS (Code Segment) and CS Register
The code segment is a section of memory that holds the code (programs and
procedures) used by the 80386DX.
The CS (Code Segment) register defines the starting address of the section of
memory holding currently active code segment.
In real mode operation, it defines the start of a 64K-byte section of memory; in
protected mode, it selects a descriptor that describes the starting address and
length of a section of memory holding code.
‘The code segment is limited to 4G bytes in the 80386 when it operates in the
protected mode
F] Ds (Data Segment) and DS Register
‘The data segment is a section of memory that contains most data used by a
program. Data are accessed in the data segment by an offset address or the
contents of other registers that hold the offset address.
The DS (Data Segment) register is used to hold the address of currently active
data segment,
‘The data segment is limited to 4G bytes in the 80386 when it operates in the
protected mode.
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-15 Introduction to 80386
EE] Es (Extra Segment) and ES Register
* The extra segment is an additional data segment that is used by some of the string
instructions to hold destination data.
* The ES (Extra Segment) is used as general data segment register. This register
holds the base addresses of memory segment.
EV] Ss (Stack Segment) and SS Register
© The stack segment defines the area of memory used for the stack. The stack entry
point is determined by the stack segment and stack pointer registers. The BP
register also addresses data within the stack segment.
OF] Fs and cs
* ‘The FS and GS segments are supplemental segment registers,
* The FS, and GS registers are used as general data segment registers. These
registers hold the base addresses of two different memory segments. These
segments are referred as to Extra Segments.
Segments and Offsets
* A combination of a segment address and an offset address, access a memory
location in the real mode. All real mode memory addresses must consist of a
segment address plus an offset address. This is illustrated in Fig. 1.4.5.
19 43 0
Base [ 16-bitsegment selector | 0000
+ 19 1615 0
offset | 0000 | 16-biteffective address
2019 0
Linear address
Fig. 1.4.5 Memory addressing in real mode
* ‘The segment address, located within one of the segment registers, defines the
beginning address of any 64K-byte memory segment. The offset address selects
any location within the 64K byte memory segment. Segments in the real mode
always have a length of 64K bytes.
* Table 1.4.1 and 1.4.2 show the default 16-bit and 32-bit segment and offset address
combinations, respectively.
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Segment Offset Special Purpose
cs. P Instruction address
ss SP or BP Stack address
DS BX, DI, SL, an 8-bit number Data address
or a 16-bit number
ES DI for string instructions String destination address
Table 1.4.1 Default 16-bit segment and offset address combinations
Segme Offset Special Purpose
nt
cs EP Instruction address
$8, ESP or EBP Stack address
Ds EBX, EDI, ESI, EAX, Data address
EC, EDX an 8:bit
number or a 32-bit
number
ES EDI for string String destination
instructions address
FS No default General address
cs No default General address
Table 1.4.2 Default 32-bit segment and offset address combinations
GOVEA USEC)
Draw and explain the programme
‘s model of 80386DX.
List the different registers in 80386.
Describe 80386 flag register with significance of each and every bit in detail.
SPPU : Dec.-03,14, May-10,13, Marks 6
Explain the function of segments and segment registers of 80386.
Describe following different flags defined in 80386 processor
a) DE b) VM o) NT d) RF Sa
Oe
With the help of dingram explain 80386 applications register se.
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-17 Introduction to 80386
EEA Operating Modes
* The operating mode of the 80386 also determines the features that are access
‘The 80386 has three operating modes :
= Real-Address Mode
= Protected Mode.
= Virtual 8086 (V86) Mode
* Real-address mode (often called just “real mode") is the mode of the processor
immediately after RESET. In real mode the 80386 appears to programmers as a
fast 8086 with some new instructions. Most applications of the 80386 will use real
mode for initialization only.
* Protected mode is the natural 32-bit environment of the 80386 processor. In this
mode all instructions and features are available.
* Virtual 8086 mode (also called V86 mode) is a dynamic mode in the sense that the
Processor can switch repeatedly and rapidly between VS6 mode and protected
mode, The CPU enters V86 mode from protected mode to execute an 8086
program, then leaves V86 mode and enters protected mode to continue executing
a native 80386 program.
ROCA tC)
1. Write a short note on operating modes of 80386DX processor.
EES Addressing Modes
To
4,17, May-18
As a part of programming flexibility, processor provides different ways to access
these operands from different locations. The different ways by which processor can
access data are referred to as addressing modes.
The 80386DX provides a total of 11 addressing modes for instructions to specify
operands. These addressing modes can be categorized in three group:
+ Register operand addressing
* Immediate operand addressing
* Memory operand addressing.
Immediate Operands
Certain instructions use data from the instruction itself as operands. Such an operand
is called an immediate operand. The operand may be 32-, 16-, or &-bits long.
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-18 Introduction to 80386
Example :
For 8-bit operand : MOV AL, 20H : This instruction copies 20H in the lower byte of
BAX register.
For 16-bit operand : MOV AX, 1020 H : This instruction copies 1020H in the lower
word of EAX register
For 32-bit operand: MOV EAX, 10B89C20H : This instruction copies 10B89C20H in
the EAX register.
Register Operands
Operands may be located in one of the 32-bit general registers (EAX, EBX, ECX, EDX,
ESI, EDI, ESP, or EBP), in one of the 16-bit general registers (AX, BX, CX, DX, SI, DI, SP,
or BP), or in one of the 8-bit general registers (AH, BH, CH, DH, AL, BL, CL, or DL).
Examples :
For 8-bit operand :_ MOV AL, DL : This instruction copies the lower byte contents of
the EDX register to the lower byte of the EAX register. Both source and destination
operands are the internal registers of 80386DX.
For 16-bit operand : MOV AX, DX This instruction copies the lower word contents
of EDX register to the lower word of the EAX register.
For 32-bit operand : MOV EAX, EDX : This instruction copies the contents of EDX
register to the EAX register.
Memory Operands
The remaining 9 addressing modes provide a mechanism for specifying the physical
address of an operand. In 80386DX, physical address is calculated before any read or
write operation
‘The physical address consists of two components : The segment base address and
an effective address. The effective address can be specified in a variety of ways. One
way is to encode the effective address of the operand directly in the instruction. This
represents direct addressing mode. The effective address can be generated with the
combinations of four addressing elements : Base, Index, Scale factor and Displacement.
where,
Base : The contents of any general purpose register.
Index: The contents of any general purpose register. The index registers are used to
access the elements of an array, or a string of characters.
TECHNICAL PUBLICATIONS® « An up thrust for knowledge Microprocessor 1-19 Introduction to 80386
Scale : The index register’s value can be multiplied by a scale factor either 1, 2, 4 or 8.
Scaled index mode is especially useful for accessing arrays or structures.
Displacement : An 8, 16 or 32-bit immediate value following the instruction.
‘The general formula for generating effective address is given as follows
EA = Base + (Index x Sealing factor) + Displacement
The Fig. 1.6.1 shows the registers that can be used to hold the values of segment
base, base, and index.
Physical Address = Segment Base Address + Effective Address
(PA) = SBA +EA
'A : [Base + (Index x Scale factor ) + Displacement }
cs aX A 1
Bx Bx
ss cx 2 8,16 or
Ds Dx ox 32-bit
pases bid Sh bs | Ox) xd |b] +
