Computer Organization

(CE-313)

Lecture – 11

Dr. Tassadaq Nawaz

Dept. of Computer Engineering
King Faisal University
Al Ahsa Saudi Arabia.

1
 In Today's Lecture ...

◼ Timing and Control

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3
 Timing and Control

◼ The timing for all the registers in the basic

computer is controlled by a master clock
generator.

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5
 Timing and Control

Clock Pulse
Generator

Flip Flops in the Registers in the Flip Flops and

System System Registers
available in the
Control Unit

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 Timing and Control

◼ The clock pulses do not change the state of a

register unless the register is enabled by a
control unit.
◼ The control signals are generated in the control
unit and provide control inputs for the
➢ multiplexers in the common bus,

➢ control inputs in processor registers,

➢ and microoperations for the accumulator.

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 Timing and Control

◼ There are two types of control organizations

Hardwired Control Microprogrammed

Control

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 Timing and Control

Hardwired Control
The control logic is implemented with gates, flip-flops,
decoders, and other digital circuits,
◼ Advantage:
◼ It can be optimized to produce a fast mode of operation
◼ Disadvantage:
◼ Requires changes in wiring among various components if the
design has to be modified or changed

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 Timing and Control

Microprogramed Control:
◼ The control information is stored in a control
memory, and the control memory is programmed to
initiate the required sequence of microoperations.
◼ Advantage:Any required changes or modifications
can be done by updating the microprogram in control
memory
◼ Disadvantage: Slower than hardwired because of
the need of control memory access
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Control Unit
HardWired:
➢ Control logic gates
➢ 3 × 8 decoder
➢ Instruction register
➢ 4 × 16 decoder
➢ 4-bit sequence
counter.

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Function of
Decoder

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 Timing and Control

◼ An instruction is read from memory and is

placed in instruction register (IR).
◼ A 3 × 8 decoder is used to decode the Opcode
bits 12-14 into signals D0, ..., D7.
◼ Bit 15 of instruction is transferred to flip-flop
designated by flip-flop designated by symbol I

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 Timing and Control

◼ Bit 0-11 are applied to control logic gates

◼ The 4-bit sequence counter (SC) can count in
binary from 0-15.
◼ The output of SC are decoded into 16 timing
signals T0 through T15
◼ The counter can be cleared to 0, causing the
next active timing signal to be T0.

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 Timing and Control

◼ Most of the time, the counter is incremented to

provide the sequence of timing signals out of
4x16 decoder.
◼ Once a while, the counter is cleared to zero,
causing the next time signal to T0
◼ For example consider the case where SC is
incremented to provide timing signals T0, T1, T2,
T3, T4 in sequence
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 Timing and Control

◼ At the time T4, SC is cleared to 0 if the decoder

output D3 is active.
◼ This can be expressed symbolically by the
statement:
SC ← 0
◼ The figure 5-7 shows the timing diagram of
time relationship of control signals

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Timing and Control

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 Timing and Control

◼ The sequence counter SC responds to the

positive transition of the clock
◼ Initially, CLR input of SC is active.
◼ The first positive transition of the clock clears
the SC to zero, which in turn activates the timing
signal T0 out of the decoder.
◼ T0 is active during the one clock pulse

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 Timing and Control

◼ The positive clock transition labeled T0 in the

diagram will trigger only those registers whose
control inputs are connected to the timing signal
T0
◼ SC is incremented with every positive clock
transition unless its clear input is active.
◼ This produces the sequence of timing signals T0,
T1, T2, T3, T4 and so on as shown in diagram
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 Timing and Control

◼ Now if SC is not cleared, the timing signals will

continue with T5, T6, T7, T8 upto T15 and back
to T0
◼ The last three waveforms in Figure 5-7 show
how SC is cleared when D3T4 = 1

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Timing and Control

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 Timing and Control

◼ When timing signal T4 become active, the input

of AND gate which implants the control
function D3T4 becomes active.
◼ This signal is applied to the CLR input of SC
◼ On the next positive clock-transition (The one
marked in T4 in the diagram) the counter is
cleared to zero.
◼ This causes timing signal T0 to become active
instead of T5 22
 Timing and Control

◼ A memory read or write cycle will be initiated

with the rising edge of timing signal
◼ Let us assume that a memory cycle time is less
than the clock cycle time
◼ According to this assumption, a memory read or
write cycle initated by timing signal will be
completed by the time the next clock goes
though its positive transition .
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 Timing and Control

◼ The clock transition will then be used to load

the memory word into a register.
◼ This timing relationship is not valid in many
computers because the memory cycle time is
usually larger than the processor clock-cycle
◼ In such cases it is necessary to provide wait
cycles in the processor until the memory word is
available
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 Timing and Control

◼ To fully comprehend the operation of the

computer, it is crucial that one understand the
timing relationship between the clock-transition
and the timing signals.
◼ For example the register transfer statement
T0: AR ← PC
◼ Specifies transfer of contents of PC into AR
when the timing signal T0 is active
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 Timing and Control

◼ T0 is active during an entire clock cycle interval

◼ During this time the content of the PC is placed
onto the bus (S2S1S0=010) and the LD input of
AR is enabled.
◼ The actual transfer does not occur until the end
of clock cycle when the clock goes through
positive transition

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 Timing and Control

◼ The same positive clock transition increments

the sequence counter SC from 0000 to 0001
◼ The next clock cycle has T1 active and T0
inactive

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Computer Organization
(CE-313)

Lecture – 12

Dr. Tassadaq Nawaz

Dept. of Computer Engineering
King Faisal University
Al Ahsa Saudi Arabia.

28
 In Today's Lecture ...

◼ Instruction Cycle
◼ Fetch and Decode
◼ Determine the type of instruction

◼ Register reference instructions

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 Instruction Cycle

◼ A program is executed in the computer by going

through a cycle for each instruction.
◼ In the basic computer each instruction cycle
consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the
instruction has an indirect address.
4. Execute the instruction. 30
 Instruction Cycle

◼ After step 4, the control goes back to step 1 to

execute the next instruction. This process
continues until a HALT instruction is
encountered.
◼ The fetch & decode phases of the instruction
cycle consists of the following microoperations
synchronized with the timing signals (clocking
principle).
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 Instruction Cycle

Fetch and Decode:

◼ Initially, the PC register is loaded with the
address of the first instruction in the program.
◼ The sequence counter SC is cleared to 0,
providing a timing signal T0.
◼ After each clock pulse , SC is incremented by
one so that timing signals go through a sequence
T0, T1, T2, and so on.
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 Instruction Cycle

◼ The microoperations for the fetch and decode

phases can be specified by the following register
transfer statements:

T0: AR  PC
T1: IR M[AR], PC  PC + 1
T2: D0, ..., D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

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 Instruction Cycle

◼ T0: Since only AR is connected to the address

inputs of memory, the address of instruction is
transferred from PC to AR.
1. Place the content of PC onto the bus by making the
bus selection inputs S2S1S0 = 010.
2. Transfer the content of the bus to AR by enabling
the LD input of AR (AR  PC).

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S2S1S0=010

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 Instruction Cycle

◼ T1: The instruction read from memory is then

placed in the instruction register IR. At the same
time, PC is incremented to prepare for the
address of the next instruction.

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S2S1S0=111

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 Instruction Cycle
1. Enable the read input of the memory.
2. Place the content of memory onto the bus by
making the bus selection inputs S2S1S0 = 111. (Note
that the address lines are always connected to AR,
and we have already placed the next instruction
address in AR.)
3. Transfer the content of the bus to IR by enabling
the LD input of IR (IR  M[AR]).
4. Increment PC by enabling the INR input of PC
(PC  PC + 1). 38
 Instruction Cycle

◼T2: The operation code in IR is decoded; the

indirect bit is transferred to I, and the address
part of the instruction is transferred to AR.

◼Similar circuit is used to realize the

microoperations at T2.

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 Instruction Cycle

Determine the type of Instruction:

◼At T3, microoperations which take place depend
on the type of instruction read from memory.
◼Fig. 5-9 presents an initial configuration for the
instruction cycle and shows how the control
determines the instruction type after decoding.

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41
Type of Instructions

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43
 Instruction Cycle

◼The four different paths are symbolized as

follows, where the control functions must be
connected to the proper inputs to activate the
desired microoperations.
➢D7’IT3 : AR  M[AR], indirect memory transfer.
➢D7’I’ T3 : Nothing, direct memory transfer.
➢D7I’ T3 : Execute a register-reference instruction.
➢D7I T3 : Execute an I/O instruction.

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 Instruction Cycle

➢D7’IT3 : AR  M[AR], indirect memory transfer

1. If D7=0 and I = 1, we have memory reference

instruction with indirect address.
2. It is necessary to read the effective address from
the memory. The micro operation for indirect
address condition can by symbolized as follows:
AR  M[AR]

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 Instruction Cycle

➢D7’I’ T3 : Nothing, direct memory transfer

1. When a memory reference instruction with I=0 is

encountered , it is not necessary to do any thing
since effective address is already in AR.
2. However, the SC must be incremented when
D7 ’ T3=1 so that the execution of memory
reference instruction can be continued with timing
variable T4

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 Instruction Cycle

➢ D7I’ T3 : Register-Reference Instructions

◼The 12 register-reference instructions are
recognized by I = 0 and D7 = 1(IR(12-14)=111).
◼These instructions use bits IR(0-11) of the
instruction code to specify one of 12
instructions.
◼The control functions and microoperations for
register-reference instructions are listed in Table
5-3. 47
Instruction Cycle

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 Instruction Cycle

◼Each operation is designated by the presence of

1 in one of the bits in IR(0-11).
◼By assigning the symbol Bi to bit i of IR all
control functions can be simply denoted by rBi
Therefore D7I’T3 = r is common to all register-
transfer instructions.
◼The control function for CLA can be written as
D7I’T3B11= rB11.
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 Instruction Cycle

◼Because CLA has hexadecimal code 7800 (See

Table 5-2
Which gives binary equivalent
0111 1000 0000 0000
◼The first bit is 0 and is equivalent to I’
◼The next three bits constitute the op-code and
are recognized from decoder output D7
◼Bit 11 in IR is 1 and is recognize as B11
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 Instruction Cycle

◼Control function that initiates the

microoperation for this instruction is
D7I’T3B11=rB11 and its execution will be
completed as the time T3
◼Sequence counter is cleared to zero and control
goes back to fetch next instruction with timing
singal T0

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 Instruction Cycle

◼The first seven instructions are register reference

instructions peform clear, compliment, ciruclar
shift and increment microoperations on the AC
and E registers
◼Next four instructions cause a skip of the next
instruction in sequence when a stated condition
is satisfied.
◼The skipping of the instruction is achieved by
incrementing PC once again 52
 Instruction Cycle

◼The AC is positive when the sign bit is in

AC(15)=0, it is negative when AC(15)=1.
◼The contents of AC=0 when all flips flips are
zero.
◼The HLT instruction clears a start-stop flip-flop
S and stops the sequence counter from counting.
of the register are zero.

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 Instruction Cycle

➢ D7I T3 : Input Output Instructions

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