2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)

Hardware Software Co-Simulation of an AES-128 based

Data Encryption in Image Processing Systems
2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) | 978-1-6654-0478-5/20/$31.00 ©2020 IEEE | DOI: 10.1109/iSES50453.2020.00065

for the Internet of Things Environment

Kusum Lata and Sandeep Saini,
Department of Electronics and Communication Engineering,
The LNM Institute of Information Technology, Jaipur, Rajasthan - 302031
{kusum, [email protected]}

Abstract—Security of the data is a major challenge in the unauthorized person cannot access the image data. Image
deployment and management of the Internet of Things (IoT)
systems in the heterogeneous environment, where data gets
security has many application areas such as- biomedical
transferred very widely and rapidly in multiple modes across the imaging, multimedia systems, military communication,
globe. Concomitant with the advancement of the technology, the internet communication, telemedicine, defense maps, and
number of devices and systems which are involved in mobile computing, etc. Cryptography algorithms are of two
transferring the image data has increased in the heterogeneous types one which uses the same key for encryption and
IoT environment. At present, image processing devices have decryption i.e. Symmetric key cryptography and the second
become an integral part of the IoT edge devices which can collect
one in which each user have different key for encryption and
the images and automatically share with the network. Because of
the multifaceted usage of images in multimedia applications in decryption i.e. Public key cryptography.
the IoT environment, it is essential to protect the data from Advanced Encryption Standard (AES) algorithm is a
unauthorized access. The Advanced Encryption Standard (AES) symmetric key cryptography algorithm that overcomes the
is a well-established cryptography algorithm used in numerous
applications to protect digital data. In this paper, we present a
disadvantages of small block size and less security in the Data
Hardware-Software Co-Simulation with Xilinx System Encryption Standard (DES) algorithm. AES algorithm is
Generator of an AES-128 bit encryption and decryption for IoT published by Rijndael and standardized by Federal
Edge devices. Hardware Co-Simulation makes it possible to Information Processing Standard in 2000 by the National
integrate a design running in an FPGA directly into Simulink Institute of Standards and Technology (NIST) and adopted by
simulation. AES-128 bit algorithm has been implemented on the U.S Government [4], [5]. According to the standard given by
SPARTAN-6 (XC6SLX45-CSG324) FPGA board with XILINX- NIST, AES uses a block cipher of a minimum of 128 bit and
ISE software. Authors can get the successful results for image key of 128/192/256 bits. AES algorithm can encrypt and
encryption and decryption both while implementing on grey and decrypt data. Encryption converts the plaintext block into a
colored images. For Hardware Co-Simulation of AES-128 bit
algorithm with Xilinx system generator, a point-to-point Ethernet
ciphertext block and decryption converts that ciphertext block
approach is used. This implementation is done using Xilinx into the original plaintext block. The ciphertext is generated
ISE14.2 and MATLAB 2011a for both grey image and colored by encoding the input plaintext in such a way that only the one
image of size 448*298. who has its key can decrypt it and get the original data on the
receiver side. In cryptography algorithms, larger key length
Keywords— Cryptography, FPGA, AES-128, VHDL, Image provides higher security but requires more rounds.
encryption, Image decryption, Hardware Co-Simulation, Internet of
Thing, Image Processing For secured image data transfer, AES, and chaos-based
image encryption method is proposed and fast and highly
I. INTRODUCTION secure images can be transferred for Earth Observation
In the era of heterogeneous IoT environment around us Satellites (EOS) using this approach [6]. This improved AES
where data transmission continues to happen every single encryption method can also be used for normal secured images
second, the Protection of these data is a daunting task; transfer. Image encryption using AES and RSA has been done
however, with proper use of cryptography, these security [7] and it is found that AES performance is better for RSA for
challenges can be alleviated. Cryptography algorithms are securing the images. Based on the chaos system and AES
image encryption is done and reported as performing better
generally used where security is essential such as bank
than the existing work [8]. A modified AES by changing the
services, military services, ATM cards, computer passwords,
shift row operations of the original AES for image encryption
online money transaction, and e-commerce; it is also used in
is presented [9]. AES algorithm implementation is done using
the wireless device [1], [2], Bluetooth low energy application Xilinx System Generator inbuilt boxes on the Virtex-6
[3] where encryption and decryption needed on the transmitter xc6vsx315t-3ff1156 FPGA board [10].
and receiver side respectively. As industries are widely using
image data for communication, so it is important to protect the A. Contribution and Outline
data from the intruder. Image security means sending the In this paper, Hardware Software Co-Simulation of AES-
image securely over a transmission medium so that, an 128 based data encryption towards Image Processing

978-1-6654-0478-5/20/$31.00 ©2020 IEEE 260

DOI 10.1109/iSES50453.2020.00065
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applications for the Internet of Things environment is III. EXPERIMENTAL SETUP
presented. Authors are successfully able to implement and get AES-128 crypto-module is implemented using VHDL
the encryption and decryption results of both types of images first and then it is implemented using Xilinx System
i.e. grey and colored images. The paper is organized as Generator. For implementing the AES-128 crypto-module,
follows: Section II describes the existing crypto-algorithms two types of the architectures are used i.e. loop unrolled
which are used at the hardware level for transferring the architecture and FSM based architecture. FSM based
secure images in the Internet of Things environments. architecture gives better performance than loop unrolled
Implementation and experimental set up of AES-128 crypto- architecture. It has been discussed in detail in the results
module using VHDL and System Generator in Xilinx ISE14.2i section. Fig. 1 shows the experimental setup used for the
and MATLAB 2011a on SPARTAN-6 (XC6SLX45-CSG324) hardware-software co-simulation of AES-128 using Xilinx
FPGA board are discussed in Section III. Section IV shows the System Generator and Spartan 6 FPGA board. This is a
successful encryption and decryption results of the development board from Xilinx with series XC6SLX45-
implemented AES-128 crypto-module for normal images. In CSG324. The setup used for the evaluation of the
this section area and calculated throughput for the implementation consists of Xilinx ISE14.2i and MATLAB
implemented loop unrolled architecture of AES is discussed 2011a. The HOST PC is connected through USB for hardware
and also compared with the existing work. Section V software co-simulation purposes. The provided input,
concludes the presented work. encrypted, and decrypted output can be seen on this HOST PC
II. EXISTING HARDWARE IMPLEMENTATIONS OF CRYPTO as well.
MODULES FOR SECURED IMAGE TRANSFER IN IOT
ENVIRONMENT
Various smart devices and sensors are deployed to
provide convenient services in heterogeneous IoT
environments. When it comes to secure data transfer, crypto-
modules are the best solutions to provide the confidentially
available integrated data. The existing research provides many
solutions at the hardware level for security in resource-
constraint devices [11]–[14]. In [15] around 54 lightweight
crypto primitives are surveyed and compared and it is found Fig.1. Experimental Setup Used for Hardware Software Co-Simulation of
that AES and ECC are the most suitable lightweight crypto AES-128 Crypto-module
primitives when it comes to providing the security of IoT
devices. The performance of various crypto algorithms e.g. IV. HARDWARE CO-SIMULATION OF AES-128 BIT ALGORITHM
AES, Twofish, LEA, etc. are discussed and compared by USING XILINX SYSTEM GENERATOR
measuring their throughput, execution times, and power For performing the hardware software co-simulation
consumption in [16]. authors have implemented and analyzed the results for two
Many research papers are published to showcase the case studies i.e. for grey images and colored images. The First
performance of the most widely accepted and used crypto- Simulink model is built and then it is integrated with the
algorithm AES for providing security to IoT devices. In a Xilinx System Generator, Xilinx ISE, and MATLAB software
wireless sensor network, AES algorithm based image to perform the co-simulation of the AES-128 crypto module.
encryption is discussed and is also used to encrypt the image Implementation and results are discussed in the following
in real-time [17]. Because multimedia applications affect subsections.
several aspects of our daily life therefore hardware Case 1: Implementation of AES-128 bit algorithm for Grey
implementation of AES based real-time encryption of video is Image in Simulink:
presented in [18], where video encryption is verified and The model for the grey image in the Xilinx system
displayed on the DVI screen. Hardware- Software co-design generator is shown in Fig. 2. In this model, the input image is
of the AES-RC4 algorithm is discussed and reported in [19] taken of size 448*298 pixels. After resizing the image in the
with low latency. The designed system is implemented using image preprocessing block the image resolution becomes
Cyclone IV FPGA and results in analysis shows that the 224*298, this goes for further processing. A black box named
system gives better performance in terms of area and latency. Bit conversion having a VHDL code of converting the 8-bit
A modified version of the AES algorithm is also output of gateway into 128 bit, as we need 128-bit block
implemented for the image encryptions in [20], where a key length and key length for the AES algorithm. The encryption
generator (A5/1, W7) was added to AES to improve the black box having the VHDL coding of AES encryption gives
performance. Side-channel attacks is the major issue in crypto- the outcome as an encrypted image and the Decryption black
module hardware implementations. Therefore, in [21] Security box having the VHDL coding of AES decryption gives the
of the AES has been enhanced by applying the obfuscation to result as a decrypted image.
the design, and then it has been used in hardware software co-
design of AES-128 for image processing applications.

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 Fig. 2. Simulink Model of AES-128 bit Algorithm for grey image input

Fig. 3. AES-128 bit implementation on SPARTAN-6 FPGA board Simulink model

Fig. 4. Simulink Model of AES-128 bit Algorithm for colored image input

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Case 2: Hardware co-simulation of AES-128 bit algorithm for B. Hardware Software Co-simulation Results for Grey and
Grey Image with Xilinx System Generator and SPARTAN- Colored Images
6(XC6SLX45-CSG324) FPGA: The mentioned design is an integral part of the Xilinx
Implementation of grey image AES encryption and System Generator based design. The experiment is performed
decryption on SPARTAN-6(XC6SLX45-CSG324) FPGA on both types of images i.e. grey images and colored images.
board using the Xilinx system generator is shown in Fig. 3. In Fig. 5 shows the encrypted and decrypted image for a grey
this Simulink model final_aes_hardware_cosim is the netlist color image by performing the hardware software co-
generated for the FPGA board. simulation using Xilinx System Generator.
Case 3: Hardware co-simulation of AES-128 bit algorithm for
Colored Image with Xilinx System Generator and SPARTAN-
6(XC6SLX45-CSG324) FPGA:
The model for a colored image in the Xilinx system
generator is shown in Fig. 4. In this model, the input image is
taken colored of size 448*298 pixels. After resizing the image
in image preprocessing the image resolution becomes Fig. 5. Original, encrypted, and decrypted grey image through
Hardware Software Co-simulation
224*298, which goes for further processing. This whole thing
Hardware Software Co-simulation results for colored
is used for R, G, and B separately.
images using Xilinx System Generator are shown in Fig. 6.
IV. RESULTS AND ANALYSIS
This section presents the two types of the results here: A)
VHDL implementation of AES-128 using loop unrolled
architecture and using FSM on Virtex-5 FPGA board and its
comparison with the similar existing work in terms of area and
throughput. B) Successfully encrypted and decrypted results of
grey and colored images.
Fig. 6. Original, encrypted, and decrypted colored image through
A. Resource Utilization and Throughput Hardware Software Co-simulation
AES-128 is implemented using loop unrolled architecture V. CONCLUSION
as well as using FSM. Table I shows the resource utilization of
the implemented architecture. In this paper, Hardware-Software Co-Simulation with
Throughput for both the cases is calculated as follows for Xilinx System Generator of an AES-128 crypto-module is
the implemented AES-128. presented which is used for encryption and decryption of the
images for IoT Edge devices. It is an important feature that
Number of processed bits helps the IoT devices to transfer the images securely over the
Throughput=
Critical path delay present heterogeneous IoT environment. AES-128 crypto-
module is designed using two architectures i.e. loop unrolled
The maximum frequency is achieved as 332.34 MHz and
architecture and FSM based architecture. It is found that FSM
throughput is calculated as 4.254 Gbps for loop unrolled
based architecture is giving better performance when it is
architecture whereas throughput comes out to be as 3.485
compared with the similar existing implementations. For
Gbps for the frequency of 272.33 MHz. Table II presents the
performing the co-simulation Xilinx System Generator is
comparison results with the existing work and shows that the
used. Simulink model has been developed for simulating the
designed implementation is working better in terms of area
grey and colored images. Then, hardware Co-Simulation is
and throughput.
also presented with the Xilinx system generator and
Table II: Comparison with the existing work
SPARTAN-6(XC6SLX45-CSG324) FPGA kit. This
Design Device Through Slices Throughput/ implementation is done using Xilinx ISE14.2 and MATLAB
-put Area 2011a for both grey image and colored image of size 448*298.
(Mbps) (Mbps/slices) We can get the successful results for both the schemes which
[22] Virtex- 1604 1857 0.867 AES-128 bit algorithm encryption and decryption. Results for
EBG860 grey and colored images are presented in the result section.
[23] XC3S40 2059 1403 1.467 This work can be extended for the various schemes of image
0-FG456 security as well as the modified version of the implemented
[24] Kintex-7 1670 5110 0.327 algorithms.
Loop Virtex-5- 4342 8704 0.488 ACKNOWLEDGEMENT
Unrolled 3ff1738
FSM Virtex-5- 3485 1345 2.591 Simulation results are the part of the M.Tech. Thesis work
Arch. 3ff1738 carried out by Ms. Niharika Agarwal. She is graduated from
the Department of Electronics and Communication

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Table I: Resource utilization for AES-128 loop unrolled architecture implementation on Virtex-5
Device: Virtex5 xc5vlx110t-3ff1738
Logic Utilization Loop Unrolled Architecture FSM Architecture
(Number of) Used Available Utilization % Used Available Utilization %
Slice Registers 8704 69120 12 1345 69120 1
Slice LUTs 20402 69120 29 14798 69120 21
Fully Used Bit Slices 6175 22931 26 934 22931 4
Bonded IOBs 514 680 75 524 680 77
BUFG/BUFGCTRLs 2 32 6 1 32 3

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