Unit IV
Unit IV
Features
• Four parallel I/O ports( P0, P1,P2, P3), each 8 bits wide
• 1 to 16 MHz clock
Pin Diagram
Pins 1 – 8 (PORT 1): Pins 1 to 8 are the PORT 1 Pins of 8051. PORT 1 Pins consists of 8 – bit
bidirectional Input / Output Port with internal pull – up resistors. In older 8051
Microcontrollers, PORT 1 doesn’t serve any additional purpose but just 8 – bit I/O PORT.
In some of the newer 8051 Microcontrollers, few PORT 1 Pins have dual functions. P1.0 and
P1.1 act as Timer 2 and Timer 2 Trigger Input respectively.
P1.5, P1.6 and P1.7 act as In-System Programming Pins i.e. MOSI, MISO and SCK respectively.
Pin 9 (RST): Pin 9 is the Reset Input Pin. It is an active HIGH Pin i.e. if the RST Pin is HIGH for a
minimum of two machine cycles, the microcontroller will be reset. During this time, the
oscillator must be running.
Pins 10 – 17 (PORT 3): Pins 10 to 17 form the PORT 3 pins of the 8051 Microcontroller. PORT 3
also acts as a bidirectional Input / Output PORT with internal pull-ups. Additionally, all the PORT
3 Pins have special functions. The following table gives the details of the additional functions of
PORT 3 Pins.
Pins 18 & 19: Pins 18 and 19 i.e. XTAL 2 and XTAL 1 are the pins for connecting external
oscillator. Generally, a Quartz Crystal Oscillator is connected here.
Pin 20 (GND): Pin 20 is the Ground Pin of the 8051 Microcontroller. It represents 0V and
is connected to the negative terminal (0V) of the Power Supply.
Pins 21 – 28 (PORT 2): These are the PORT 2 Pins of the 8051 Microcontroller. PORT 2 is
also a Bidirectional Port i.e. all the PORT 2 pins act as Input or Output. Additionally,
when external memory is interfaced, PORT 2 pins act as the higher order address byte.
PORT 2 Pins have internal pull-ups.
Pin 29 (PSEN): Pin 29 is the Program Store Enable Pin (PSEN). Using this pins, external
Program Memory can be read.
Pin 30 (ALE/PROG): Pin 30 is the Address Latch Enable Pin. Using this Pins, external
address can be separated from data (as they are multiplexed by 8051).
During Flash Programming, this pin acts as program pulse input (PROG).
Pin 31 (EA/VPP): Pin 31 is the External Access Enable Pin i.e. allows external Program
Memory. Code from external program memory can be fetched only if this pin is LOW.
For normal operations, this pins is pulled HIGH.
During Flash Programming, this Pin receives 12V Programming Enable Voltage (VPP).
Pins 32 – 39 (PORT 0): Pins 32 to 39 are PORT 0 Pins. They are also bidirectional Input /
Output Pins but without any internal pull-ups. Hence, we need external pull-ups in order
to use PORT 0 pins as I/O PORT.
In addition to acting as I/O PORT, PORT 0 also acts as lower order address/data bus
when external memory is accessed.
Pin 40 (VCC): Pin 40 is the power supply pin to which the supply voltage is given (+5V).
Architecture of 8051
Architecture consists of CPU, Memory, and Peripherals.
Registers: A, B, PSW, DPTR, PC, SFR, (DPTR-16bit reg. DPL-low byte, DPH- High Byte)
Parallel port (PO, P1, P2, P3), Serial port, Timers (T0 and T1) and Interrupts.
Memory Organization of 8051
Program Memory
Data Memory
Each Register Bank has 8 general purpose registers (R0, R1, R2, R3, R4, R5, R6, R7)
21 ,09,08
• 128 bytes of internal RAM (00H to 7FH)is general R/W storage.
• 21 Special-Function Registers (SFR) which are not part of 128 bytes of RAM at
80H to F8H locations of the RAM space.
• 64 KB External RAM can be used fully in addition to 128 internal RAM.
• Although 8051 normally operates with separate program and data memory
space, there are applications where it can be used as one 64 KB of memory.
When this is done, 8051 can input a block of data through its serial
communication port, load it into memory, and then execute that data as a
program.
Addressing Modes
1) Immediate
MOV A, #5FH
SUB A, #27H
2) Register
ADD A, R4
3) Direct
ADD A, 45H
MOV A, @R0
ADD A, @R1
5) Indexed
MOVC A, @ A+DPTR
MOVC A, @ A+PC
Instruction sets of 8051
Data Transfer
MOV, MOVC,MOVX,PUSH,POP,XCH,XCHD
Rn= R0 – R7
Arithmetic Instructions
ANL, ORL, XRL, CLR, CPL, RL, RLC, RR, RRC, SWAP
Boolean or Bit manipulations
CLR, SETB, MOV, JC, JNC, JB, JNB, JBC, ANL, ORL, CPL
A-1100 0000 (C 0)- A- BYTE ADDRESSABLE-8, BIT addressable – 1bit.. ACC.7, ACC.3,
ACC.0
JNC 45H
ADD A, 25H
JB P1.2, LOOP1
SUBB
Branching Instructions
LJMP, AJMP, SJMP, JZ, JNZ, CJNE, DJNZ, NOP, LCALL, ACALL, RET, RETI, JMP
DJNZ R5, 7FH; DJNZ 44H, 54H
TIMERS/COUNTERS OF 8051
SFR registers:
TMOD Register
M1, M0 (16 BIT TIMER/COUNTER – TH0 AND TL0 -3FFF- FFFF) (00-FF)
M1 M0 MODE DESCRIPTION
0 0 0 13-bit timer-8192
0 1 1 16-bit timer-65536
1 0 2 8-bit auto-reload-256
1 1 3 Split mode-256
C/T
COUNTER = 1, TIMER = 0
GATE
GATE=0, START TIMER/COUNTER OPERATION BY TRX (TIMER RUN CONTROL BIT)- S/W
FFFF-0000
8 bit timer
13 bit timer
5) CLR TRX
UART
SFR registers
SCON REGISTER
Baud rate
SM0 SM1 MODE Description
Clock Frequency
Baud Rate= -----------------------
12 x 32 x (256-TH1)
3) Initialize TMOD register (Timer1 in mode 2 (auto reload); load values in TH1
4) start timer1
Sources
Registers
IE (Interrupt Enable)
IP (Interrupt Priority )