BEC302

Model Question Paper-I with effect from 2023-24 (CBCS Scheme)

USN

Third Semester B.E. Degree Examination

Digital System Design using Verilog
TIME: 03 Hours Max. Marks: 100

Note: 01. Answer any FIVE full questions, choosing at least ONE question from each MODULE.

*Bloom’s
Module -1 Taxonomy Marks
Level
Q.01 a Design a logic circuit that has 4 inputs, the output will only be high, when L3 10
the majority of the inputs are high. Use k-map to simplify
b Simplify the given Boolean function using Quine MC Cluskey find the L3 10
prime and essential prime implicants and also verify with K-map
f(A,B,C,D)=⅀m(0,1,4,5,7,8,13,15) +d(2)

OR
Q.02 a Simplify the following expression using K-map. Implement the simplified L3 10
expression using basic gates only
f(a,b,c,d)=ΠM(0,2,3,4,5,12,13)+dc(8,10)
b Define the following terms with example. L1 04
Minterm, Maxterm
c Place the following equation into proper canonical form L3 06
P = f(a,b,c) = ab'+bc
T = f(a,b,c) = (a+b) (b'+c)
Module-2
Q. 03 a Design two bit magnitude comparator and write truth table, relevant L3 08
expression and logic diagram.

b Implement the following functions using 3:8 decoder L3 6

f1(a,b,c) =⅀m(1,3,5)
f2(a,b,c)=⅀m(0,1,6)
c Implement Y=ad+bc'+bd using 4:1 mux considering A and B as a select L3 6
line.
OR
Q.04 a Explain 4-bit carry look ahead adder with neat diagram and relevant L2 10
expressions.
b Implement the following Boolean function using 8:1 multiplexer and 4:1 L3 10
multiplexer f(a,b,c,d) = Σm(0,1,5,6,10,12,14,15).
Module-3
Q. 05 a Explain the working of Master-Slave JK flip-flop with functional table and L2 10
timing diagram.
b Explain Universal Shift Register with the help of logic diagram, mode L2 10
control table.
OR
Q. 06 a Derive Characteristic equation for SR,T,D and JK flip-flop with the help L2 10
of function table
b Design a Synchronous Mod-6 counter using SR flip-flop for the sequence L3 10
0-2-3-6-5-1.

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 BEC302
Module-4
Q. 07 a Realize the 2x1 Multiplexer with active low enable and also write the L3 10
Verilog program by considering delay time to the signal assignment
statements with simulation waveform.
b Realize the Full Subtractor circuit using Verilog data flow description. L3 10
OR
Q. 08 a List all the data types available in Verilog HDL and explain any four data L2 10
types with examples.
b Explain arithmetic and logical operator with example. L2 10
Module-5
Q. 09 a Realize the D-Latch Behavioral description code with circuit diagram, L3 10
waveform.
b Write a Verilog structural code for four bit ripple carry adder. L3 10
OR
Q. 10 a Explain with syntax of the following sequential statements in Verilog. i) L2 8
For-loop ii) While-loop iii) Repeat iv)Forever
b Write a Verilog program for 8:1 MUX using case statement. L3 6
c Realize the JK flip-flop using Verilog Behavioral description. L3 6

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 BEC302
Model Question Paper-II with effect from 2023-24 (CBCS Scheme)
USN

Third Semester B.E. Degree Examination

Digital System Design using Verilog
TIME: 03 Hours Max. Marks: 100

Note: 01. Answer any FIVE full questions, choosing at least ONE question from each MODULE.

*Bloom’s
Module -1 Taxonomy Marks
Level
Q.01 a What is combinational circuit? Design a combinational logic circuit with
three input variables that will produce logic 1 output when more than one L2 06
input variables are logic 1.
b Convert the following Boolean function into canonical minterm and
L2 06
maxterm form in decimal format 𝑅 = 𝑓 𝑎, 𝑏, 𝑐 = 𝑎 + 𝑏 𝑎 + 𝑐 + 𝑏𝑐
c Find all the prime implicants and essential prime implicants for the
following function using k-map method.
L3 08
(i) 𝑀 = 𝑓 𝑎, 𝑏, 𝑐, 𝑑 = Σ(1,5,7,8,9,10,11,13,15)
(ii) 𝑌 = 𝑓 𝑎, 𝑏, 𝑐, 𝑑 = π(0,2,3,8,9,10,12,14)
OR
Q.02 a . Simplify the following Boolean functions using K-map
(i) 𝑌 = 𝑓 𝑎, 𝑏, 𝑐, 𝑑 = π 0,1,4,5,8,9,11 + 𝑑(2,10) L3 10
(ii) 𝑀 = 𝑓 𝑤, 𝑥, 𝑦, 𝑧 = Σ(0.1,2,4,5,6,8,9,12,13,14)
b Solve the following Boolean function by using QM minimization
technique
L3 10
𝑃 = 𝑓 𝑤, 𝑥, 𝑦, 𝑧 = Σ 2,3,4,5,13,15 + d(8,9,10,11)
Verify using K-map method
Module-2
Q. 03 a Implement the following functions using 3:8 decoder along with OR
and/or NOR gates. In each case the gates should be selected so as to
minimize their total number of inputs.
(a) f1 (X2, X1, X0) = Σ m(0,2,4,6,7) and f2 (X2, X1, X0) = Σ L3 07
m(1,3,5,6,7)
(b) f1 (X2, X1, X0) = ΠM (0,2,4,6,7) and f1 (X2, X1, X0) = ΠM (1,3,7)

b Construct single decade decimal adder with necessary correction circuit

L2 08
design.
c Design a one-bit comparator circuit. L2 05
OR
Q.04 a Construct the following function S = f(a,b,c,d) = Σ(1,4,5,7,8,9,14,15) using
L2 07
(a)8:1 Mux and (b)16:1 Mux
b Construct the functional table for 4 to 2 line priority encoder with a valid
output, assigning highest priority to highest bit position or input with L2 07
highest index and obtain the minimal sum expressions for the outputs.
c Implement a Full adder using PAL L2 06
Module-3
Q. 05 a Explain the working of Master-Slave JK flip-flop with functional table and
L2 08
timing diagram
b Derive the characteristic equations of SR and D Flipflops L2 04
c Make use of negative edge triggered T -Flip Flops to describe the working L2 08

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 BEC302
of 4-bit binary ripple counter. Also draw the timing diagram.
OR
Q. 06 a Make use of 4-bit shift register circuit to explain the following modes of
L2 08
operations: SISO, SIPO, PISO and PIPO.
b Develop a mod-5 synchronous counter with the sequence 0,2,6,3,1 using T
L3 07
-Flip Flops.
c Explain the working of Ring counter with necessary diagram and
L2 05
equations.
Module-4
Q. 07 a List all the data types available in Verilog HDL. Explain any three data
L2 08
types with examples.
b Explain three modeling styles available in Verilog with half adder example L2 07
c (ii)Evaluate the following:
i)A * B ii) A + B iii) A << 2 iv) {A [3], B} L2 05
Given: A=0011 B= 0100
OR
Q. 08 a Explain the Signal declaration and Assignment Statements in Verilog data-
L1 06
flow description.
b Realize D latch with active high enable and also write the Verilog program
by considering delay time to the signal assignment statements with L2 08
simulation waveforms.
c Write a verilog dataflow model for full adder L2 06
Module-5
Q. 09 a Write a verilog behavioural description for 8:1 mux along with the design
L2 08
and timing diagrams.
b Explain different case statements available in verilog with syntax and
L2 06
necessary examples
c Realize the Binary up-down counter using verilog behavioral description. L2 06
OR
Q. 10 a Explain with syntax of the following sequential statements in Verilog.
L2 06
i) For-loop ii) While-loop iii) Repeat
b Write a structural description of 3-bit ripple carry adder L2 08
c Write a verilog code for 2x1 mux using If Else statement L2 06

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