Model 1

1.With the help of diagram explain Basic Operational Concepts of computer. Explain the
steps in detail. Or
Draw and explain the connection between memory and processor with the respective register
2.How to measure the performance of a computer? Explain
Or
What is performance measurement? Explain the overall SPEC rating for the computer in a
program suite
3.Analyze Big Endian and Little Endian method of byte addressing with proper example
4. What are various factors that affect the performance of the system? A program contains
1000 instructions. Out of that 25% instructions require 4 clock cycles, 40% instructions
require 5 clock cycles and remaining require 3 clock cycles for execution. Find the total time
required to execute the program running in a 1 GHz machine.
6. Define addressing Modes. Explain the types of addressing modes with example.[10 marks]
7.Registers R1 and R2 of a computer contain the decimal values 1200 and 4600. What is the
effective address of the memory operand in each of the following instructions? [8 marks]
(i) Load 20[R1],R5
(ii) Move #3000,R5
(iii) Store R5,30[R1,R2]
(iv) Add –(R2),R5
8.Show how the below expression will be executed in one address, two address and three
address processors in an accumulator organization C=A-B [8marks]
9.Show how the below expression will be executed in one address, two address and three
address processors in an accumulator organization C=A-B [8marks]
10. Show how the below expression will be executed in one address, two address and three
address processors in an accumulator organization C=(A*B)+(C*D) [8marks]
11.Explain the fallowing (i) Processor clock (ii) Basic performance Equation (iii) Memory
operation
12. Explain the fallowing (i)Register transfer Notation (ii)Assembly language Notation
13. Define and discuss about straight-line sequencing and instruction execution
14.Differentiate the instruction execution for adding ‘n’ numbers using Straight line
sequencing and branching
 Model 2-Input/Output Organization
1.Ilustrate a program that reads one line from the keyboard, stores it in memory buffer, and
echoes it back to the display in an I/O interface
2.write the scenario when the interrupts are enabled.
3.With neat sketches, explain various methods for handling multiple interrupts requests raised
by multiple devices
4.What is an interrupt? What are interrupt service routines and what are vectored interrupts?
Explain with example
5.Explain how the I/O devices should be organized in a priority structures,
6.Define Exception, describe the different kinds of exceptions
7.Demonstrate the DMA and its implementation and show how the data is transferred between
memory and I/O devices using DMA controller.

8. What is DMA bus Arbitration? Briefly explain different bus arbitration techniques.

9.Explain synchronous Bus and Asynchronous bus with neat timing diagrams.
 Module-3-Memory system
1. Explain internal organization of 16 Megabit DRAM chip configured as 2M*8 cells
Also explain how it can be made to work fast in fast page mode.
2. Explain the working of 16-megabyteDRAM chip configured as 1M x 16 memory
chip.
3. Discuss the internal organization of a 1K x 1 memory chip
4. Explain the read and write operations of a static RAM cell and CMOS cell
5. Differentiate between SRAM and DRAM giving 5 key differences.(With a cell
diagram).
6. With a block diagram, explain the organization of 8M x 32 memory using 512 K x 8
memory chips
7. Explain synchronous DRAM with a neat diagram.
8. With figure analyse the memory hierarchy in terms of speed cost and size
9. What is cache? With block diagram explain Direct, Associative and set-associative
mapping between cache and main memory.
10. Briefly explain any four non-volatile memory concepts(ROM, PROM, EPROM,
EEPROM, Flash)

1.With a neat diagram, explain the internal organization of 16x8 memory chip (10 marks)page
2-3
2. What is cache? With block diagram explain Direct, Associative and set-associative
mapping between cache and main memory. (10 Marks)(pages-16 to 21)
3. Differentiate between SRAM and DRAM giving 5 key differences.(With a cell
diagram).(6 marks)(page no-24)
4. Describe the working of static RAM memories (5 marks)(page4-5)
5.Explain the operation of a CMOS memory cell.(6 marks) page4-5)
6.With a neat figure, explain the organization of a 2Mx32 memory module using 512Kx8 static
memory chip.(8 marks)(page no-8-9)
7. Explain the internal structure of synchronous DRAM with diagram(8 marks)page7-8
8. Analyze how data are written into Read only memories (ROM). Discuss different types of
Read Only Memories (10 marks)page no-11-13
9.Analyze the working mechanism of asynchronous DRAM(6 marks) page no-5
10. Discuss the internal organization of a 1K x 1 memory chip
11. With a neat figure, explain the internal organization of 2MX8 dynamic memory chip. (8
marks) page-5-6
12. With figure analyse the memory hierarchy in terms of speed cost and size(6 marks)page
13-14)
13. Explain synchronous DRAM with a neat diagram.
14. What is virtual memory? Explain simple method of translating virtual address into
physical address.
15. Define the following:
a. Memory Latency
b. Memory bandwidth
c. Hit rate d. Miss-penalty
Model 4-Airthmetic and basic processing Unit

1.perform the fallowing operation on the 5-bit signed numbers using 2’s complement
representation system:
i. (-10) + (-13)
ii. (-10) - (+4)
iii. (-3)+(-8)
iv. (-10) – (+7)

2.substract -5 from -7 using Two’s complement subtraction.

3. Perform the addition and subtraction of signed number.
i. +4 and -6
ii. -5 and -2
iii. +7 and -3
iv. +2 and +3

4. Explain 4 bit carry-look ahead adder with a neat diagram (10 marks)
Or
In a carry look ahead addition, explain the generate Gi and propagate Pi functions for stage i.
Using this design explain 4 bit carry look ahead adder(10 marks)

5.Perform the multiplication of positive numbers +13 and +11 using sequential multiplication
method .(10 marks)

6. Explain sequential multiplication method with a neat diagram.( 8 marks)

Or
Explain sequential multiplication method algorithm. Apply sequential multiplication method
to
7.Explain the working of single bus organization of data path. (7 marks)

8.Write the sequence of control steps to execute the instruction Add(R3),R1 on single bus
architecture. (8 marks).

9. Draw and explain multiple bus(three bus) organization.. Explain its advantages (10 marks)

10. write and explain the control sequence for execution of an unconditional branch
instruction.(10 marks)

11. What is the purpose of control unit ? with neat sketches explain the organization of
hardwired control unit in detail (10 marks)
 Model 5-Pipeline Processing
1.Explain Flynn’s classification in detail?(5 marks)[page no 301]
2.Define pipeline. Explain with example and content of register table in pipeline.[page no-
302,303,304][10 marks]

3.In certain scientific computations it is necessary to perform the arithmetic operation (Ai+Bi)(
Ci+Di)with a stream of numbers. specify a pipeline configuration to carryout this task. List the
contents of all registers in the pipeline for i=1 through 6.
4. Draw a space-time diagram for a six-segment pipeline showing the time it takes to process
eight tasks.

5. Determine the number of clock cycles that it takes to process 200 tasks in a six-segment
pipeline
6. The non pipeline system takes 50 ns to process a task . the same task can be processed in a
six – segment pipeline with clock cycle of 10ns . Determine the speedup ratio of the pipeline
for 100ns task . what is the maximum speedup that can be achieved?

8.Explain arithmetic pipeline with four segments example. [page no 307-309]

7.What is pipelining? Explain the five stages Instruction pipeline with timing diagram(10
marks)[page no 311
Or
Explain basic idea of instruction pipelining(10 marks)
Or
What is pipelining? Explain the 4 stages pipeline with its Instruction execution steps and
hardware organization(10 marks)
8.Exaplain pipeline for calculating an inner product in vector processing.
9. With diagram, Explain attached array processor with host computer.
10.Explain SIMD array processor organization with a neat diagram.
11. differentiate b/w vector processing and array processors.