Chapter 5

Synchronous Sequential Logic

Objectives: After completing this chapter, you should be able to:

• Analyze the sequential logic.
• Learn operation of the S-R latch.
• Design D flip-flop from S-R latch.
• Learn the application of the D flip-flop.
• Learn operation of the J-K and T flip-flops.
• Design register and shift register using the D flip-flops.
• Develop state table for a sequential circuit.
• Develop state diagram from the state table.
• Develop excitation table for each types of flip-flop.
• Design digital counter.

5.1 Introduction

Sequential logic circuit contains memory elements, and the output depends on the
current value of input and prior input-level conditions. Figure 5.1 shows block
diagram of sequential logic as shown in this figure; the outputs depend on the inputs
and current state of memory elements; in this figure, the outputs of combinational
logic are the inputs to memory elements, and the outputs of memory elements are
the inputs to combinational logic; the basic elements of memory elements are flip-
flops that can hold binary values as long as the device is powered. The output of a
synchronous sequential logic depends on the outputs of memory elements and
inputs. The applications of synchronous sequential logic are designing register,
counter, and memory. Synchronous sequential logic operates with the clock pulse.

© Springer International Publishing AG 2018 97

A. Elahi, Computer Systems, https://doi.org/10.1007/978-3-319-66775-1_5
98 5 Synchronous Sequential Logic

Fig. 5.1 Block diagram of synchronous sequential logic

Fig. 5.2 Block diagram

of S-R latch

Fig. 5.3 Logic circuit S

of S-R latch using NOR Q
gates

Q'
R

Fig. 5.4 Logic circuit S

of S-R latch using NAND Q
gates

Q'
R

5.2 S-R Latch

S-R latch is a type of memory with two inputs S (set) and R (reset), two outputs Q,
and Q0 , and the outputs are the complement of each other. Figure 5.2 shows block
diagram of a S-R latch.
A S-R latch can be constructed with NOR or NAND gates: Fig. 5.3 shows S-R
latch using NOR gates and Fig. 5.4 shows S-R latch using NAND gates.
5.3 D Flip-Flop 99

Table 5.1 Characteristic S R Q Q0

table of S-R latch
0 0 1 1 Forbidden
0 1 1 0
1 1 1 0 No change
1 0 0 1
1 1 0 1 No change

S
D
Q

Clock
010

R Q'

Fig. 5.5 Logic circuit of D flip-flop

S-R Latch Operation Consider S-R latch of Fig. 5.4 which is constructed with
NAND gates; the following steps describe the operation of S-R latch, and Table 5.1
shows its characteristic table:
1. By setting S ¼ 0 and R ¼ 0, results outputs Q ¼ Q0 ¼ 1 which are not permitted
because Q and Q0 must be a complement of each other; therefore, S ¼ R ¼ 0 is
prohibited.
2. By setting S ¼ 0 and R ¼ 1, results Q ¼ 1 and Q0 ¼ 0 as shown in Table 5.1, if S
changes from 0 to 1 then Q does not change.
3. By setting S ¼ 1 and R ¼ 0, results Q ¼ 0 and Q0 ¼ 1, if R changes from 0 to
1 then the Q does not change. It can conclude when S ¼ R ¼ 1 the output of Q
does not change (if Q ¼ 0 stays 0 or Q ¼ 1 stays 1). The S-R latch is a basic logic
circuit for D, J-K, and T flip-flops.

5.3 D Flip-Flop

D flip-flop is a 1-bit memory, and it is used for designing SRAM (Static RAM) and
register; Fig. 5.5 shows the logic diagram of D flip-flop. The inputs to flip-flop are D
and clock. When the clock is 0, then S ¼ R ¼ 1, and according to Table 5.2 the
output of flip-flop doesn’t change, by setting D to 0, and changing clock from 0 to
1 results S ¼ 0 and R ¼ 1 then Q ¼ 0 and Q0 ¼ 1; this means when input D ¼ 0 and
applying clock, the output Q changes to 0. Setting D to 1 and changing clock from
0 to 1 results S ¼ 0 and R ¼ 1, and then according to Table 5.2, the Q sets to one;
this means when input D ¼ 1 and applying clock, the output Q changes to
1. Figure 5.6 shows block diagram of D flip-flop, and rising edge of the clock is
represented by “ ” and Table 5.2 shows a characteristic table of D flip-flop.
100 5 Synchronous Sequential Logic

Table 5.2 Characteristic Clock D Q

table of D flip-flop
" 0 0
" 1 1

Fig. 5.6 Block diagram of

D flip-flop

Fig. 5.7 J-K flip-flop

Table 5.3 Characteristic Clock J K Q

table of J-K flip-flop
" 0 0 No change
" 0 1 0
" 1 0 1
" 1 1 Complement

5.4 J-K Flip-Flop

Figure 5.7 shows block diagram of a J-K flip-flop where J, K, and clock are the
inputs to the J-K flip-flop. The application of J-K flip-flop is counter and frequency
divider. Table 5.3 shows characteristic table of J-K flip-flop, and the following steps
describe J-K flip-flop operations:
(a) By setting J ¼ K ¼ 0 and applying clock pulse to the flip-flop, the output Q does
not change, if Q ¼ 0 then stays 0, or if Q ¼ 1 then stays 1.
(b) By setting J ¼ 0, K ¼ 1 and applying clock pulse to the flip-flop, then output Q
changes to 0.
(c) By setting J ¼ 1, K ¼ 0 and applying clock to the flip-flop, the output Q changes
to 1.
(d) By setting J ¼ K ¼ 1 and applying a clock pulse, the output of the flip-flop is the
complement of present output; this means if Q ¼ 0 and applying clock, then
output changes to 1 and if Q ¼ 1 and applying clock pulse then the output will
change to 0.
5.6 Register 101

Fig. 5.8 Block diagram of T flip-flop

Table 5.4 Characteristic Clock T Q

table of T flip-flop
" 0 No change
" 1 Complement

5.5 T Flip-Flop

T flip-flop is a special case of J-K flip-flop, and by connecting J and K inputs of J-K
flip-flop together results in a T flip-flop; Fig. 5.8 shows a block diagram of T flip-
flop, and Table 5.4 shows the characteristic table of T flip-flop; as shown in
Table 5.4 if T ¼ 0 and applying clock pulse, then the output of T flip-flop does
not change, and if T ¼ 1 and applying clock, then output of flip-flop becomes the
complement of the present output.

5.6 Register

D flip-flop is 1-bit memory or 1-bit register. If a group of D flip-flops share a

common clock, it is called register; the N-bit register is constructed with N D flip-
flops, and if 32 D flip-flops use a common clock, then it is called a 32-bit register.
Figure 5.9 shows a 4-bit register, and in this figure by placing 1101 at the inputs and
applying clock pulse, then the output will be 1101.
Shift Register
A shift register has one serial input, and one bit is loaded from serial input into the
register by every clock pulse, and then each bit of register is shifted to the next bit
position. Figure 5.10 shows 4-bit shift right register operation, and after shifting one
bit to the right, the contents of the register will be 0101. Figure 5.11 shows 4-bit
serial shift right register.
Example Figure 5.12 shows 4-bit shift right register; show the contents of register
after applying four clock pulses, and assume initial output of each D flip-flop is
zero.
Figure 5.13 shows shift left register with serial input of 1110100, and Table 5.5
shows contents of register after applying five clock pulses; assume the initial output
of each flip-flop is 0.
102 5 Synchronous Sequential Logic

Fig. 5.9 4-bit register

Fig. 5.10 4-bit shift right register operation

Fig. 5.11 4-bit serial shift right register

Barrel Shifter
Barrel shifter is used for shifting data left and right; barrel shifter uses combina-
tional logic rather shift register; combinational logic does not require clock and it is
the fastest shifter; Fig. 5.14 shows 4-bit barrel shifter and Table 5.5 shows operation
table for barrel shifter.

5.7 Frequency Divider Using J-K Flip-Flop

Figure 5.15 shows a J-K flip-flop as frequency divider; the inputs J and K are set to
1 and assume the initial value of Q ¼ 0; as shown in this figure, for every two clock
pulses applied to the flip-flop, then Q generates one clock pulse as shown in
Fig. 5.15; this means the circuit divides the frequency by 2.
5.7 Frequency Divider Using J-K Flip-Flop 103

Fig. 5.12 4-bit shift right register

Fig. 5.13 4-bit shift left register

Table 5.5 Barrel shifter S1 S0 D3 D2 D1 D0

operation
0 X A3 A2 A1 A0
1 0 0 A3 A2 A1
1 1 A2 A1 A0 0
104 5 Synchronous Sequential Logic

Fig. 5.14 4-bit barrel shifter

Fig. 5.15 Frequency divider using J-K flip-flop

5.8 Analysis of Sequential Logic

In a combinational logic, the truth table represents the characteristic of a function,

but characteristic of sequential logic is represented by state table. State table is
represented by present state, next state, and output. The present state is the current
state of the flip-flop (current output), and the next state is the output of flip-flop after
applying clock to the sequential logic. Figure 5.16 shows a sequential circuit with
two J-K flip-flops with two states A and B; the state table consists of two columns
present state and next state; present state represents current outputs of the flip-flops
with all possible values for A and B (00, 01, 10, and 11) as shown in Table 5.6.
Consider the first row; the present state is 00 (means A ¼ 0 and B ¼ 0); it is
interested to find the outputs of flip-flops (next state) by applying clock pulse. If
5.8 Analysis of Sequential Logic 105

Fig. 5.16 Sequential logic

Table 5.6 State table Present state Next state

for Fig. 5.16
A B A B
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0

A ¼ 0 and B ¼ 0 result in JA ¼ KA ¼ 0, JB ¼ KB ¼ 1, then applying clock pulse to

flip-flops results A ¼ 0 and B ¼ 1 (AB ¼ 01 next state).
Consider the second row, for present state A ¼ 0 and B ¼ 1; therefore,
JA ¼ KA ¼ 1, JB ¼ 0, and KB ¼ 1; applying a clock pulse to the flip-flops results
to next state with A ¼ 1 and B ¼ 0; the same procedure is used for row 10 and 11 to
find the next states. Table 5.6 shows state table for sequential logic of Fig. 5.16.
106 5 Synchronous Sequential Logic

Fig. 5.17 Sequential

circuit
DEV2
X
D Q A

C
Clock

Table 5.7 State table for Present state Next state for X ¼ 0 Next state for X ¼ 1
Fig. 5.17
A A A
0 0 1
1 1 0

Fig. 5.18 State diagram

Fig. 5.19 State diagram for

D flip-flop

Example 5.1 Find the state table of Fig. 5.17.

Figure 5.17 contains external input X, and Table 5.7 shows stable with two
columns for next state: one for X ¼ 0 and another one for X ¼ 1.

5.9 State Diagram

Another way to represent the characteristic of sequential logic is by state diagram,

as shown in Fig. 5.18. The present state is the current value of flip-flop, and
applying clock the present state changes to next state.
D Flip-Flop State Diagram Figure 5.19 shows state diagram of D flip-flop, and
the following steps describe state diagram:
5.10 Flip-Flop Excitation Table 107

Fig. 5.20 J-K and T flip-flops state diagrams

Table 5.8 Excitation table Q(t) Q(t + 1) D

for D flip-flop
0 0 0
0 1 1
1 0 0
1 1 1

1. If Q ¼ 0 (present state), by setting D ¼ 1 and applying clock, then Q changes

from 0 to 1 (next state).
2. If Q ¼ 1, by setting D ¼ 1 and applying clock, then output stays 1.
3. If Q ¼ 1, by setting D ¼ 0 and applying clock, then output changes to 0.
4. If Q ¼ 0, by setting D ¼ 0 and applying clock, then output stays 0.
Figure 5.20 shows state diagram of J-K and T flip-flops.

5.10 Flip-Flop Excitation Table

The application of excitation table is to determine input or inputs of a flip-flop in

order to get predefined output.
D Flip-Flop Excitation Table
Table 5.8 shows excitation table for D flip-flop: Q(t) is present output (present state)
and Q(t + 1) is the next state.
Excitation Table Operation Consider the first row of Table 5.8, if Q(t) ¼0 (pre-
sent state) and it is desired after applying a clock pulse, the output Q(t + 1) stays
0 and then D must be set to 0.
Consider the second row, the current output of D flip-flop (present state) is 0, and
it is desired to change the output Q (t + 1) to one; therefore, the input D must set to 1.
108 5 Synchronous Sequential Logic

Table 5.9 J-K flip-flop Q(t) Q(t + 1) J K

excitation table
0 0 0 d
0 1 1 d
1 0 d 1
1 1 d 0

Table 5.10 T flip-flop Q(t) Q(t + 1) T

excitation table
0 0 0
0 1 1
1 0 1
1 1 0

Consider the third row, the present output is 1, and it is desired to change the
output (next state) to 0; therefore the input D must be set to 0.
Consider the fourth row, the present state is 1, and it is desired to stay 1;
therefore, D must set to one.
J-K Flip-Flop Excitation Table
Table 5.9 shows J-K flip-flop excitation table, and the following steps describe how
this table was generated:
1. Consider the first row of excitation table, the present state of the flip-flop is zero,
and it desired to stay 0 by applying clock pulse; therefore, J must set to zero and
K is don’t care (0 or 1).
2. Consider the second row, the present state of the flip-flop is 0, and it is desired to
change the output to 1 by applying clock pulse; therefore, J must set to 1 and K
can don’t care.
3. Consider the third row, the present state Q(t) is 1, and it is desired to change it to
0; therefore, the J can don’t care and k ¼ 1.
4. Consider the fourth row, the present state is 1, and it is desired to stay 1;
therefore, J can don’t care and K ¼ 0.

T Flip-Flop Excitation Table. Table 5.10 shows excitation table of T flip-flop.

5.11 Counter

A counter is a sequential logic which is used to count the number of pulses applied
to it or divide a clock frequency if a system has a clock of 16 Hz, and it is possible to
use a counter to change 16 Hz clock to 4 Hz. The following steps describe how to
design a counter:
5.11 Counter 109

Table 5.11 State table of Present state Next state

counter
A B A B
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0

Table 5.12 Excitation table Present state Next state

for counter
A B A B JA KA JB KB
0 0 0 1 0 d 1 d
0 1 1 0 1 d d 1
1 0 1 1 d 0 1 d
1 1 0 0 d 1 d 1

(a) Define count sequence which is a sequence that the counter will count.
(b) Use count sequence to determine the number of flip-flops.
(c) Select the types of flip-flop.
(d) Use count sequence to develop state table.
(e) Use state table and flip-flop excitation table to develop excitation table for
counter.
(f) Use K-map to find the input functions or function to each flip-flop.
(g) Draw the sequential logic for the counter.
Example: Design a counter to count 0—1—2—3 and repeat using J-K flip-flops.
The biggest number in count sequence is 3 which is represented in binary by 11;
therefore, two flip-flops are needed and it is called A and B as shown in Fig. 5.22,
and Table 5.11 shows state table for the counter.
The present state defines the current output of flip-flops, and the next state is the
output of flip-flops after applying a clock pulse.
Table 5.12 shows excitation table for the counter which was developed by using
excitation table of JK flip-flop.
Consider the first row, the present output of J-K flip-flops is 00 (A ¼ 0, B ¼ 0),
and it is desired the outputs change to 01 (A ¼ 0 and B ¼ 1); therefore, it must set
JA ¼ 0, KA ¼ d (don’t care) in order for the A to stay 0 and set JB ¼ 1, KB ¼ d in
order for B to change from 0 to 1.
Consider the second row, the present state is 01 (A ¼ 0 and B ¼ 1), and it is
desired the output changes to 10 (A ¼ 1 and B ¼ 0); therefore, it must set JA ¼ 1,
KA ¼ d, and JB ¼ 0, KB ¼ d.
It is desired to find the input functions to the flip-flops, the present state are the
inputs, and JA, KA, JB, and KB are the outputs of the Table 5.12, by transferring the
outputs to the K-maps, and reading the K-maps results the input functions to the
flip-flops; Fig. 5.21 shows K-maps for JA, KA, JB, and KB.
The input functions to the flip-flops are JA ¼ JB ¼ B, JB ¼ B0 and KB ¼ 1, and
Fig. 5.22 shows the circuit of 2-bit counter.
110 5 Synchronous Sequential Logic

Fig. 5.21 K-maps for 2-bit counter

5.12 Summary

• Sequential logic circuit requires clock to operate.

• A S-R latch is the basic component for flip-flop.
• S-R latch can be constructed by the NAND or NOR gates.
• The basic element of sequential logic is flip-flop.
• Flip-flop is a memory element with the two outputs Q and Q0 .
• By applying clock to the D flip-flop, the value of the D input copies at the Q
output.
• D flip-flop use for designing register.
5.12 Summary 111

Fig. 5.22 Sequential logic

of 2-bit counter

• Register is a group of the D flip-flop sharing the same clock.

• J-K flip-flop is used for the designing counter.
• Connecting inputs of a J-K flip-flop together results a T flip-flop.
• State table and state diagram show operation of a sequential circuit.
• Chapter 6 is an introduction to computer architecture which covers basic com-
ponents of a microcomputer as well as CPU technologies, CPU architectures,
multicore processor, instruction execution steps, pipelining, and microcomputer
buses.
Problems 1. Complete the following table for D flip-flop.

D Q(t) present output Q(t + 1) next output

0 0
0 1
1 0
1 1
112 5 Synchronous Sequential Logic

2. Complete the following table for J-K flip-flop.

J K Q(t) present output Q(t + 1) next output

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

3. Complete the following table for T flip-flop.

T Q(t) present output Q(t + 1) next output

0 0
0 1
1 0
1 1

4. The following figure shows a sequential logic; complete the following table
assuming initial value of Q1 ¼ 0 and Q2 ¼ 0. Use logisim to verify your answer.

Clock Q0 Q1
Initial value 0 0
Clock #1
Clock #2
Clock #3

5. Show an 8-bit register using D flip-flops.

6. The following shift register given, find the output after five clock pulses.
5.12 Summary 113

Q3 Q2 Q1 Q0 Serial In
D3 D2 D1 D0
11000111
D D D D
Flip Flop Flip Flop Flip Flop Flip Flop
Clock

7. With the following sequential logic given, assume initial value for Q0 ¼ 0 and
Q1 ¼ 0, and flip-flop changes state in rising edge of clock pulse; complete the
following table and then use logisim to verify your result.

Clock Q0 Q1
Initial value 0 0
Clock #1
Clock #2
Clock #4
Clock #4

8. Complete the following excitation table for J-K flip-flop.

Q(t) Q(t + 1) J K
0 0
0 1
1 0
1 1

9. Design a counter to count 0—1—2—3—4—5—6—7 and repeat.

(a) Use J-K flip-flops.
(b) Use T flip-flops.
(c) Verify your design using logisim.
114 5 Synchronous Sequential Logic

10. Find the state diagram for the following state table.

AB AB
AB X¼0 X¼1
00 01 10
01 10 00
10 11 01
11 00 10

11. What is the content of the following register after shifting five times to the left?

12. Show state table and state diagram for following circuit.

X
JA A

B′
KB A

B
A
JB

KB B

Clock