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LAB00

The document summarizes the results of a lab assignment (LAB00) involving VHDL modeling and simulation. It discusses three types of VHDL design styles (dataflow, structural, behavioral) and provides examples of a 2-to-1 multiplexer modeled in each style. It also examines behavioral modeling of a 3-state multiplexer and truth tables/modeling of NAND and XOR gates. Simulation results are provided to verify the different designs match the expected logic functions. A testbench is developed and used to simulate a 2-input NAND gate by applying different input patterns and checking the output values.

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21021326 Phùng Mạnh Khang
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16 views6 pages

LAB00

The document summarizes the results of a lab assignment (LAB00) involving VHDL modeling and simulation. It discusses three types of VHDL design styles (dataflow, structural, behavioral) and provides examples of a 2-to-1 multiplexer modeled in each style. It also examines behavioral modeling of a 3-state multiplexer and truth tables/modeling of NAND and XOR gates. Simulation results are provided to verify the different designs match the expected logic functions. A testbench is developed and used to simulate a 2-input NAND gate by applying different input patterns and checking the output values.

Uploaded by

21021326 Phùng Mạnh Khang
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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LAB00 report.

Name: Phùng Mạnh Khang Student’s ID: 21021326


Assignment: LAB00 Group: 4

1. Getting Started
 1st question.
There are 3 types of VHDL design styles, namely dataflow, structural, and behavioral styles.

Figure 1: VHDL Design Styles


source [https://www.slideshare.net/BhupendraPratapSingh1/behavioral-modelling-in-vhdl]

- The VHDL design style of the mux2in1b.vhd is dataflow, because it describes the circuit by
describing how data flow in the circuit.

Figure 2: simulation result

 2nd question
In the mux2in1b_3state.vhd, it is clear that the design style of the multiplxer is behavioral
because the code describes the mux2 at the most abstract level, not gate or interconnected
gates.

Figure 3: The architecture part of the mux2in1

Figure 4: simulation result of the mux2in_3state.

2. NAND gate modeling example


 1st question
The truth table of the NAND gate is given below
Inputs Output
A B Z
0 0 1
0 1 1
1 0 1
1 1 0
Figure 5: the truth table of a NAND gate

From the truth table given above, the derived function of the NAND gate is:
 2nd question

Figure 6: Simulation result of the 2-input NAND gate.

Since the NAND gates has 2 inputs, there are 4 possible different inputs pair: 00,01,10,11.
Looking at the simulation results, it is clear that the outputs corresponding to the 4 inputs are 1,
1, 1, 0, which are the same as the results in the truth table ( Figure 3).

3. XOR3 gate in different design styles


 1st question
The truth table of the 3 inputs XOR gate is:
Inputs Output
A B C Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Figure 7: Truth table of a 3-input XOR gate

From the truth table given above, the derived function of the XOR gate with 3 inputs is:

or simply
 2nd question
The VHDL code of the 3 input XOR gate in dataflow style is:
Figure 8: Simulation result of 3-input XOR gate designed with dataflow style.

The VHDL code of the 3 input XOR gate in structural style is:

Figure 9: Simulation result of 3-input XOR gate designed with structural style.

The VHDL code of the 3 input XOR gate in behavioral style is:

Figure 10:Simulation result of 3-input XOR gate designed with behavioral style.

 3rd question
Looking at 3 simulation results of the XOR3 gate with 3 design styles, it is clear that the results of
each design styles is the same and similar to the outputs of the truth table given in Figure 5.
4. Simulation using testbench
 1st question

Figure 11: Simulation result of the 3-input XOR gate.

The test_vector(0), (1), (2) correspond to 3 inputs of the XOR gate A, B, C, respectively. Take the
test_vector 001, for example, the inputs A, B, and C would be 0, 0, 1. Based on the truth table
given in Figure 4, the output corresponding with 001 is 1.
 2nd question
The program below is the testbench for the 2-input NAND gate in Section 2.
library ieee;
use ieee.std_logic_1164.all;
entity nand_gate_tb is
end;

architecture sim of nand_gate_tb is


component nand_gate
port(a,b : in STD_LOGIC;
z: out STD_LOGIC);
end component;
signal a,b,z : STD_LOGIC;
begin
dut:nand_gate port map(a,b,z);
process begin
a <= '0' ; b <= '0' ; wait for 10ns;
a <= '0'; b <= '1' ; wait for 10ns;
a<='1';b<='0'; wait for 10ns;
a<='1'; b<='1'; wait for 10ns;

end process;
end;
Figure 12: testbench of the 2-input NAND gate.

Figure 13: Simulation result of the 2-input NAND gate.


Simulation results of circuits given in LAB00

Figure 14: Simulation result of mux2in1b

Figure 15:Simulation result of mux2in1_3state

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