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Lab 2

This document provides instructions for a lab experiment involving wire models, Elmore delay calculation, and coupling capacitance effects in VLSI circuit design. The lab consists of two parts: 1) measuring delay through different wire models and comparing to Elmore delay, and 2) examining crosstalk and delay under different coupling capacitance conditions between inverter outputs. Students are asked to simulate the provided circuit schematics in LTSPICE, record output waveforms, measure delays, and report results.

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Ahmed Shafeek
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19 views

Lab 2

This document provides instructions for a lab experiment involving wire models, Elmore delay calculation, and coupling capacitance effects in VLSI circuit design. The lab consists of two parts: 1) measuring delay through different wire models and comparing to Elmore delay, and 2) examining crosstalk and delay under different coupling capacitance conditions between inverter outputs. Students are asked to simulate the provided circuit schematics in LTSPICE, record output waveforms, measure delays, and report results.

Uploaded by

Ahmed Shafeek
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Ain Shams University Senior 1 Level / Spring 2022

Faculty of Engineering ECE314: VLSI Design


ECE Program Lab 2

Part 1: Wire Models & Elmore Delay


1. Open LTSPICE schematics: PC desktop\ECE314_VLSI\Lab2\part_one.asc.
2. Review that schematics includes 5 inverters loaded with wire models arranged in 5 rows as
follows:
Each of the top 3 inverters is loaded with a wire of total resistance of 50Ω and total
capacitance to ground of 100fF, one represented as single L-section, another represented as
single T-section, while the third is represented as single π-section. Hence, we can compare
the accuracy of such representations.
Each of the bottom 2 inverters is loaded with a simple wire tree with 2 branches, one
represented using L-sections while the other using π-sections. Hence, we can compare the
accuracy of such representations.
3. Include the technology model file:
“.include C:/Program Files (x86)/LayoutEditor/library/openCellLibrary/spicemodel.sp”.
4. Click RUN. Using the GUI, draw the waveforms at the outputs of the 5 cases on a single
graph. Take a snapshot of such graph and paste it in your lab report.
5. Measure the delay for each of the 5 cases:
Use the following delay measurement command 5 times (1 for each case),
“.meas tpd trig V(input_node_name)=0.5 Fall=1 targ V(output_node_name)=0.5 rise=1”,
then click RUN, and finally check results from View Spice Log.
6. In your lab report, compare delays of the first 3 cases to Elmore delay.
7. In your lab report, compare delays of the last 2 cases to Elmore delay.

Part 2: Coupling Capacitance Effects


1. Open LTSPICE schematics: PC desktop\ECE314_VLSI\Lab2\part_two.asc.
2. Review that schematics includes 3 cases:
Each case consists of 2 inverters having their load wires coupled with 100fF. (Note that wire
coupling capacitance is distributed similar to capacitance to ground. Hence, for a single π-
section, half is located at its input and the other half at its output).
Review the pulse sources of the 3 cases:
Case 1: One inverter is switching while the other is idle.
Case 2: Both inverters are switching in same direction.
Case 3: Both inverters are switching in opposite direction.
Hence, we can check crosstalk and compare the effect of coupled signal activity on delay.
3. Include the technology model file:
“.include C:/Program Files (x86)/LayoutEditor/library/openCellLibrary/spicemodel.sp”.
4. Click RUN. Using the GUI, draw the waveforms at the outputs of the 6 wires in the 3 cases
on a single graph. Take a snapshot of such graph and paste it in your lab report.
5. Measure crosstalk peak voltage for the idle inverter. Then, measure the five delays for the
other 5 switching inverters (similar to Part 1).
6. In your lab report, comment on crosstalk pulse shape and report its peak voltage.
7. In your lab report, compare delays of the 3 cases of coupled signal activity and calculate the
corresponding Elmore delay.

Make sure you put all your info on the report along with all required work.
Save the report file and upload it to LMS.
Delete created snapshots and log files and undo your changes to schematics.

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