VLSI Design

ECE314
Spring 2022
M4: Digital Building Blocks
Lecture 4
Memories
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

D. Khalil ECE314 – M4 Lecture 4 1

 Outline
• Memories
– Classifications
– Structure (Building Blocks)
– Memory core (Cells)

D. Khalil ECE314 – M4 Lecture 4 2

 Classifications
Memories can be classified based on different factors
Most important classification is based on:
• Read/Write ability: read-only vs. read-write
• Value retention: non-volatile vs. volatile
 3 main categories of memories: Non-volatile read-write memories,
(volatile) read-write memories, read-only memories
Other important classification is based on:
• Functionality: storage, portable storage, stand-alone, embedded,
cache, inside processor (instruction/data memory, register file)
• Access pattern: random vs. serial (FIFO, LIFO/stack, video)
• Storage mechanism: hard-wired vs. programmable vs. static vs.
dynamic
• I/O capability: single-port vs. multiple-port
• Addressability: byte, word, line

D. Khalil ECE314 – M4 Lecture 4 3

 Classifications
Examples of popular memories and their classification
Hard-Wired Programmable Static Dynamic
FIFO,
Serial
LIFO,
RWM Access
Video
SRAM DRAM
EPROM,
Random
NVRWM EEPROM,
Access
Flash
ROM ROM PROM

• Size, speed, and power are also very important parameters

in evaluating memories

D. Khalil ECE314 – M4 Lecture 4 4

 Basic Structure of Memory
• Memory core (storage cells)
Stores the values of N words, each of M bits,
in an NxM bit array (NxM is the size in bits)
• Peripherals
‒ Address decoder
Decodes K bits of address to N selectors
(called word-lines) to allow selecting only
1 word (line) of the core
‒ Sense amplifiers
Senses the voltage on vertical wires connecting
same bit in all words (bit-lines) to determine
the read value of the selected bit
‒ Drivers
Drives the voltage on vertical wires connecting same bit in all words
(bit-lines) to deliver the write value to the selected bit
‒ Control
Controls timing of different peripherals to ensure proper read/write

D. Khalil ECE314 – M4 Lecture 4 5

 Square Structure of Memory
• N/M is called Aspect Ratio (AR)
• As N increase, bit-lines
become much longer,
and limits performance
& size (to almost 512 bits)
• Improve design to have
large N by keeping
AR close to 1
• Divide long column to
multiple smaller ones
and select one of them
using column multiplexer
• Performance & size
limitation improved
(to almost 256 kbits)

D. Khalil ECE314 – M4 Lecture 4 6

 Hierarchical Structure of Memory
• Larger size is realized by combining multiple square structures
(blocks) into a larger memory with unified address and port
• Now some bits of the address are used to select a block
• Address is divided to 3 parts to select: a block, a column, and a line
• Block address can also be used save power by putting unselected
blocks in power saving mode

8Mbit SRAM
Byte addressable
Size=8x220=223bits
= 220B
Address=20bits
I/O-port=8bits
Max block size 256kbit
Block size=28x210=218
Row address=18/2=9
Column address=9-3=6
Block address=20-9-6=5

D. Khalil ECE314 – M4 Lecture 4 7

 Memory Cells – NOR ROM
• In ROM, a single MOSFET can
form a cell that represent 0 or 1
• In NOR ROM, the MOSFET is
placed as pull-down device
in a NOR gate
• When a word-line is selected,
it is high and all others are low
• If MOSFET exists,
the bit-line is pulled down
• If MOSFET does not exist,
the bit-line remains precharged
• Needs ground lines in parallel to
word-lines (takes area)

D. Khalil ECE314 – M4 Lecture 4 8

 Memory Cells – NAND ROM
• Another option is NAND ROM
• In NAND ROM, the MOSFET is
placed as pull-down device
in a NAND gate
• The word-lines have inverted logic
all are high except selected word
• If MOSFET exists,
the bit-line cannot be pulled down
• If MOSFET does not exist,
the bit-line is pulled down through
other MOSFETs
• Slower pull-down than NOR ROM
(many series MOSFETs)
• No needs for ground lines (saves area)
• More popular (less cost)

D. Khalil ECE314 – M4 Lecture 4 9

 Memory Cells – PROM / NVRAM
• A MOSFET with programmable VT would be very useful
to have programmable ROM
• When VT is normal, it can be ON as previously explained
• When VT is too high, it cannot be ON (as if it does not exist)
• Must have a mechanism to increase VT (write) and reduce it to
normal (erase) and read (like previously explained)
• Dual-gate MOSFETs are nice devices to achieve this
(like FAMOS, FLOTOX, and ETOX)
• Write mechanisms: Avalanche hot-e injection or tunneling
• Erase mechanisms: UV irradiation or tunneling
• Needs additional high supply 12V to 25V to slowly write/erase
• Can be used to create PROM
and NVRWM like EPROM, EEPROM, and Flash

D. Khalil ECE314 – M4 Lecture 4 10

 Memory Cells – SRAM (6T Cell)
• In volatile RWM (simply RAM),
some mechanism must allow
fast write/erase without
additional high supply
• Write/erase  write (0 or 1)
• In SRAM, 2 inverters are connected
back-to-back forming a static latch
that can store 0 or 1 & 2 MOSFETs
are used to access stored value to
either read it or force it to desired value
• To read: BL & BL are precharged to mid-voltage, WL is enabled to
access Q & Q, BL & BL change values slightly depending on them,
sense amplifier amplifies difference
• To write: BL & BL are driven to desired value, WL is enabled to
access Q & Q, driven value is forced
• SRAM read & write are very fast
D. Khalil ECE314 – M4 Lecture 4 11
 Memory Cells – DRAM (3T Cell)
• In DRAM, dynamic charge storage
replaces static latch
• Charge is stored on gate capacitance
of M2 altering the state of M2 (ON/OFF),
M1 is used to change stored value, and
M3 is used to read the stored value through
M2 drain rather than gate (to keep it safe)
• To read: BL2 is precharged to VDD, RWL is enabled to access M2,
BL is discharged/unchanged depending on X, sense amplifier
amplifies difference
• To write: BL1 is driven to desired value, WWL is enabled to access
X, X is charged/discharged to driven value
• Some other 3T variants exist
• Slower than SRAM but much smaller

D. Khalil ECE314 – M4 Lecture 4 12

 Memory Cells – DRAM (1T Cell)
• Smallest RAM cell is achieved by 1T DRAM
• Sometimes called 1T-1C DRAM (needs capacitor)
• Charge is stored on capacitor Cs
& M1 is used to access stored value
to either read it or force it to desired value
• To read: BL is precharged to mid-voltage, WL is enabled to access
X, BL is discharged/charged slightly depending on X, sense
amplifier amplifies BL difference, X becomes mid-voltage and need
to be refreshed, sense amplifier drives BL to read value to
charge/discharge X back to original value (refresh).
• To write: BL is driven to desired value, WL is enabled to access X,
X is charged/discharged to driven value
• Smallest and least cost RAM (very popular)
• Much slower and needs refresh after each read
and regularly due to leakage

D. Khalil ECE314 – M4 Lecture 4 13

 References

• Rabaey, section 12.1 & 12.2

D. Khalil ECE314 – M4 Lecture 4 14