1.

(A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveform. Synthesize the design by setting proper constraints and obtain the netlist. and
compare the value of the area, power, and timing analysis (before and after synthesis)
(i) 4 bit up/down counter
(B) Draw the schematic for the Inverter gate and verify the following
(i) DC Analysis (ii) Transient Analysis

2. (A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveform.
(i) 4 bit Adder
(B) Draw the schematic for NAND and verify the following
(i) Transient Analysis (ii) DRC (iii) LVS

3. (A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveforms. Synthesize the design by setting proper constraints and obtain the netlist.
and compare the value of area, power, and timing analysis (before and after synthesis)
(i) JK flip flop
(B) Common Source amplifier with pmos current mirror load
(i) AC analysis (ii) LVS

4. (A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveforms. Synthesize the design by setting proper constraints and obtain the netlist.
and compare the value of area, power, and timing analysis (before and after synthesis
(i) SR Flip Flop.
(B) Draw the schematic for Inverter and verify the following (select, Wn=2Wp )
(i) DC Analysis (ii) Transient Analysis (iii) LVS

5. (A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveforms. Synthesize the design by setting proper constraints and obtain the netlist.
and compare the value of area, power, and timing analysis (before and after synthesis)
(i) 4 bit UP counter
(B) Draw the schematic the 2 – input CMOS NAND gate
(i) Transient Analysis (ii) calculate the propagation delay

6. (A) Write Verilog code for the following circuits and its test bench for functional verification, observe
the waveforms.
(i) 32 bit ALU
(B) Draw the schematic for common source and verify the following
(i) AC Analysis (ii) DC gain and UGB
7. (A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveforms.
(i) 4 bit adder
(B) Draw the schematic for common source and verify the following
(i) AC Analysis (ii) DRC (iii) LVS

8. (A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveforms. Synthesize the design by setting proper constraints and obtain the netlist.
(i) SR Flip flop
(B) Draw the schematic for Inverter and verify the following (select, Wn=2Wp )
(i) DC Analysis (ii) Transient Analysis (iii) LVS

9. (A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveforms. Synthesize the design by setting proper constraints and obtain the netlist.
and compare the value of area, power, and timing analysis (before and after synthesis)
(i) 4 bit down counter
(B) Draw the schematic for Inverter gate and verify the following
(i) DC Analysis (ii) LVS

10.(A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveforms. Synthesize the design by setting proper constraints and obtain the netlist.
(i) D latch
(B) Draw the schematic for Common Source amplifier and verify the following
(i) AC Analysis (ii) Gain and UGB

11.(A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveforms. Synthesize the design by setting proper constraints and obtain the netlist.
(i) SR latch
(B) Draw the schematic for NAND gate, check the functionality and verify the following
(i) LVS

12.(A) Write Verilog code for the following circuits and its test bench for functional verification, observe
the waveforms. Synthesize the design and obtain the netlist.
(i) 4 bit adder
(B) Draw the schematic for common source and verify the following
(i) AC Analysis (ii) DC gain & UGB (iii) DRC
13.(A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveforms. Synthesize the design by setting proper constraints and obtain the netlist.
(i) D Flip flop
(B) Draw the schematic for Common Source amplifier and verify the following
(i) AC Analysis (ii) Gain and UGB
14.(A) Write Verilog code for the following circuits and its test bench code for functional verification,
observe the waveforms. Synthesize the design by setting proper constraints and obtain the netlist.
(i) SR Flip flop
(B) Draw the schematic for Inverter and verify the following (select, Wn=2Wp )
(i) DC Analysis (ii) Transient Analysis (iii) LVS