LAP reansctucors & Moasuromente (SU 2-20 __Slgnal Conditioning & Data Aq lvisition Bye 3 - 2.41 D/A Converters : _ The Mock diagram of a resistive type DAC Is shown in Pig. 2.111 ‘The basic building blocks of a DAC are ~ a resis contalled electronic syitches ve network, digitally 4 voltage reference and current to age con (A digital input Gode is applied to the resistive network vin the digitally controlled switches. Gi) The digitally (sand 1's), trolled_switehes are turned on or off by the digital input bits switches are turned on Gil) The output of the resistive network is in the form of current, It can be converted into a in the form of current Proportional voltage with the help of a current to voltage converter, Thus we obtain an onal voltage with the hel “urrent to voltage conver analog output voltage proportional to the digital input code. (iv) The actual digital to analog conversion takes place within the resi: ive network, Resistive Optional curont network output Digitally Ttov Analog output eooled convertor voltage V, switches lise Digital input Fig. 2.11.1 : Block diagram of a DAC DwA Depending on the type of resistive network used, we have different ty converter circuits. Some of them are : Binary weighted resistor DAC R - 2R ladder type DAC and Inverted R ~ 2R ladder type DAC. 2.11.1 Binary Welghted Resistor DAC : (1) The circuit diagram of binary weighted resistor type DAC is us shown in F ‘This circuit uses # network of binary weighted resistors and a summing amp tors 2'R, ZR, ....2°R ate from the network of biniy Weighted resistors,€ > be i, a, “a” number of electronic swi Tare OS SPD ee Switches used, Je double throw (SPD' : , ot mer " - am oo coatralled by Pn € switches. The posi oF ee They are single F ‘SPDT swi y the binary input word, For examplecif the hee er of every ae fist SPOT sich wil Somes resar2'8 to epnene aeae and v binary input d, is “0” then this swi pative re ay utd, is “O” then this switch will connect terenge vliage vo) ground. —\Thus an n-bit digital word will deci = bit decide the positi connect their corresponding binary wei eed Sela 5 0 ei . inary weighted resistors to either ~ V, _—S, Depending upon the Positions of various switches i Hier ~ Vp or ground. through the resistors 2'R to 2°R respectively as shown in Fig Sih ——— a AAR spectively as ill start flowing Tn aa We Binary weighted resistors Summing + ‘amplifier ~Vp (Reference voltage) 4d, (LSB) bd, $4, (MSB) js n-bitdigital input ——+ Fig. 2.11.2 : Weighted resistor DAC 2.11.1(A) Expression for Analog Output Voltage : () Let the n-bit digital input word to the DAC be dy d) .... d, with dy as MSB (most significant bit) and d, as LSB (least significant bit). Gi) Let Ry be the feedback resistor and I, be the output current. Let the OP-AMP in Fig. 2112 be an ideal OP-AMP so that the current flowing between its input terminals is zero. (iii) Assuming the OP-AMP of Fig. 2.11.2 to be ideal, the output current J, can be expressed as the sum of individual currents through the weighted resistors. Ve Ve Ve = thon +L BRat Rb ton t+ BR oe = DNote that dy, dy......d, can have a value of either “O” or (21D sty = MB ayo dy 22 eet dO wn(2.11.2) RL .AQ 3) is the required expression for output voltage. R (W) Let K =" and Vis = Vp So if R= R then K= Vo = Va (di 2" 44,2774 dy 2) 2114 ‘tut in Equation (2.11.4) we can obtain the vty =S By substituting the values of dy, d,..... d, in Equa of Corresponding analog output voltage V, ie 241 -(8) Drawbacks of Weighted Resistor DAC : @ The accuracy and stability of this type of DAC depends on the accuracy of the resisiis used, Gi) This type of DAC requires a wide range of resistor values, If the number of digits n pe = nd te 8 th. eat nain 4 : binary word is 8 then the smallest resistor is "x R=R Q, while the largest one ZR ie. 128 R'Q. Thus the largest resistor is 128 times, the smallest ‘One. This proporica will be worse for still higher values of n (say n= 12). = (ii) For n = 12, if the smallest tesistance is 2.5 KQ, then the largest one will k 2" X2.5 KQ = 5.12 MQ. The fabrication of such a large resistance in an IC fom isat ‘Practically possible. The smallest resistance o 2.5 KO. Te: annot be smaller than 2.5 KQ. Tiss necessary to avoid the loading effect. — ~ void the loading effect. Gv) The difficulty to achieve and maintain accurate Tatios over such a wide range of ris = ighted ys eh values restricts the use of weighted resistor DAC for the Values of n less than SS therefore the resolution of such a DAC is poor. nn (v) The finite resistan Reselation Poor ance of the switches will distur the currents particularly in th: most Significant bit (MSB) position where the current Setting resistors are small in value. 2.11.2 R-2R Ladder DAG: © The problem of using a wide ran ' ; th ising Be of resistor values can be solved by using the ® ladder type DAC, a. The circuit diagram for R-2R ladder w ° + lype DAC is shown in Fig, 2.11.3. Tt sho¥s only two Values of resisiors un red, of 84 © This method is therefore suituble for the integrated circuit realization. The valve Fig. 2.11.3 can be anywhere between 2.5kQ to 10 kQ. Good fer Integrated Crew vealteclionReference voltage (-Va) iLSB i é i :MSB Sdg=0 — édp=0 d= '+— Digital input 100 —»} Fig, 2.11.3 : R-2R ladder DAC 2.11.2(A) Operation of R-2R Ladder DAC : @ Refer to Fig. 2.11.3 where the number of digits per binary word is aoe (i.e. n= 3). The switch positions indicate that the binary word is d, d, d, = 100. (i) The original circuit can now be simplified as shown in Figs. 2.11.4 and 2.11.5 . respectively. Resistors in parallel 2 BRISR= AY Fig. 2.11.4 : Simplified R-2R ladder DAC + Gi) The simplified circuit shown in Fig. 2.11.4 gets further reduced to the simplified equivalent circuit shown in Fig. 2.11.5. The eq equivalent resi: nly “2R” and node A is at “virtual groun QA © a, © i ce to pine left of node “B” ; Rosistors in, L Resistors in parallel Resistors in f series R+R=2R aR ZAR series R+ R= 2A Fig. 2.11.5 : Simplified equivatent circuits to the left of B i(iv) wv) (vi) [FP transducers & Measurements (SU) 2-30 _ Signal Conditioning & Data Aquisiti Rosiotors in parallel 2A IIA = 23, > ground =) e-2Ro (a) Simplified equivalent circuit (b) Final equivalent circuit Fig. 211.6 The simplified equivalent circuit of an Fig. 2.11.6(a) is redrawn as shown in Va a ® Fig. 2.11.6(b). As the two resistorsR YR. and 2R ‘are in parallel with each Yo other, their parallel combination results in a resistance of 2. v Voltage at node Bis givenby, ya, 2A. B pig.2417 = —@R3)__ Vs = 3R+ QR) *~ VR Ra 2RI3} =Vr 7 Ve = [eRe ae spe (2115) 3 Considering the OP-AMP to be an inverting amplifier the equivalent circuit of the DAC is as shown in Fig. 2.11 Hence the output voltage is given by, QL) ‘Thus for a binary input of 100 the analog output produced is Vp /2- eee roduced is Vn. 2.11.2(B) Advantages of A/2R Ladder DACs : Because we need resistors of only two values, itis easier to build this circuit accurate —————— rere asier to build this We can ine! R/2R values- ‘The equivalent resistance to the right of each labelled node (A, B, C ..) will be ow 2R. Hence current flowing downwards, away from each node is equal to the © flowing towards right cate Due to the small resistance spread, (only 2 to 1) the R-2R ladder can be fab monolithically, with a high accuracy and stability,Ta Y 2.11.3 Inverted R-2R Ladder DAC : \dvantage of the weighted resistor DAC and R-2R ladder DAC is that the The main dis not remainyconstant. current flowing in different re Instead it will change with change in the digital input to DAC. This will cause more power dissipation in the resistors carrying more current which in turn causes heating of the resistors, ad The resistance value changes due to heating which will introduce non-linearity in DAC. This problem can be solved by using the “Inverted R-2R Inder” type DAC. The circuit diagram of a 3-bit inverted R-2R ladder type DAC is as shown in Fig. 2.11.8. This is called as “invert ladder DAC because the positions of MSB and LSB in ] the original R-2R ladder DAC have been interchanged. ‘The circuit shown in Fig. 2.11.8 is also called as the current mode R-2R ladder DAC. This is because this circuit operates on the ladder currents, 7 ®,8, © RF © 2 Electronic switches ‘Analog 4d, (MSB) 6 6 output 1, (MSB) Ody 6 d5(LSB) voltage Vo i Digital input ——w 2.11.3(A) Operation of the Circuit : @ Gi) ii) Thus both the terminals of each switch are at ground potential. Hence the currents (iv) | Fig. 2.11.8 : Inverted R-2R ladder DAC (current mode R-2R DAC) | | Fig. 2.11.8 shows a 3-bit inverted R-2R ladder type DAC. In this circuit each input binary word connects the corresponding switch to either ground or to the inverting terminal of the OP-AMP. Note that the inverting ( — ) terminal of the OP-AMP is at virtual ground poy flowing through the resistors will remain constant irrespective of the switch position i.e. independent of the input binary word. ~ The another important property of this circuit is that the total current gets divided | equally at each node. This is due to the fact that the resistance to the left and to the right lly at each no e | the left and to the right of each node is same, equal to 2R.ss ans SA Y, () Due to >-equal current division at cach node, the current in each branch of the R- AR lade Will remain constant, Duc to constant branch currents the ladder node voltages af, aed | Temain constant. The node voltages for Fig. 2.11.8 will be, ; i Vy Valo” Vy = Val2! ae independent of the binary inputs, These node voltages will remain constant, Expression for the output voltage V, : 1. The various currents shown in Fig. 2.11.8 are given by 2 eH er" ys =2R Ca) = 3G a = Re SEE Vo __Va_ _ and 1, = 98 =3RSF= RZ 2R © 2Rx 2! L either come from the ground point or from the virtual ground point. dh+d,h+ah Vv ake RB forty 4277b+27b] 3. Sothe output voltage is given by, a, R 7 - = = SRlX Ve [b, 21 +b,27 +b, 27] 4 ‘We can substitute — (Rz/R) = K to get V. = K Vp [bj 2'+b, 27? +b, 2°] %. Due to the constant node voltages, the stray capacitances cannot produce the “S!# down" effect on the performance of the DAC circuit. This is the biggest advantage a the inverted R-2R ladder DAC. 2.11.38) Advantages of Inverted R-2R Ladder DAC : : Current flowing through resistors remain Constant irrespective of the switch position. 2 Tota! current gets gets divided equally at each node, 3, Current ‘ $s ve ag branch of R-2R ludder will remain constant and the node voltages 4. The “slow down" effect le 10 stray Capacitance is not present. 2.11.4 Sources of Errore in DAC; =f. There are tree type of ettors present in the transfer characteristics of DACs. They &* linearity, offset and gain erro errors. LeU discuss them one by one.Linearity Errol <> This is defined as the amount by which the actual output of a DAC differs from the ideal serait Hine transfer characteristics. This error is introduced due to the error in the current source resistance values. Fig. 2.11.9(a) shows the linearity error in the transfer characteristics ofa DAC. offset Error = ~~ When all the digital inputs are 0, the analog output also is expected to be 0. But practically it does not happen. «As shown in Fig. 2.11.9(b) some non-zero analog output voltage is present even for a zero digital input. ace « This is called as the offset error. Thus the offset error is defined as the non-zero level of analog output when all the digital inputs are 0. The offset error is due to the offset voltages of OP-AMPs and leakage currents in the switches. output Output Ideal (Linear) ideal] 718 718 Practical] Practical 1 tnoarty error Input Input (a) Linearity error in transfer characteristics (b) Offset error in transfer characteristics of D/A converter of a D/A converter Fig. 2.11.9 Gain Error : * Ina DAC we _use_a current to voltage converter. The gain of this converter determines the analog output voltage of the DAC. The gain error is defined as the difference between the calculated _gain and Practically obtained gain of the I to V converter. ~ aaa This error exists due to the error in the feedback resistor value. The gain error is as shown in Fig. 2.11.9(c). Fig. 2.11.9(c) : Gain error in the transfer characteristics of a D/A converteramy ees MR RY 2 I PUEDE OSs noarty EXror ¢ ‘This is defined as the amount by which the actual output of a DAC differs from the ideal sqaight line transfer characteristics. This error is introduced due to the error in the current goorce resistance ValUcs. Fig. 2.11.9(a) shows the linearity error in the transfer characteristics ofa DAC. offset Error : + When all the digital inputs are 0, the analog output also is expected to be 0. But practically it does not happen. + As shown in Fig, 2.11.9(b) some non-zero analog o zero digital input. «This is called as the offset error. Thus the offset as th analog output when all the digital inputs are 0. The offset error is due to the offset voltages of OP-AMPs and leakage currents in the switches. Output Output Teeal (Unea) Idea 718 78 Practical Practical (Non-tinean)| 28 [7] Unearity error Gis Ta a Input a Input (2) Linearity error in transfer characteristics _—_(b) Offset error in transfer characteristics of D/A converter of a D/A converter Fig. 211.9 Gain Error: . Output In a DAC we use a current to voltage converter. The gain of this converter determines the analog output voltage of the DAC. ‘The gain error is defined as the difference between the calculated gain and Practically i of the I to V converter, This error exists due to the error in the feedback resistor value. The gain error is as shown in Fig. 2.11.9(c). 0 718 418 218 Input Fig. 2.11.9(c) : Galn error In the transfer characteristics of a D/A converter