Combinational logic circuits

Mrs. M.S. Ranade

HOD Computer Engineering Department
Classification of digital circuits
Digital circuits are classified into two categories
• Combinational logic circuits
• Sequential logic circuits

A1 Y1
A2 Y2
Combinational circuit
An Ym

A combinational circuit consists of input variables,

logic gates, and output variables
 Combinational logic circuits

• In combinational circuits output at any instant

depends on input applied at that instant
• Combinational circuits do not require any memory
• For n input variables, there are 2n possible binary
input combinations.
• For each binary combination of the input variables,
there is one possible output
Combinational logic circuits continued
•A combinational circuit can be described by:
 A truth table that lists the output values for each
combination of the input variables, or
 m Boolean functions, one for each output variable

•In any engineering design number of components used

should be minimum to ensure low cost, saving in space, power
requirement etc

•Methods used to simplify Boolean Equations

Algebraic method : depends on inspiration and
experience
Karnaugh map (K map) simplification : systematic, step-
by-step approach.
 SOP and POS representation for
logical expressions
• Logical functions are expressed in terms of logical
variables

• Any logical function can be expressed conveniently

in following forms
Sum of products (SOP)
Product of sums (POS)
 SOP and POS representation for
logical expressions continued
• Sum : OR operation
• Product : AND operation
• Each sum-of-products expression consists of two
or more AND terms that are ORed together
• Example : A.B + A.B.C
• Each product-of-sums expression consists of two
or more OR terms that are ANDed together
• Example : (A+B+C).(A+C)
 Standard SOP and POS forms
• When each term used in logical function/expression
contains all available input variables/literals in
complemented or uncomplemented form, the logic
expression is known as Standard SOP or POS
expression
• Example :
Standard SOP Y = A.B.C + A’.B.C’ + A.B.C’
Standard POS Y = (A+B’+C). (A’+B+C’)
Conversion of logical expression to
Standard SOP forms

Steps to be followed
1. For each term in given logical expression, find the
missing literal
2. AND each term with the term formed by ORing the
missing literal and its complement
3. Simplify the expression to get standard SOP form
Conversion of logical expression to
Standard SOP forms continued
Convert Y = AB + AC’ + BC to Standard SOP
Y = AB + AC’ + BC

Missing literals C B A

Y = AB(C+C’)+AC’(B+B’)+BC(A+A’)
= ABC+ABC’+ABC’+AB’C’+ABC+A’BC
= ABC+ABC’+AB’C’+A’BC
Conversion of logical expression to
Standard SOP forms continued
Convert Y = A’ + BCD’ to Standard SOP
Y = A’ + BCD’

Missing literals B,C,D A

Y = A’(B+B’)(C+C’)(D+D’)+BCD’(A+A’)
= (A’B+A’B’)(CD+CD’+C’D+C’D’)+
ABCD’+A’BCD’
= A’BCD+A’BCD’+A’BC’D+A’BC’D’+
A’B’CD+A’B’CD’+A’B’C’D+A’B’C’D’+
ABCD’+A’BCD’
= A’BCD+A’BCD’+A’BC’D+A’BC’D’+A’B’CD
+A’B’CD’+A’B’C’D+A’B’C’D’+ABCD’
Conversion of logical expression to
Standard POS forms
Steps to be followed
1. For each term in given logical expression, find the
missing literal
2. OR each term with the term formed by ANDing the
missing literal and its complement
3. Simplify the expression to get standard SOP form
Conversion of logical expression to
Standard POS forms continued
Convert Y = (A’+B).(B+C’).(A’+C’) to Standard POS
Y = (A’+B).(B+C’).(A’+C’)

Missing literals C A B
Y = (A’+B+CC’).(B+C’+AA’).(A’+C’+BB’)
= (A’+B+C)(A’+B+C’)(A+B+C’)(A’+B+C’)
(A’+B+C’)(A’+B’+C’)
= (A’+B+C)(A’+B+C’)(A+B+C’)(A’+B’+C’)
• There is a complementary relationship between the functions
expressed in terms of minterms and maxterms
 Concept of minterm and maxterm
• Each individual term in standard SOP form is called as
minterm. Each minterm is denoted by mi.
• Each individual term in standard POS form is called as
maxterm. Each maxterm is denoted by Mi.
• Minterms are obtained by applying the inputs to AND
gate to obtain high (logical 1) output
• Maxterms are obtained by applying the inputs to OR
gate to obtain low (logical 0) output
• For n variables, number of minterms or maxterms is 2n
minterms and maxterms for 3 variables

Input variables minterms maxterms

A B C mi Mi
0 0 0 m0 = A’B’C’ M0 = A+B+C
0 0 1 m1 = A’B’C M1 = A+B+C’
0 1 0 m2 = A’BC’ M2 = A+B’+C
0 1 1 m3 = A’BC M3 = A+B’+C’
1 0 0 m4= AB’C’ M4 = A’+B+C
1 0 1 m5 = AB’C M5 = A’+B+C’
1 1 0 m6 = ABC’ M6 = A’+B’+C
1 1 1 m7 = ABC M7 = A’+B’+C’
How to write SOP expression from
given truth table
• For writing SOP expression
inputs Output consider the input combinations
A B C Y where output Y= 1
0 0 0 0
• Obtain fundamental product
0 0 1 1
term/minterm for each
0 1 0 1
combination
0 1 1 0
• OR all these terms to get SOP
1 0 0 0
expression
1 0 1 1
1 1 0 0
• Y= A’B’C+A’BC’+AB’C+ABC
1 1 1 1 = m1+m2+m5+m7
= Ʃ m(1,2,5,7)
How to write POS expression from
given truth table
• For writing POS expression consider the input
combinations where output Y= 0
• Obtain fundamental sum term/maxterm for each
combination
• AND all these terms to get POS expression
• Y= (A+B+C).(A+B’+C’).(A’+B+C).(A’+B’+C)
= M0.M3.M4.M6
= Π M(0,3,4,6)
 Karnaugh map(K-map)
simplification technique
• It is a graphical technique
• It provides systematic method for simplifying
Boolean expression
• Information available in truth table or SOP/POS form
can be represented using K-map
• K-maps can be drawn for 2,3,4,5,6 input variables
• It is easy to convert a truth table to k-map and k-map
to SOP/POS form equation.
 K-map
• K-map can be drawn as an array containing 2n cells in
a grid like format, where n is the number of variables
in the Boolean expression that is to be reduced or
optimized
• As it is evaluated from the truth table, each cell in the
K-map will represent a single row of the truth table
• The k-map consists of variables and their complements
in vertical columns and horizontal rows
• Columns/rows in the k-map are labeled in such a way
that only one variable changes from complemented to
uncomplemented form
 2 variable K-map

Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
 3 variable K-map

Inputs Output
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
 4 variable K-map
Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
 K-map simplification (SOP)
• K- map contains pairs, quads & octets
• 1’s that are horizontally/vertically adjacent form a pair. In
pair only one variable goes from complemented to
uncomplemented form. Other variable doesn’t change.
We can eliminate the variable that changes the form
• Quad is a group of four 1’s that are horizontally/vertically
adjacent. Quad eliminates two variables and their
complements
• Octet is a group of eight 1’s. It eliminates three variables
and their complements
 K-map simplification continued
•After drawing k-map encircle octets first, then
quads, then pairs, check if any 1 is yet to be
encircled (encircle isolated 1’s)
•You can use same 1 more than once (overlapping
groups)
 K-map simplification continued
•If the map is rolled such that left side touches the right
side/top touches the bottom 1’s on the edge of k-map can
be grouped with 1’s on opposite edge
•Redundant groups should be eliminated (redundant group
is a group whose all 1’s are already used by other groups
•Write Boolean equation by Oring products corresponding
to encircled groups
 K-map simplification continued
Minimize following Boolean expression using k map. Draw
logic diagram of minimized expression using logic gates
Y = ∑m(1,3,5,7,8,10,14)
 Don’t care condition
• In some digital circuits certain input conditions never occur
during normal operation, therefore corresponding output never
appears. Hence it is indicated by x in the truth table
• This x is called as don’t care condition
• It can be considered as 0 or 1 whichever produces simpler
logic circuit
In case of don’t care conditions
• Draw k map with 0’s, 1’s, don’t cares from given truth table
• Encircle actual 1’s on k map in largest group by treating don’t
cares as 1’s
• After including actual 1’s in groups,disregard remaining don’t
cares by visualizing them as 0’s
 Don’t care condition continued
Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
 K-map simplification (POS)
• We can easily convert a truth table to k-map and k-map to
standard POS expression.
• Minimize following expression using k map and realize using
NOR gates F(A,B,C,D) = ∏M(0,1,5,10,11,13,14,15)
 Half adder
A combinational circuit that performs addition of two
single bits is called a half adder. It has two inputs A & B
and two outputs sum(S) &carry(C)
Truth table of half adder
A Sum Inputs outputs
H.A.
B Carry
A B Sum(S) Carry(C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
 Half adder continued
From truth table we can draw From the Boolean equations
K maps for half adder obtained, half adder can be
implemented using EX-OR
gate & AND gate
 Half adder continued

Half adder using basic gates Half adder using universal gates
 Full adder
A combinational circuit that performs addition of two single bits
along with carry generated from lower order bits is called as full
adder. It has three inputs A ,B & Cin and two outputs sum(S)
&carry(C)

A S

B FA
Cin C
 Full adder continued
Truth table of full adder
Inputs Outputs
A B Cin Sum(S) Carry (C)

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Full adder continued

Full adder using basic gates Full adder using universal gates
 Full adder continued

Full adder using two half adders and

OR gate
Full adder using EX-OR gate
 Half subtractor
A combinational circuit that performs subtraction of two
single bits is called a half subtractor. It has two inputs A & B
and two outputs Difference(D) & Borrow(Bout)

Truth table of half subtractor

Inputs outputs
A Difference
H.S. A B Difference Borrow
B Borrow (D) (Bout)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
 Half subtractor continued
From truth table we can draw K From the Boolean equations
maps for half subtractor obtained, half subtractor can be
implemented using EX-OR gate
NOT gate & AND gate
 Half subtractor continued

Half subtractor using basic gates Half subtractor using universal gates
 Full subtractor
A combinational circuit that performs subtraction of two
single bits along with borrow from previous bit is called
as full subtractor. It has three inputs A ,B & Bin and two
outputs Difference(D) & Borrow(Bout)

A D

B F.S.
Bin Bout
 Full subtractor continued
Truth table for full subtractor
Inputs Outputs
A B Bin Difference Borrow
(D) (Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
 Full subtractor continued

Full subtractor using two half

Full subtractor using EX-OR gate
subtractors and OR gate
 Binary to Gray converter
Binary code Gray code
Decimal
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0 0
Binary Gray 1 0 0 0 1 0 0 0 1
inputs outputs 2 0 0 1 0 0 0 1 1
B3 G3 3 0 0 1 1 0 0 1 0
B2 Bonary to G2 4 0 1 0 0 0 1 1 0
B1 Gray converter G1 5 0 1 0 1 0 1 1 1
B0 G0
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
1010 binary number 10 1 0 1 0 1 1 1 1

1111 gray number 11 1 0 1 1 1 1 1 0

12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Binary to Gray converter continued
 Binary to Gray converter continued
G3 = B3
G2 = B3 + B2
G1 = B2 + B1
G0 = B1 + B0
 Gray to Binary converter
Gray code Binary code
Decimal
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0

Gray Binary 1 0 0 0 1 0 0 0 1

inputs outputs 3 0 0 1 1 0 0 1 0

G3 B3 2 0 0 1 0 0 0 1 1

G2 Gray to Binary B2 6 0 1 1 0 0 1 0 0
G1 converter B1 7 0 1 1 1 0 1 0 1
G0 B0 5 0 1 0 1 0 1 1 0
4 0 1 0 0 0 1 1 1
12 1 1 0 0 1 0 0 0
13 1 1 0 1 1 0 0 1
15 1 1 1 1 1 0 1 0
1101 gray number 14 1 1 1 0 1 0 1 1
1001 binary number 10 1 0 1 0 1 1 0 0
11 1 0 1 1 1 1 0 1
9 1 0 0 1 1 1 1 0
8 1 0 0 0 1 1 1 1
Gray to Binary converter continued

B2 = G3’G2 + G3G2’
B3 = G3

B1 = G3’G2’G1+ G3’G2G1’ B0 = G3’G2’G1’G0 + G3’G2’G1G0’ +

+ G3G2G1 +G3G2’G1’ G3’G2G1’G0’ + G3’G2G1G0 + G3G2G1’G0
+ G3G2G1G0’ + G3G2’G1’G0’ + G3G2’G1G0
 Gray to Binary converter continued
B3 = G3
B2 = G3’G2 + G3G2’ = G3 + G2
B1 = G3’G2’G1+ G3’G2G1’ + G3G2G1 +G3G2’G1’
= G3 + G2 + G1
B0 = G3’G2’G1’G0 + G3’G2’G1G0’ + G3’G2G1’G0’ + G3’G2G1G0 +
G3G2G1’G0 + G3G2G1G0’ + G3G2’G1’G0’ + G3G2’G1G0
= G3 + G2 + G1 + G0
 Arithmetic circuits - Adder

• Full adder is used to add two single bit binary numbers

along with carry
• In practice we have to perform multi bit addition e. g. 4
bit, 8 bit, 16 bit etc.
• For 4 bit addition we have to use 4 full adders in
cascade
• Carry output of lower bit adder is connected to carry
input of higher bit adder
Arithmetic circuits – Adder continued

Here 4 bit binary number A (A3A2A1A0) is added to 4 bit

binary number B (B3B2B1B0) to get 4 bit sum
S(S3S2S1S0) and carry out (Cout)
 IC 7483
• Such 4 bit parallel adder is available in the form of an integrated
circuit (IC 7483) .
• It is TTL MSI 4 bit parallel adder.
• It consists of two 4 bit input operands(A3A2A1A0 & B3B2B1B0),
Cin is carry input, Cout is carry output, S3S2S1S0 represents sum
output
 4 bit binary adder using IC 7483
• Here Cin is connected to ground
• Addition of two 4 bit numbers A & B is available at
output
 Cascading of adders
• Two 8 bit numbers can be added by cascading two 4 bit adders
• Adder1 adds 4 LSB bits (B3-B0) & (A3-A0)
• Cin of adder1 is connected to ground
• Cout of adder1 is connected to Cin of adder2
• Adder2 adds 4 MSB bits (B7-B4) & (A7-A4)
• Cout of adder2 is final carry output, sum output is S7-S0
4 bit binary subtractor using IC 7483
• 1’s complement or 2’s complement subtraction can be performed using
IC 7483
• For 2’s complement subtraction number A is connected as it is. Number
B is passed through inverters to obtain 1’s complement. Cin = 1. i.e. 1
is added to 1’s complement of B to get 2’s complement. Therefore 7483
adds A and 2’s complement of B to produce subtraction at S output
(S3S2S1S0). Cout represents sign of output
• If A>B, Cout = 1, result is positive and is in true binary form
If A<B, Cout = 0, result is negative and is in 2’s complement form
 4 bit binary adder/subtractor

• This circuit acts as adder/subtractor depending upon mode select

input
• Number A is applied directly while number B is applied through
EX-OR gates
• One input to each EX-OR gate is mode select input
4 bit binary adder/subtractor continued
• If M = 0 number B is applied as it is to IC 7483,
Cin = 0 and the circuit acts as adder.
• If M = 1 number B is inverted & applied to IC 7483,
Cin = 1, hence 2’s complement of B is added to A,
circuit acts as subtractor.
 BCD adder using IC 7483
• IC 7483 can be used for addition of BCD numbers
• Two BCD numbers are added using rules of binary addition
• If sum is less than or equal to 9 & carry = 0, then no correction
is necessary
• If sum is greater than 9 or carry = 1, correction factor (0110)
should be added to the answer
• Hence 4 bit BCD adder should consist of
 4 bit binary adder to add given BCD numbers A & B
 A combinational circuit to check whether sum>9 or carry = 1
 Another 4 bit adder to add correction factor (0110) if answer is
incorrect
• The output of combinational circuit should be 1 if sum
produced by adder1 is greater than 9 or Cout =1
BCD adder using IC 7483 continued
Inputs ( sum output of adder1) output
S3 S2 S1 S0 Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
 BCD adder using IC 7483 continued

Output of combinational circuit should be 1 if Cout of adder1 = 1

or output of adder1 > 9
Therefore output Y is Ored with Cout of adder1
Output of combinational circuit is connected to B2B1 inputs of
adder2 & B3B0 are connected to ground i.e. B3B2B1B0 = 0110
 Multiplexer
• Multiplexer is a combinational logic circuit which has several
inputs (n) and a single output
• It selects one of the data input and connects it to output
• It is analogous to rotary switch
• Selection of particular input line is controlled by set of select
input lines (m)
• To select n inputs, m select lines are required such that 2m = n
• A strobe or enable input helps in cascading. It is generally
active low i.e. it performs intended operation when it is low
 Multiplexer continued

n:1multiplexer Multiplexer as rotary switch

 4:1 Multiplexer
• 4:1mux has 4 data input lines, 2 select inputs,1output line and a
strobe/enable input
• One of the data input line is selected according to select input
and is connected to output Y
• Truth table for 4:1 mux is as shown
• With low input at G (strobe/enable)
output Y = S1’S0’D0 + S1’S0D1 + S1S0’D2 + S1S0D3
 4:1 Multiplexer continued
The output expression Y = S1’S0’D0 + S1’S0D1 + S1S0’D2 + S1S0D3
can be implemented using basic gates /universal gates (NAND
gates)
 8:1 Multiplexer
• 8:1mux has 8 data input lines, 3 select inputs,1output line and a
strobe/enable input
• output Y = S2’S1’S0’D0 + S2’S1’S0D1 + S2’S1S0’D2 + S2’S1S0D3
+ S2S1’S0’D4 + S2S1’S0D5 + S2S1S0’D6 + S2S1S0D7

Select inputs Output

S2 S1 S0 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
8:1 Multiplexer continued

• 8:1 mux can be

implemented using basic
gates as well as universal
gates
 16:1 Multiplexer
• 16:1mux has 16 data input lines, 4 select inputs,
1output line and a strobe/enable input
• output Y = S3’S2’S1’S0’D0 + S3’S2’S1’S0D1 +
S3’S2’S1S0’D2 + S3’S2’S1S0D3 + S3’S2S1’S0’D4 +
S3’S2S1’S0D5 + S3’S2S1S0’D6 + S3’S2S1S0D7
+S3S2’S1’S0’D8 + S3S2’S1’S0D9 + S3S2’S1S0’D10 +
S3S2’S1S0D11 + S3S2S1’S0’D12 + S3S2S1’S0D13 +
S3S2S1S0’D14 + S3S2S1S0D15
16:1 Multiplexer continued
Select inputs Output
S3 S2 S1 S0 Y
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7
1 0 0 0 D8
1 0 0 1 D9
1 0 1 0 D10
1 0 1 1 D11
1 1 0 0 D12
1 1 0 1 D13
1 1 1 0 D14
1 1 1 1 D15
 Multiplexer applications
Applications
• It is used as data selector
• It is used for simplification of logic design
• It is used in data acquisition system
• It is used in D/A converter
• It is used in design of combinational circuits
Multiplexer tree
• Multiplexer with more number of inputs can be obtained by
cascading two or more multiplexers with less number of
inputs. It is called as multiplexer tree.
8:1 Multiplexer using 4:1 Multiplexer

• 8:1mux can be implemented using two 4:1 mux and OR gate

• Eight data inputs are D0-D7
• Select inputs S0 and S1 of both mux are connected together. Third select
input S2 is formed by using enable input
• S2 is connected directly to enable input of mux1 and through inverter to
enable input of mux2
• Outputs of both mux are Ored to obtain output Y
16:1 Mux using 4:1 Multiplexers
 Mux Example

• Implement following logic

expression using 16:1 mux
Y = ∑ m (0,3,5,7,8,9,12,13)
• Connect data inputs
corresponding to these
minterms to logic 1 and
remaining data inputs to
logic 0
 Mux Example
• Realize logic function of
given truth table using mux
 Multiplexer IC
• The TTL/MSI 74151 is a
high speed 8-input Digital
Multiplexer.
• It provides, the ability to
select one bit of data from up
to eight sources.
• Both true and complement
outputs are provided.
• Z = e (S2’S1’S0’I0 +
S2’S1’S0I1 + S2’S1S0’I2 +
S2’S1S0I3 + S2S1’S0’I4 +
S2S1’S0I5 + S2S1S0’I6 +
S2S1S0I7)
 Demultiplexer
• Demultiplexer is a combinational logic circuit which has
single input and a many outputs (n)
• Input signal is transmitted to one of the many outputs
depending on select input signal
• It performs reverse operation of a mux
• For distributing input signal over one of the n output lines, set
of (m) select input lines is required such that 2m = n
• A strobe or enable input helps in cascading. It is generally
active low i.e. it performs intended operation when it is low
• Demux is equivalent to single pole multiple way switch
Demultiplexer continued
 1 : 4 Demultiplexer
• 1:4 demux has 1data input line, 2 select inputs, 4 output lines and
a strobe/enable input
• The data input line is connected to one of the output lines
according to select inputs
• Truth table for 1:4 demux is as shown
• With low input at G (strobe/enable) output is given as
Y0 = S1’S0’D Y1 = S1’S0D Y2 = S1S0’D Y3 = S1S0D
 1 : 4 Demultiplexer continued

The outputs :
Y0 = S1’S0’D
Y1 = S1’S0D
Y2 = S1S0’D
Y3 = S1S0D
can be implemented using
basic gates or universal
gates
 1 : 8 Demultiplexer
1:8 demux has 1 data input line, 3 select inputs,8output lines and a
strobe/enable input

Truth table
Select inputs outputs
S2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 D
0 0 1 D
0 1 0 D
0 1 1 D
1 0 0 D
1 0 1 D
1 1 0 D
1 1 1 D
 1 : 8 Demultiplexer continued
The outputs of 1:8 demux are
as follows
Y0 = S2’S1’S0’D
Y1= S2’S1’S0D
Y2 = S2’S1S0’D
Y3 = S2’S1S0D
Y4 = S2S1’S0’D
Y5 = S2S1’S0D
Y6 = S2S1S0’D
Y7 = S2S1S0D7
1:8 demux can be
implemented using basic gates
as well as universal gates
 1 : 16 Demultiplexer
1:16 demux has 1 data input line, 4 select inputs, 16 output lines and a
strobe/enable input
The outputs are as follows
Y0 = S3’S2’S1’S0’D
Y1 = S3’S2’S1’S0D
Y2 = S3’S2’S1S0’D
Y3 = S3’S2’S1S0D
Y4 = S3’S2S1’S0’D
Y5 = S3’S2S1’S0D
Y6 = S3’S2S1S0’D
Y7 = S3’S2S1S0D
Y8 = S3S2’S1’S0’D
Y9 = S3S2’S1’S0D
Y10 = S3S2’S1S0’D
Y11 = S3S2’S1S0D
Y12 = S3S2S1’S0’D
Y13 = S3S2S1’S0D
Y14 = S3S2S1S0’D
Y15 = S3S2S1S0D15
 Demultiplexer IC
• Dual 1:4 demux with common select
inputs, separate enable inputs
• Each demux has active low outputs
• Both demux have two input enable
gate
• Decoder a enable gate requires one
active high input & one active low
input
Ea, Ea’ : enable a
• Decoder b enable gate requires two
A1, A0 : select inputs active low inputs
0a’-3a’ : output of mux1
0b’-3b’ : output of mux2
Eb’,Eb’ : enable b
 Demultiplexer tree
Similar to multiplexer tree we can construct demux tree i.e.
demultiplexer with more number of outputs can be obtained by
cascading two or more demultiplexers with less number of outputs
 1:64 Demux using 1:16 Demux

• We can construct 1:64

demux using four 1:16
demux and one 1:4 demux
• Here S0-S5 are select inputs
• Y0 -Y63 are outputs
• Din is data input
 Demux example
Implement full adder using demux
Truth table of full adder

Expressions for sum & carry

S = ∑ m (1,2,4,7) C = ∑ m (3,5,6,7)
 Comparison of Mux and Demux
Sr. No. parameter Mux Demux
1 Type of logic circuit combinational combinational
2 Number of data inputs n 1
3 Number of select inputs m m
4 Number of data outputs 1 n
5 Relation between input/output 2m = n 2m = n
lines and select lines
6 Principle of operation Many to 1/as data 1 to many /as data
selector distributor
7 application We can implement We can implement
combinational combinational
circuits using mux circuits using demux
 Encoders & Decoders
• Wide variety of codes are used in digital systems e.g.
BCD, excess-3, gray, octal, binary etc.
• Many times it is required to convert one form of code to
another form. Hence code converter is necessary
• A digital circuit which converts data expressed in one
code to another is called code converter
• There are two types of code converters
– Encoders
– Decoders
• MSI Ics are available for performing these conversions
 Encoders
• The process of generating binary codes is called encoding
• Different types of encoders like decimal to BCD, octal to
binary, hex to binary are used in digital systems
• Encoder has n input lines & m output lines
• Only one input line is active
• This input is coded to binary output of m bits
 Octal to binary(8:3)Encoders
• Octal to binary encoder has 8 input lines and 3 output lines
• For an octal number we get three bit binary output
• Only one input is active at a time

Logical expressions for output

A = D4+D5+D6+D7
B = D2+D3+D6+D7
C = D1+D3+D5+D7
 Decoders
• Decoder is a combinational circuit
• It has n inputs & to a maximum 2n outputs
• Decoder is similar to demux without any data input
• It performs exactly opposite operation to that of
encoder
 3 : 8 Decoder
•It has 3 input lines and 8 output lines
•One of the output line will be activated depending upon applied
input

Truth table

Logic diagram
 BCD to 7 segment Decoder continued
• 7 segment display is popular display device in digital systems
• To display data using 7 segment display, available BCD data
should be converted to 7 segment code
• MSI chip is available for this conversion
• BCD to 7 segment decoder/driver has 4 input lines and 7
output lines
• It accepts 4 bit BCD input and converts it to 7 bit code suitable
for 7 segment display
• Output lines a through g of decoder are connected to a through
g terminals of 7 segment display respectively
• Outputs of decoder are active high/active low
BCD to 7 segment Decoder
 BCD to 7 segment Decoder continued
• For active low outputs
common anode 7
segment display is used
• For active high outputs
common cathode 7
segment display is used
• IC 7447 has active low
outputs
• IC 7448 has active high
outputs
 IC 7447/7448
Both ICs have lamp test
(LT),ripple blanking input
(RBI), ripple blanking
output (RBO) and blanking
input (BI) facilities
 Tristate Buffers
• Tristate buffer is a circuit which
connects or isolates its input from its
output. i. e. it controls flow of signal
from input to output
• Tristate buffers are of two types
– Inverting buffers
– Non inverting buffers
• Tristate buffers are used where several
signals are simultaneously connected
to a common bus
• Here signals A, B, C are connected to
a common bus via tristate buffers
 Tristate Buffers continued

• Here enable input E1 is

connected to +5v, therefore
A gets connected to bus
• Enable inputs E2 & E3 are
connected to ground,
therefore respective buffers
will go into high impedance
state, hence B & C will be
isolated from the bus
Unidirectional Buffer (IC 74LS244)
• IC 74LS244 is octal tristate
unidirectional buffer split into two 4
bit sections
• It consists of 8 unidirectional
buffers
• Pins 1A1-1A4 & 2A1-2A4 are
eight input lines of the buffers
whereas pins 1Y1-1Y4 & 2Y1-2Y4
Inputs Output are eight output lines of the buffers
1G’ &/ 2G’ A Y • 1G’ & 2G’ are active low enable
L L L inputs, if these inputs are at high
L H H level output goes into high
H X Z impedance state
 Bidirectional Buffer (IC 74LS245)

• IC 74LS245 is octal tristate bidirectional buffer

• It allows data transfer in both directions
• It is also known as transceiver (transmitter + receiver)
Bidirectional Buffer (IC 74LS245)
continued

• Enable input G’ is active low, i. e. when it is at low

level, buffer allows data transfer from A to B /from
B to A depending on direction control input DIR
• When G’ is high buffer goes into isolation state

G’ (enable) DIR (direction control) Operation

L L Data transfer from B to A
L H Data transfer from A to B
H X Isolation