SUBJECT OUTLINE

48622 Mechatronics 1
Course area UTS: Engineering
Delivery Autumn 2018; City
Subject
Fields of practice: Mechanical Engineering and Mechatronics Engineering majors
classification
Credit points 6cp
Requisite(s) 48510 Introduction to Electrical and Electronic Engineering
Result type Grade and marks

Recommended studies: Basic knowledge in electrical engineering and programming.

Subject coordinator
Dr. Gavin Paul (Lecturer)
Email: [email protected]
Room: CB11.09.208
Phone: +61 2 9514 2969

Teaching staff
Dr. Gavin Paul (Lecturer)
Email: [email protected]
Room: CB11.09.208

Dr. Ravi Ranasinghe (Tutor)

Email: [email protected]
Room: CB11.09.207

Mr Yujun Lai (Tutor)

Email: [email protected]

Mr Jason Ho (Tutor)
Email: [email protected]

Mr Jordan Henry (Tutor)

Email: [email protected]

After watching the lecture videos, attempting the practice quiz questions, reading the lecture slides and attending
class, if you still wish to discuss questions or need further help with understanding concepts in the subject, please see
the lecturer or tutor after the interactive sessions or tutorials. Alternatively, asking questions on the UTS Online
Discussion board is encouraged. If all avenues are exhausted, then please email details of how you attempted to solve
the problem yourself (or in collaboration with others) to tutors or the appropriate lecturer. Email messages will be
responded to within two working days. In special circumstances appointments outside of allocated times can be
requested via email. For administrative Enquiries: post a message to UTS online, “discussion board” - “Administrative
Issues”.

Subject description
The objectives of this subject are to enable students to: master the fundamentals of digital and programmable
electronic circuits and their engineering applications; master the hardware architecture of a typical small computer
system; and understand the principles of low-level programming and gain an ability to write simple embedded
software. Students are introduced to the basics of real-time application programming. Topics include: digital sequential
circuits; state diagram and its application in the design of digital circuits; basic hardware architectures of the digital
computer in terms of its building blocks; how hardware integrates with software at the machine level; low-level
language programming; internal architecture and design of a typical register-based central processing unit and a main
memory subsystem, and their interdependence; concepts of computer system buses, as well as different types of input
and output devices; interrupts; input and output; micro-controller theory; hardware interfacing design techniques; and

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and output devices; interrupts; input and output; micro-controller theory; hardware interfacing design techniques; and
aspects of real-time programming.

Subject learning objectives (SLOs)

Upon successful completion of this subject students should be able to:
1. Explain and apply the fundamentals of digital and programmable electronic circuits and their engineering
applications.

2. Explain and apply the fundamentals of microcontrollers.

3. Identify the principles of low-level programming and gain an ability to write simple embedded software.

Course intended learning outcomes (CILOs)

This subject also contributes specifically to the development of the following faculty Course Intended Learning
Outcomes (CILOs) and Engineers Australia (EA) Stage 1 competencies:
Establish priorities and goals, which is linked to EA Stage 1 Competencies: 2.3, 3.5 (A.2)
Identify and apply relevant problem solving methodologies, which is linked to EA Stage 1 Competencies: 1.1, 2.1,
2.2, 2.3 (B.1)
Design components, systems and/or processes to meet required specifications, which is linked to EA Stage 1
Competencies: 1.3, 1.6, 2.1, 2.2, 2.3 (B.2)
Implement and test solutions, which is linked to EA Stage 1 Competencies: 2.2, 2.3 (B.5)
Communicate effectively in ways appropriate to the discipline, audience and purpose, which is linked to EA Stage 1
Competency: 3.2 (E.1)

Teaching and learning strategies

The teaching and learning strategies focus on:
Introducing in lecture notes and UTSOnline videos the key fundamental concepts and their interrelations,
Introducing in tutorials appropriate problems to motivate, illustrate and exemplify the concepts presented in lectures,
Introducing in tutorials the main software tools used in the subject.

This subject involves a 1.5-hour interactive lecture session and 2-hour tutorial work each week. The students are
expected to watch the UTSOnline videos, and attempt the practice quiz questions before coming to the classes. The
interactive lecture sessions will discuss the major issues and questions raised from the students regarding digital logic
design and microcontrollers. The face-to-face tutorials aim at further explaining the studied material by solving a
variety of problems. In addition, a hardware kit will be used by students to design simple digital circuits and write
embedded software. A number of laboratory sessions will run to help students with their practical assignments.

Content (topics)
Digital combinational and sequential circuits
State diagram and its application in the design of digital circuits
How hardware integrates with software at the machine level
Low-level language programming
Internal architecture and design of a typical register-based central processing unit
Concepts of computer system buses, as well as different types of input and output devices
Interrupts
Input and output
How mechanical devices are interfaced to electronic circuits

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Program
Week/Session Dates Description

1 12-18 March Interactive lecture: Introduction to the subject, staff and tutors, MXK
demonstration and sales, distribute and discuss assignment 1.

Introduction to digital systems, information, Basic gates and Boolean

algebra.

No face-to-face tutorial classes this week. Work through the self-guided

introductions to Xilinx and purchase an MXK.

Notes:

Before the first class:

Familiarisation with Mechatronics (Mx1) subject structure. Self-paced

review (or learning) using online resources.
Explore UTSOnline (both Mechatronics 1 and MXKOnline), read the
subject outline and watch the introductory videos.
Read the slides, watch the videos and attempt the practice quizzes on
"Digital systems and information" (available on UTSOnline in Week 1
folder).
For details of MXK (kit) sales, refer to MXKOnline subject (on
UTSOnline).

2 19-25 March Interactive lecture: Combinational logic circuits design (part 1).

Tutorial: Xillinx tutorial 1.

Notes:

Prior to the interactive lecture, read the slides, watch the videos and
attempt the practice quizzes on "Combinational logic" (available on
UTSOnline in Week 2 folder).

3 26 March - 1 April Interactive lecture: Combinational logic circuits design (part 2).

Tutorial: No tutorials due to Good Friday Easter Holidays (may hold

make-up sessions in StuVac week depending upon demand).

Notes:

Prior to the interactive lecture, read the slides, watch the videos and
attempt the practice quizzes on "Combinational logic" (available on
UTSOnline in Week 3 folder).

Quiz 1 is next week in the interactive lecture.

4 2-8 April Interactive lecture: Assessment Task 3:In-class Quiz 1 during the
interactive lecture (feedback is provided when marking). Followed by
discussion and questions about Sequential logic circuits design (part 1).

Assessment Task 1: Assignment 1 part A is due in the tutorial class.

Tutorial: Xillinx tutorial 2.

Notes:

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 Quiz 1 in the interactive lecture.

Prior to the interactive lecture:

review all material on Combinational logic circuits for the quiz and
attempt the practice quiz questions on UTSOnline,
read the slides, watch the videos and attempt the practice quizzes on
"Sequential logic" (available on UTSOnline in Week 4 folder).

5 9-15 April Interactive lecture: Sequential logic circuits design (part 2).

Tutorial: Xilinx tutorial 3.

Notes:

Prior to the interactive lecture, read the slides, watch the videos and
attempt the practice quizzes on "Sequential logic" (available on
UTSOnline in Week 5 folder).

6 16-22 April Interactive lecture: Revision of Combinational and Sequential circuits, and
introducting "Registers and Counters" in preparation for PIC material.

Tutorial: Xilinx tutorial 4.

Stuvac 23-29 April Interactive lecture: No interactive session due to Stuvac

Tutorial: make-up sessions may run depending upon demand. Details to

be posted on UTSOnline.

Notes:

Review all material on Combinational and Sequential logic circuits for Quiz
2 (in week 7) and attempt the practice quiz questions on UTSOnline.

7 30 April - 6 May Interactive lecture: Assessment Task 3: in-class Quiz 2 during the
interactive lecture (feedback is provided when marking). Followed by PIC
introduction and assignment help session.

Tutorial: Assessment Task 1: Assignment 1 part B (demonstration) is

due in tutorial class (oral feedback is provided).

Assessment Task 1: Assignment 1 part C (report) is due on Friday at

23:59.

Notes:

Quiz 2 in interactive lecture session.

Prior to the interactive lecture:

review all material on Combinational and Sequential Logic Circuits for

Quiz 2 and attempt the practice quiz questions on UTSOnline,
read the slides, watch the videos and attempt the practice quizzes (on
UTSOnline).

Prior to the next interactive lecture, review the material on "PIC part 1"
(available on UTSOnline).

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 8 7 -13 May Interactive lecture: PIC Part 1.

Tutorial: PIC tutorial 1.

Notes:

Prior to the interactive lecture, review the material on "PIC part 1"
(available on UTSOnline).

9 14-20 May Interactive lecture: ​PIC Part 2.

Tutorial: PIC tutorial 2.

Notes:

Quiz 3 in interactive lecture session. Review first 2 weeks of PIC material.

Study sample quiz questions on UTSOnline.

10 21-27 May Interactive lecture: ​ Assessment Task 3: In-class Quiz 3 during the
interactive lecture (feedback is provided when marking) followed by PIC
Part 3.

Tutorial: PIC tutorial 3.

Notes:

Quiz 3 in interactive lecture session. Review first 2 weeks of PIC material.

Study sample quiz questions on UTSOnline.

11 26 May - 3 June Interactive lecture: PIC Part 4.

Tutorial: PIC tutorial 4 and help session for Assignment 2.

Notes:

Prior to the interactive lecture, review the material on "PIC part 4"
(available on UTSOnline).

12 4-10 June Interactive lecture: Assessment Task 3: In-class Quiz 4 during the
interactive lecture (feedback is provided when marking). Followed by a
final exam review session.

Tutorial: Assessment Task 1: Assignment 2 demonstration in tutorial

class (oral feedback is provided during the demonstration).

Notes:

Quiz 4 in interactive lecture session so prior to the interactive lecture

review all PIC material.

Assessment Task 2: Assignment 2 report is due on Friday at 23:59.

S2 11-15 June Final StuVac.

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 A1-A2 16-30 June Assessment Task 4: Final Exam will be scheduled during this Final
Assessment Period.

Additional subject costs

You are expected to buy a MXK (Modular eXperimenter Kit) (approximately AUD$100) containing parts required for
practical work. Further details will be provided on UTSOnline.

Assessment
Assessment task 1: Assignment 1: Xilinx and FPGA demonstration
Objective(s): This assessment task addresses the following subject learning objectives (SLOs):

1 and 3

This assessment task contributes to the development of the following course intended learning
outcomes (CILOs):

A.2, B.5 and E.1

Type: Demonstration

Groupwork: Individual

Weight: 25%

Task: In this individual task, students are required to design combinational and sequential logic circuits then
schematically program the FPGA using Xilinx-based simulations. The demonstration needs to
achieve a particular set of functional requirements that are detailed and communicated via
UTSOnline. The final demonstration will be given in class to an assessor and requires students to
answer various questions related to their Xilinx design and their strategy for solving the task. Students
will then write a reflections report detailing their thought process, design, successes and challenges
faced. This assessment task is staged so students can complete and demonstrate each part in
incremental steps. Further details about the deadlines are provided in the program and more details
about the requirements and deliverables will be provided via UTSOnline.

Due: Assignment 1 part A is due in the tutorial class Week 3; Assignment 1 part B (demonstration) is due
in tutorial class Week 7; Assignment 1 part C (report) is due on Friday Week 7 at 23:59

Criteria Criteria Weight (%) SLOs CILOs

linkages:
Demonstrate a simulated and working 60 1 A.2, B.5
FPGA design

Demonstrate functionality and correctness 20 1 B.5

of MXK setup

Quality of communications and reflections 20 1, 3 E.1

report

SLOs: subject learning objectives

CILOs: course intended learning outcomes

Further Weighting in Assessment criteria is approximate. Please refer to marking guide for specific weighting
information: allocation

Assessment task 2: Assignment 2: PIC programming task

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 Objective(s): This assessment task addresses the following subject learning objectives (SLOs):

1, 2 and 3

This assessment task contributes to the development of the following course intended learning
outcomes (CILOs):

B.1, B.2, B.5 and E.1

Type: Demonstration

Groupwork: Individual

Weight: 25%

Task: In this individual task, the student is required to configure and program the PIC Microcontroller and
demonstrate that it achieves a particular set of functional requirements that will be detailed and
communicated via UTSOnline. The final demonstration will be given in class to an assessor and will
require students answer various questions related to their software design, electronics circuitry, PIC
configuration and their strategy for solving the task. Students will then write a report reflecting upon
how they engineered their solution. This assessment task is staged so students can complete and
demonstrate each part incrementally. Further information about the deadlines is provided in the
program and more details about the requirements and deliverables will be communicated via
UTSOnline.

Due: Assignment 2 demonstration in tutorial class Week 12 Assignment 2 report is due on Friday Week 12
at 23:59

Criteria Criteria Weight (%) SLOs CILOs

linkages:
Demonstrate the functionality and 70 2, 3 B.1, B.2, B.5
correctness of PIC design

Quality of communications and reflections 30 1, 2, 3 E.1

report

SLOs: subject learning objectives

CILOs: course intended learning outcomes

Further Weighting in Assessment criteria is approximate. Please refer to marking guide for specific weighting
information: allocation . Detailed assignment briefs will be provided on UTSOnline.

Assessment task 3: Review Quizzes

Objective(s): This assessment task addresses the following subject learning objectives (SLOs):

1, 2 and 3

This assessment task contributes to the development of the following course intended learning
outcomes (CILOs):

B.1 and B.2

Type: Quiz/test

Groupwork: Individual

Weight: 20%

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 Task: Students will individually sit four in-class review quizzes in the weeks indicated in the program.
These quizzes will assess the student’s knowledge on the topics of combinational logic circuits,
sequential logic circuits, and PIC microcontrollers, in an incremental manner. The quizzes are online
and will be attempted for the first time in class and will thus provide an immediate feedback
opportunity to students at key times throughout the session.

Due: Quiz 1: Week 4, in interactive lecture class; Quiz 2: Week 7, in interactive lecture class; Quiz 3: Week
10, in interactive lecture class; Quiz 4: Week 12, in interactive lecture class.

Criteria Criteria Weight (%) SLOs CILOs

linkages:
Correctness of answer 60 1, 2, 3 B.1, B.2

Justication of results 40 1, 2, 3 B.2

SLOs: subject learning objectives

CILOs: course intended learning outcomes

Further Weighting in Assessment criteria is approximate. Please refer to marking guide for specific weighting
information: allocation. Detailed assignment briefs will be provided on UTSOnline.

Assessment task 4: Formal exam

Type: Examination

Groupwork: Individual

Weight: 30%

Task: The final exam is a centrally conducted examination that assesses a student's theoretical knowledge
of combinational logic circuits, sequential logic circuits, and PIC microcontrollers. Students will be
required to demonstrate in the exam that they understand the design process and the approach to
implementation. The topics and style of questions will be covered and practised in the interactive-style
classes throughout the session.

Due: UTS Exam period

Further Weighting in Assessment criteria is approximate. Please refer to marking guide for specific weighting
information: allocation.

Examination material or equipment

The final exam will be a restricted open book examination. Programmable and non-programmable calculators may be
used.

Recommended texts
Mano and Kime, Logic and Computer Design Fundamentals, 4th Ed., Prentice Hall, 2004, ISBN 0-13-1911651.
Library’s Call Number: 621.395 MANO (ED.4).
Publisher's website:
https://www.pearsonhighered.com/product/Mano-Logic-and-Computer-Design-Fundamentals-4th-Edition/9780131989269.htm

Wilmshurst, T., Designing Embedded Systems with PIC Microcontrollers, 2nd Ed., Elsevier, 2009, eBook ISBN:
9780080961842, Paperback ISBN: 9781856177504.
Library's Call Number: 629.89 WILM (ED.2)

References
Floyd, T.L., Digital Fundamentals, 8th Ed., Prentice Hall, 2003, ISBN 0-13-046411-2.
Library’s Call Number: 621.3815 FLOY (ED.8).

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Katzen, S., The Quintessential PIC® Microcontroller, Springer 2005, ISBN: 1-85233-942-X. (http://www.springer.com)

Predko, M., PICmicro® Microcontroller Pocket Reference, McGraw-Hill, 2001, ISBN 0-07-136175-8.
Library’s Call Number: 629.895 PREK.
Book website: http://www.myke.com/pic-pckt.htm

Play-Hookey Website

http://www.play-hookey.com/digital/

Graduate attribute development

For a full list of the faculty's graduate attributes and EA Stage 1 competencies, refer to the FEIT Graduate Attributes
webpage.

Assessment: faculty procedures and advice

Extensions

When, due to extenuating circumstances, you are unable to submit or present an assessment task on time, please
contact your subject coordinator before the assessment task is due to discuss an extension. Extensions may be
granted up to a maximum of 5 days (120 hours). In all cases you should have extensions confirmed in writing.

Special Consideration

If you believe your performance in an assessment item or exam has been adversely affected by circumstances
beyond your control, such as a serious illness, loss or bereavement, hardship, trauma, or exceptional employment
demands, you may be eligible to apply for Special Consideration.

Late Penalty

Work submitted late without an approved extension is subject to a late penalty of 10 per cent of the total available
marks deducted per calendar day that the assessment is overdue (e.g. if an assignment is out of 40 marks, and is
submitted (up to) 24 hours after the deadline without an extension, the student will have four marks deducted from
their awarded mark). Work submitted after five calendar days is not accepted and a mark of zero is awarded.

For some assessment tasks a late penalty may not be appropriate – these are clearly indicated in the subject outline.
Such assessments receive a mark of zero if not completed by/on the specified date. Examples include:
a. weekly online tests or laboratory work worth a small proportion of the subject mark, or
b. online quizzes where answers are released to students on completion, or
c. professional assessment tasks, where the intention is to create an authentic assessment that has an absolute
submission date, or
d. take-home papers that are assessed during a defined time period, or
e. pass/fail assessment tasks.

Querying marks/grades and Final Results

If a student disagrees with a mark or a final result awarded by a marker:

where a student wishes to query a mark, the deadline for a query during teaching weeks is 10 working days from
the date of the return of the task to the student
where a student wishes to query a final examination result, the deadline is 10 working days from the official release
of the final subject result.

Further information can be found at Academic advice.

Academic liaison officer

Academic liaison officers (ALOs) are academic staff in each faculty who assist students experiencing difficulties in
their studies due to: disability and/or an ongoing health condition; carer responsibilities (e.g. being a primary carer for
small children or a family member with a disability); and pregnancy.

ALOs are responsible for approving adjustments to assessment arrangements for students in these categories.
Students who require adjustments due to disability and/or an ongoing health condition are requested to discuss their
situation with an accessibility consultant at the Accessibility Service before speaking to the relevant ALO.

The ALO for undergraduate students is:

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Chris Wong
telephone +61 2 9514 4501

The ALO for postgraduate students is:

Dr Nahm Tran
telephone +61 2 9514 4468

Statement about assessment procedures and advice

This subject outline must be read in conjunction with the policy and procedures for the assessment for coursework
subjects.

Statement on copyright
Teaching materials and resources provided to you at UTS are protected by copyright. You are not permitted to re-use
these for commercial purposes (including in kind benefit or gain) without permission of the copyright owner. Improper
or illegal use of teaching materials may lead to prosecution for copyright infringement.

Statement on plagiarism
Plagiarism and academic integrity

At UTS, plagiarism is defined in Rule 16.2.1(4) as: 'taking and using someone else's ideas or manner of expressing
them and passing them off as ... [their] own by failing to give appropriate acknowledgement of the source to seek to
gain an advantage by unfair means'.

The definition infers that if a source is appropriately referenced, the student's work will meet the required academic
standard. Plagiarism is a literary or an intellectual theft and is unacceptable both academically and professionally. It
can take a number of forms including but not limited to:
copying any section of text, no matter how brief, from a book, journal, article or other written source without duly
acknowledging the source
copying any map, diagram, table or figure without duly acknowledging the source
paraphrasing or otherwise using the ideas of another author without duly acknowledging the source
re-using sections of verbatim text without using quote marks to indicate the text was copied from the source (even if
a reference is given).

Other breaches of academic integrity that constitute cheating include but are not limited to:
submitting work that is not a student's own, copying from another student, recycling another student's work,
recycling previously submitted work, and working with another student in the same cohort in a manner that exceeds
the boundaries of legitimate cooperation
purchasing an assignment from a website and submitting it as original work
requesting or paying someone else to write original work, such as an assignment, essay or computer program, and
submitting it as original work.

Students who condone plagiarism and other breaches of academic integrity by allowing their work to be copied are
also subject to student misconduct Rules.

Where proven, plagiarism and other breaches of misconduct are penalised in accordance with UTS Student Rules
Section 16 – Student misconduct and appeals.

Avoiding plagiarism is one of the main reasons why the Faculty of Engineering and IT is insistent on the thorough and
appropriate referencing of all written work. Students may seek assistance regarding appropriate referencing through
UTS: HELPS.

Work submitted electronically may be subject to similarity detection software. Student work must be submitted in a
format able to be assessed by the software (e.g. doc, pdf (text files), rtf, html).

Further information about avoiding plagiarism at UTS is available.

Retention of student work

The University reserves the right to retain the original or one copy of any work executed and/or submitted by a student
as part of the course including, but not limited to, drawings, models, designs, plans and specifications, essays,
programs, reports and theses, for any of the purposes designated in Student Rule 3.9.2. Such retention is not to affect
any copyright or other intellectual property right that may exist in the student's work. Copies of student work may be

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retained for a period of up to five years for course accreditation purposes. Students are advised to contact their subject
coordinator if they do not consent to the University retaining a copy of their work.

Statement on UTS email account

Email from the University to a student will only be sent to the student's UTS email address. Email sent from a student
to the University must be sent from the student's UTS email address. University staff will not respond to email from
any other email accounts for currently enrolled students.

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