DESIGN AND IMPLEMENTATION OF CMOS LOW POWER

HIGH PERFORMANCE 10T SRAM 4*4 ARRAY

A Project Report Submitted in partial fulfillment of
the requirements for the award of degree of
Bachelor of Technology
in
ELECTRONICS AND COMMUNICATION ENGINEERING
by
M.J.N.V.D. Sambhavi (20K61A0485)
M.Likhitha (20K61A0489)
Ch. Sireesha (20K61A04D2)
S.M.V.V. Satyanarayana (20K61A04D1)
Under the esteemed guidance of
P. Sivadurgarao

Assistant Professor

Department of Electronics & Communication Engineering

SASI INSTITUTE OF TECHNOLOGY&ENGINEERING
Kadakatla, TADEPALLIGUDEM– 534 101
Academic Year 2023-24
 SASI INSTITUTE OF TECHNOLOGY&ENGINEERING
Department of Electronics & Communication Engineering
Kadakatla, TADEPALLIGUDEM– 534 101
Academic Year 2023-24

Certificate

Date:

This is to certify that the project work entitled “Design and implementation of CMOS low
power high performance 10T SRAM 4*4 array” is being submit M.J.N.V.D. Sambhavi
(20K61A0485),M.Likhitha(20K61A0489),Ch.Sireesha(20K61A04D2),S.M.V.V.Satyanar
ayana (20K61A04D1) in partial fulfillment for the award of Degree of Bachelor of
Technology in Electronics & Communication Engineering to the Jawaharlal Nehru
Technological University, Kakinada during the academic year 2023-24 is a record of
bonafide work carried out by them under our guidance and supervision .

Project Guide Head of the Department

P. Sivadurgarao Dr. G. Naveen Kishore,
Assistant Professor Professor & HoD

External Examiner
 DECLARATION
We,M.J.N.V.D.Sambhavi(20K61A0485),M.Likhitha(20K61A0489),Ch.Sireesha(20K
61A04D2),S.M.V.V.Satyanarayana (20K61A04D1)), hereby declare that this thesis titled
“Design and implementation of CMOS low power high performance 10T SRAM 4*4
array” under the guidance and supervision of P. Sivadurgarao, Assistant Professor, ECE
Department, Sasi Institute of Technology & Engineering, Tadepalligudem., is a bonafied
research work submitted in partial fulfilment of the requirements for the award of the
degree of Bachelor of Technology. The work carried out by them and results embodied in
this thesis have not been reproduced or copied from any source.

We also declare that it has not been submitted previously in part or in full to this
university or any other university / Institution for the award of any degree or diploma.

Place: Tadepalligudem
Date:

With gratitude,

1) M.J.N.V.D. Sambhavi (20K61A0485)

2) M.Likhitha (20K61A0489)
3) Ch. Sireesha (20K61A04D2)
4) S.M.V.V. Satyanarayana (20K61A04D1)
 ACKNOWLEDGMENT

We take immense pleasure to express our deep sense of gratitude to our beloved Guide
P. Sivadurgarao, Assistant Professor, ECE Department, Sasi Institute of Technology &
Engineering, Tadepalligudem-534101, for his valuable suggestions and rare insights,
constant encouragement and inspiration throughout the project work.

We express our deep sense of gratitude to our beloved Principal, Dr. Mohamad
Ismail, Sasi Institute of Technology& Engineering, Tadepalligudem-534101, for his
valuable guidance and for permitting us to carry out this project.

We would like to take this opportunity to thank Dr. K.Bhanu Prasad, Director, Sasi
Institute of Technology& Engineering, Tadepalligudem-534101, for providing a great
support in successful completion of our project.

We express our deep sense of gratitude to Dr. G. Naveen Kishore, HOD, ECE
Department, Sasi Institute of Technology& Engineering, Tadepalligudem-534101, for the
valuable guidance and suggestions, keen interest shown thorough encouragement extended
throughout the period of project work.

We are grateful to my project coordinator and thanks to all teaching and non
teaching staff members those who contributed for the successful completion of our project
work.

With gratitude,

1) M.J.N.V.D. Sambhavi (20K61A0485)

2) M.Likhitha (20K61A0489)
3) Ch. Sireesha (20K61A04D2)
4) S.M.V.V. Satyanarayana (20K61A04D1)
A PROJECT REPORT ON DESIGN AND IMPLEMENTATION OF CMOS LOW POWER HIGH
PERFORMANCE 10T SRAM 4*4 ARRAY

LIST OF CONTENT

TABLE OF CONTENTS
VISION & MISSION
PEOs & POs
ABSTRACT
LIST OF FIGURES
LIST OF TABLE

CHAPTER -1: INTRODUCTION 1

1.1 Introduction 2
1.2 Aim of the project 2
1.3 Methodology 2
1.4 Significance of the work 2
1.5 Organization of the project 3
1.6 Conclusion 3
CHAPTER -2: LITERATURE SURVEY
2.1 Soft Error Hardened Memory Design for Nano-scale 4
2.2 Design of Area-Efficient and Highly Reliable RHBD 10T Memory 5
Cell for Aerospace Applications

2.3 Radiation-Hardened 14T SRAM Bit cell With Speed and Power 6
Optimized for Space Application
2.4 Soft error rate mitigation techniques for modern micro circus 8
2.5 Efficient Majority Logic Fault Detection With Difference-Set 9
Codes for Memory Applications

2.6 Improving Error Correction Codes for Multiple-Cell Upsets in Space 10

Applications
2.7 Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit Cell 11
Designs for Highly Reliable Terrestrial Applications

2.8 Novel Low-Power and Highly Reliable Radiation Hardened Memory 12

Cell for 65 nm CMOS Technology

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2.9 Design for Soft Error Mitigation 14

2.10 A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read 15
Capability

CHAPTER- 3: INTRODUCTION TO EDA TOOL 16

3.1 TECHNOLOGIES USED (EDM) 16
3.2 START NEW DESIGN & SETUP LIBRARIES 16
3.3 SETUP THE SPICE MODELS FOR THE GENERIC_025 KIT 18
3.4 ENTER THE SCHEMATIC TO SIMULATE THE IV BEHAVIOR 19
OF AN NMOS TRANSISTOR

3.5 SETUP THE PARAMETERS THAT WILL BE USED DURING THE 22

DC SWEEP ANALYSIS
3.6 TRANSIENT ANALYSIS OF A CMOS INVERTER & SYMBOL 25
CREATION
CHAPTER- 4: METHODOLOGY WISE ANALYSIS 32
4.1 Soft Error Hardened Memory Design for Nano-scale 32
4.2 Design of Area-Efficient and Highly Reliable RHBD 10T Memory 33
Cell for Aerospace Applications

4.3 Radiation-Hardened 14T SRAM Bit cell With Speed and Power 34
Optimized for Space Application

4.4 Soft error rate mitigation techniques for modern micro circus 36

4.5 Efficient Majority Logic Fault Detection With Difference-Set 36

Codes for Memory Applications

4.6 Improving Error Correction Codes for Multiple-Cell Upsets in Space 37

Applications
4.7 Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit Cell 38
Designs for Highly Reliable Terrestrial Applications

4.8 Novel Low-Power and Highly Reliable Radiation Hardened Memory 40

Cell for 65 nm CMOS Technology

4.9 Design for Soft Error Mitigation 40

4.10 A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read 41
Capability

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CHAPTER- 5: IMPLEMENTATION & RESULTS 42

5.1 Existing method 42
5.2 6T SRAM SCHEMATIC 49
5.3 OPERATION OF 6T SRAM 49
CHAPTER- 6: SIMULATION OF PROPOSED METHOD

6.1 Proposed method 51

6.2 APPLICATION OF 10T SRAM IN DESIGNING 53
OF 4X4 ARRAY

6.3 OPERATION OF 2X4 DECODER 54

6.3.1 4 Input OR gate 55
6.4 4X4 10T SRAM ARRAY 55
6.5 Operation of 4X4 ARRAY 56
CHAPTER- 7: CONCLUSION AND FUTURE SCOPE
7.1 CONCLUSION 58

7.2 FUTURE SCOPE 58

REFERENCES 59

APPENDIX 62

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VISION & MISSION

INSTITUTE VISION:
Confect as a premier institute for professional education by creating technocrats
who can address the society’s needs through inventions and innovations.

INSTITUTE MISSION:

 Partake in the national growth of technological, industrial area with societal

responsibilities.

 Provide an environment that promotes productive research.

 Meet stakeholder’s expectations through continued and sustained quality

improvements.

DEPARTMENT VISION:
To help in making the institute in providing competitive engineering education
to the learner and bring out quality professionals in the field of Electronics and
Communication Engineering, who can meet the industrial needs by taking up
existing, new engineering and social challenges.

DEPARTMENT MISSION:
 To provide quality and effective training in the domain of Electronics and
communication Engineering through curriculum, effective teaching, and
learning process.
 Provide state of art laboratories.

 Conduct industrial collaborative programs.

 Involve the stakeholders in Co-curricular & extracurricular activities.

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PROGRAM EDUCATIONAL OBJECTIVES

PEO1. Develop strong foundation in Electronics and Communication Engineering to
achieve the needs of industry with continuous skill improvement.
PEO2.Contribute to society in solving technical problems using electronic and
communication principles, tools, practices and Team work.
PEO3. Personally encourage to uphold to professional, ethical, social, environmental
responsibilities of their profession.

PROGRAM OUTCOMES & PROGRAM SPECIFIC

OUTCOMES
PROGRAM OUTCOMES:
PO1: Engineering knowledge
Apply the knowledge of mathematics, science, engineering fundamentals and an
engineering specialization to the solution of complex engineering problems.
PO2: Problem analysis
Identify, formulate, research literature and analyze complex engineering problems
reaching substantiated conclusions using first principles of mathematics, natural sciences
and engineering sciences.
PO3: Design/development of solutions
Design solutions for complex engineering problems and design system components or
processes that meet specified needs with appropriate consideration for public health and
safety, cultural, societal and environmental considerations.
PO4: Conduct investigations of complex problems
Use research based knowledge and research methods including design of experiments,
analysis and interpretation of data and synthesis of information to provide valid conclusions.
PO5: Modern tool usage
Create, select and apply appropriate techniques, resources and modern engineering
and IT tools including prediction and modelling to complex engineering activities with an
understanding of the limitations.
PO6: The engineer and society
Apply reasoning informed by contextual knowledge to assess societal, health, safety,
legal and cultural issues and the consequent responsibilities relevant to professional
engineering practice.

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PO7: Environment and sustainability

Understand the impact of professional engineering solutions in societal and
environmental contexts and demonstrate knowledge of and need for sustainable
development.
PO8: Ethics
Apply ethical principles and commit to professional ethics and responsibilities and
norms of engineering practice.
PO9: Individual and team work
Function effectively as an individual, and as a member or leader in diverse teams and
in multidisciplinary settings
PO10: Communication
Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as being able to comprehend and write effective
reports and design documentation, make effective presentations and give and receive clear
instructions
PO11: Project management and finance
Demonstrate knowledge and understanding of engineering and management
principles and apply these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments
PO12: Life-long learning
Recognize the need for and have the preparation and ability to engage in independent
and life- long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES

PSO1: Practice in Embedded Systems
An ability to recognize and adapt to emerging trends in embedded systems and its
applications
PSO2: Signal & Image Analysis
An ability to perform Signal & Image processing in the field of communication
PSO3 Digital System design

An ability to design a system or process to meet desired needs in VLSI.

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ABSTRACT

The critical charge of sensitive nodes is reducing, making SRAM cells, used for
aerospace applications, more vulnerable to soft-error. If a radiation particle strikes a
sensitive node of the standard 6T SRAM cell, the stored data in the cell is flipped,
causing a single-event upset (SEU). Therefore, in this Project, a Soft-Error-Aware Read-
Stability- Enhanced Low Power 10T (SARP10T) SRAM cell is proposed to mitigate
SEUs. Enable is more promising since this cell delivers robust operation while incurring
moderate area overhead. However, our study shows that Enable experiences large
number of write failures under parametric variations of scaled technologies, impeding
the application of this SRAM cell To analyze the relative performance of SARP10T, it is
compared with other recently published soft-error-aware SRAM cells, QUCCE12T,
ENABLE12T, RHD12T, RHPD12T and RSP14T. All the sensitive nodes of SARP 10T
can regain their data even if the node values are flipped due to a radiation strike.
Furthermore, SARP10T can recover from the effect of single event multi-node upsets
(SEMNUs) induced at its storage node pair. Along with these advantages, the proposed
cell exhibits the highest read stability, as the ‘0’-storing storage node, which is directly
accessed by the bitline during read operation, can recover from any upset. Furthermore,
SARP10T consumes the least hold power. SARP10T also exhibits higher write ability
and shorter write delay than most of the comparison cells. All these improvements in the
proposed cell are obtained by exhibiting only a slightly longer read delay and consuming
slightly higher read and write energy.

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LIST OF FIGURES
S.NO Title Page No.
Figure 3.1 Start of new design and setup libraries 17

Figure 3.2 Setup of SPICE models 18

Figure 3.3 Selecting DC sweep analysis 19

Figure 3.4 Setup properties of transistor 20

Figure 3.5 Schematic diagram of the transistor 20

Figure 3.6 Connect power supply and set the properties 21

Figure 3.7 Connect the ground 22

Figure 3.8 DC analysis 23

Figure 3.9 Adding parameters folder 23

Figure 3.10 Graph of VDS VS Current 24

Figure 3.11 Spice engine to check errors 25

Figure 3.12 Export SPICE net list 28

Figure 3.13 Symbol of inverter 29

Figure 3.14 Symbolic view of inverter 30

Figure 3.15 Output waveforms of inverter 30

Figure. 4.1 Previous radiation hardened memory cells. (a) Cell 32

NS [11], (b) 13T

Figure. 4.2 Schematic of the proposed RHBD 10T memory cell 33

Figure. 4.3 (a) RHD-12T bitcell. 35

Figure. 4.4 Schematic of an ML decoder. I) cyclic shift register. 37

II) XOR matrix. III) Majority gate. IV) XOR for
correction

Figure. 4.5 Block diagram of the fault injector simulator 38

Figure. 4.6 Quadruple cross-coupled storage cell QUCCE 10T 39

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Figure. 4.7 SEU in an inverter and upset polarity waves: (a) 40

SEU physics mechanism; (b) when PMOS is
struck, a positive transient pulse is induced; (c)
when NMOS is struck a negative transient pulse is
generated.

Figure. 4.8 Elimination of extra delay in the path of write data. 41

Figure. 4.9 a) 12T DICE cell for differential read/write and b) 42

standard 6T cell with cross- coupled node capacitor

Figure.5.1 12T SRAM with multi-node soft error 43

Figure 5.2 12 simulation results of SRAM with multi-node 44

soft error

Figure. 5.3 Write “0” and read operations 45

Figure 5.4 Write “0” operation 46

Figure 5.5 Write ‘0’ Operation 47

Figure 5.6 Read Operation 48

Figure 5.7 6T SRAM Schematic 49

Figure 5.8 6T SRAM Simulation Results 49

Figure 6.1 writes enable: Radiation-hardened SRAM Cell 51

Figure6.2 simulation of 10T SRAM Cell 52

Figure6.3 Schematic of 2x4 Decoder 53

Figure 6.4 2x4 decoder results 54

Figure 6.5 Schematic of inverter 54

Figure 6.6 Schematic of 4 input OR gate 55

Figure 6.7 SCHMETAIC OF 4X4 ARRAY 55

Figure 6.8 Simulation results of 4x4 array 10TSRAM 56

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LIST OF TABLES

S.no Title Page No.

Table 1 Comparison between 12T with 53
10T

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CHAPTER-1

INTRODUCTION

1.1 INTRODUCTION

Quality of life and sense of safety have both been boosted thanks to advancements in
areas such as military surveillance, satellite communications, directing systems, tracking
systems, and other aerospace services. Aviation uses microprocessors for control, guiding,
engine management, inertial navigation, and more. Multi-core CPUs improve performance.
Cores enhance cache memory. Thus, CPU power, area, and latency optimization requires
SRAM cache memory. Highly energetic particles in space affect memory circuit performance.
An energetic particle and an integrated circuit substrate, such as semiconductor memory,
generate electron-hole pairs. The minority carriers of the strike interpret as a forward field the
reverse bias that exists between the substrate and the n-well and the electric field that exists in
the diffusion zone. As a result of the accumulation of minority carriers in drain diffusion zones,
a voltage spike is produced. This voltage spike can be either positive or negative, depending
on the minority carrier. If the spike exceeds the logic circuit's switching threshold and lasts
long enough, the stored content flips, causing a single-event upset (SEU). A single ion
assault can affect many integrated circuit nodes. Single-event multi-node upsets (SEMNUs) are
becoming increasingly prevalent as a result of the fast decrease in device spacing brought
about by technological advancements. Memory systems that use triple modular redundancy
(TMR) have fewer single event upsets (SEUs). According to the, three duplicated memory
cells vote on the right value. Error correction codes, often known as ECCs, have the potential
to lower SEUs. Error correction codes, often known as ECCs, are only useful in electronic
circuits when they are accompanied by redundant components and encoding/decoding
devices. ECCs call for an increase in the amount of time, space, and power. SRAMs that are
aware of soft errors perform better than ECCs because they have a lower power consumption
and a shorter latency. It is recommended in reference to make certain that the SRAM cell is
able to recover from multi-node disturbances.

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1.2 Aim of the project

The aim of the project is to design and implantation of CMOS low power high performance
10T SRAM 4*4 array. To analyze the relative performance of SARP10T, it is compared
with other recently published soft-error-aware SRAM cells, QUCCE12T, ENABLE12T,
RHD12T, RHPD12T and RSP14T. All the sensitive nodes of SARP 10T can regain their
data even if the node values are flipped due to a radiation strike. Furthermore, SARP10T
can recover from the effect of single event multi-node upsets (SEMNUs) induced at its
storage node pair. Along with these advantages, the proposed cell exhibits the highest read
stability, as the ‘0’-storing storage node, which is directly accessed by the bitline during
read operation, can recover from any upset. Furthermore, SARP10T consumes the least
hold power. SARP10T also exhibits higher write ability and shorter write delay than most
of the comparison cells. All these improvements in the proposed cell are obtained by
exhibiting only a slightly longer read delay and consuming slightly higher read and write
energy.

1.3 Methodology
A radiation-hardened SRAM cell, may solve the problem, according to this study. In
this statement, "we" stands for "writ-ability enhanced." Enable uses 12 access transistors to
improve the SRAM cell's writ ability. Our write enable design uses SRAM cell
architecture to match the Enable design's cell area. Monte-Carlo (MC) simulations
determine the SRAM cell design's practicality. Despite parametric process changes, write
enable performs well for 16 nm FD-SOI technology writ ability. Thus, we compare write
enable to Enable. This project uses scaled technology to create radiation-resistant SRAM
chips.

1.4 Significance of the work:

The proposed work will be very helpful for improving the classical method this
proposed method will provides lower power consumption, with less kickback noise with
higher speed. the proposed cell exhibits the highest read stability, as the ‘0’-storing storage
node, which is directly accessed by the bit line during read operation, can recover from any
upset. Furthermore, SARP10T consumes the least hold power. SARP10T also exhibits
higher write ability and shorter write delay than most of the comparison cells. All these
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improvements in the proposed cell are obtained by exhibiting only a slightly longer read

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1.5 Organization of the project:

The Organization of the thesis follows the sequence of achieved objectives. In
addition to this chapter, there are six other chapters: [Literature Review, System design,
Software implementation, Software code using EDA Tools, Simulation Results, Future
scope and conclusion].

1.6 Conclusion:
The project is to design and implantation of CMOS low power high performance 10T
SRAM 4*4 array. To analyze the relative performance of SARP10T, it is compared with
other recently published soft-error-aware SRAM cells, QUCCE12T, ENABLE12T,
RHD12T, RHPD12T and RSP14T. All the sensitive nodes of SARP 10T can regain their
data even if the node values are flipped due to a radiation strike. Furthermore, SARP10T
can recover from the effect of single event multi-node upsets (SEMNUs) induced at its
storage node pair. Along with these advantages, the proposed cell exhibits the highest read
stability, as the ‘0’-storing storage node, which is directly accessed by the bitline during
read operation, can recover from any upset. Furthermore, SARP10T consumes the least
hold power. SARP10T also exhibits higher write ability and shorter write delay than most
of the comparison cells. All these improvements in the proposed cell are obtained by
exhibiting only a slightly longer read delay and consuming slightly higher read and write
energy

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CHAPTER-2
LITERATURE SURVEY
2.1 Soft Error Hardened Memory Design for Nano-scale
ComplementaryMetal Oxide Semiconductor
Technology
The majority of the decrease in the dependability of nanoscale memories is due to
radiation- induced soft errors. Through this research, a 65-nanometer CMOS memory cell that
is error- tolerant has been developed. The physics mechanism of the SEU serves as the
foundation for the suggested layout-topology. The read and write access speeds, the amount
of power consumed, and the amount of layout space are all factors that are compared for
hardened memory cell designs. As a result of its flawless fault tolerance, the cell in question is
particularly well-suited for use in memory applications in environments with high levels of
radiation. The results of our simulations indicate that the suggested cell is capable of
withstanding multiple- node upsets in spite of changes in process, voltage, and temperature
(PVT). It is believed that single event upsets (SEUs), which can be caused by both the
packing materials and cosmic rays, limit the availability and reliability of nano-
scalememory systems [1–3]. The reduction in supply voltage and node capacitance brought
about by Single Event Upsets, often known as SEUs, can alter the content of memory cells,
which can lead to malfunctions in electrical devices [4]. SEUs, also known as soft errors
[4, 5], are able to be rectified during the write or reset operations of a device. In applications
that rely heavily on memory, such as cardioverter defibrillators, even minor mistakes can have
significant repercussions [8]. Consequently, environments exposed to radiation necessitate the
implementation of highly efficient memory protection technologies to minimize the effects of
(SEUs). The mitigation of memory system damage caused by single-event upsets, commonly
referred to as TMR [9]. The TMR algorithm effectively determines the accurate value by
employing three replicas of each memory cell and implementing a voting mechanism that
operates on the principle of majority rule. Evenif one copy is altered, the other two copies
will have a greater influence on voting; hence, the output will not shift even if all three
copies are modified. According to previous studies[9], [10], the TMR technique has
significant limits in terms of both the amount of space it requires and the amount of power it
consumes, which renders it inappropriate for the

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majority of design scenarios.. Radiation-resistant memory cells are used for circuit-level
hardening instead. In a prior work [11], an NMOS stacked (NS) memory cell was proposed
as a way to recover from single event upsets (SEUs) between 0 and 1. This fortified cell
can only handle single-event upsets (SEUs). Modern memory architectures must also handle
multiple-node upset caused by charge sharing due to CMOS scalability [12, 13]. The 13T
design in [14] was based on a memory cell from [15]. This design addressed multiple-node
upsets. This design amplifies the sharing critical charge via Schmitt trigger hysteresis. This
cell consumes more power and has a larger patterning surface. The dual interlocked storage
cell (DICE) design [16] uses dual node feedback control to eliminate single node upsets. It
cannot sustain a multiple-node upset. Thus, preventing multiple-node upsets requires a new
strengthened memory cell. This work introduces a 12-transistor memory cell designed to
resist radiation-induced SEUs. The suggested architecture protects sensitive nodes from
SEUs using SEU physics methods and layout-topology. This memory cell design also
withstands multiple-node upsets on two fixed nodes.

2.2 Design of Area-Efficient and Highly Reliable RHBD 10T

MemoryCell for Aerospace Applications
This suggests using a reliable 10T memory cell to improve electronic systems in
radiation- intensive aerospace environments. This approach effectively maintains
compactness, minimizes power usage, and ensures exceptional stability. This phenomenon
can be attributed to a disruption in the physical process, coupled with an inaccurate scaling of
the transistor dimension. Cadence Spectre and evaluated using the Taiwan Semiconductor
Manufacturing Company. Despite increased read/write access times, these simulations
show that the 10T cell can survive 0→1 and 1→0 single node shocks. SRAMs affect
airplane electronic system latency, area, power, and essential reliability [1]. Static Random
Access Memories (SRAMs) in aerospace applications are limited by energetic particle
dependability. SEUs, transitory changes in an electronic system's recorded state, are a key
dependability failure mechanism [2]. Drift mechanisms efficiently gather and store induced
charge along a particle's flight, protecting an integrated circuit's sensitive nodes. Once the
accumulated charge's transient voltage pulse exceeds the circuit's switching threshold, this
node's high-sensitivity value will change [4]. The 6T SRAM cell is constructed using two

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inverters that are cross-coupled.

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process, Methods that use overwriting can restore every bit of data that was lost due to a
"soft error" [3, 4]. The issues associated with SRAM cell reliability are increased as CMOS
processes are scaled up. Densities, critical charge, and supply voltage are the main causes
[1]. Due to these factors and the complex cosmic radiation environment, radiation-hardened-
by-design (RHBD) approaches in aerospace applications are increasing [5], [6]. Circuit-level
redundancy or memory cell rebuilding have been studied to improve radiation-induced fault
tolerance in RHBD cells. Design flaws restrict memory cell SEU robustness. cells can only
cure 0 -1 SEU abnormalities. PS- 10T cells can withstand 10 SEUs but not one.
Jahinuzzaman et al. [8] recommended negative feedback with a RHBD Enable-10T memory
cell to prevent single event upset (SEU). RHBD 11T memory cell values are protected by
feedback route obstruction [9]. Operation-generated transient pulses do not affect subsequent
nodes. a 12- transistor DICE memory cell [10]. Two latch pairs store complimentary values
in this memory cell. Positive feedback restores modified values. Shallow trench isolation and
cell structure modification provide This innovation demands a large overhead area. 11T,
DICE, and 12T cells are space-intensive. Thus, aircraft cannot employ RHBD cells. Design-
for- reliabilitysolutions are needed for dependable, space-efficient RHBD memory cells. This
study proposes an area-efficient, power-efficient, and. Circuit-level hardening fixes the
suggested design. A correct transistor size and SEU physical theory can harden radiation,
but write and read access times are slower. This brief's structure. Section II examines the
temporal properties, fault-resilient recovery mechanisms, and design.

2.3 Radiation-Hardened 14T SRAM Bitcell With Speed and

Power Optimized for Space Application
This work introduces the RSP-14T, a space-specific radiation-hardened 14-
transistor SRAM bit-cell. The RSP-14T is a radiation-hardened memory technology
breakthrough due to its enhanced speed and power efficiency. Charge sharing among 65 -nm
CMOS OFF- transistors provides robustness. HSPICE simulations show that the RSP-14T
memory cell writes 50% faster and uses 65% less power than the radiation hardened design
(RHD) - 12T. SEUs are nondestructive, soft-error single-event effects (SEEs) [1]. Ionization
occurs when a high-energy ion hits a semiconductor material in radiation. Device sensitive
nodes will collect these additional costs. Thus, such nodes will experience voltage
disturbances.

Figure 1 shows that when the voltage perturbation amplitude exceeds the inverter's logic

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threshold, SRAM bitcell data switches. This causes a SEU. CMOS scaling reduces inter-

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transistor distance. Thus, numerous transistors can now be charged by a single particle
attack [2]. Charge sharing causes, which have increased due to high-energy particle impacts in
nanoscale CMOS technology [3], [4]. Supply voltage reduction increases circuit radiation
vulnerability. Radiation-hardened digital circuitry technology is crucial [5]. (SRAM)
exhibits a higher vulnerability to soft errors compared to dynamic random-access memory.
Thus, nanoscale technology increases SRAM soft mistakes [6]. SEUs can be reduced by using
alternate 6T SRAM cell designs [7–15]. The main way to reinforce circuit safety is to
create a cell-level transistor connectivity design. [7] I have successfully developed the Enable-
10T SRAM cell with enhanced soft error resilience. The system offers a differential read
operation and incorporates a sizable noise buffer. The system is capable of restoring data
exclusively from "1" to "0" following Single Event Upsets (SEUs). The radiation hardness
and immunity of SEMNU require enhancement. The memory cell based on Schmitt trigger
(STB)-13T, as described in reference [4], successfully achieves complete immunity against
single-event upsets (SEUs). In contrast to DICE, SEMNU's immune promotion is more
restricted, resulting in decreased writing speed, reduced power consumption, and a smaller
layout space. The previous work [9] has proposed the Radiation Hardened Design (RHD)-11T
and RHD-13T memory cells, which have been found to exhibit higher reliability compared
to the STB13T cell. Regrettably, there has been a decline in their writing speed and margin.
According to the reference [10],it is recommended to utilize RH memory (RHM)-12T in
radiation-hardened systems due to its advantageous features of low power consumption and
high reliability. However, the utilization of nMOS as pull-up devices resulted in a reduction of
read noise margins. The RHD-12T memory cell, which is resistant to radiation, was recently
introduced as depicted in Figure 2(a) [12]. The system is capable of providing immunity to
Single Event Upsets (SEUs) on its internal nodes for SEMNUs. Regrettably, the device's
reduced writing speed and elevated power consumption impose limitations on its practical
application. It has been suggested that alternative design solutions have the potential to
enhance radiation tolerance without the need for circuit reinforcement [13, 14].

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2.4 SOFT ERROR RATE MITIGATION TECHNIQUES

FOR MODERN MICROCIRCUS
This work introduces the RSP-14T, a space-specific radiation-hardened 14-
transistor SRAM bit-cell. The RSP-14T is a radiation-hardened memory technology
breakthrough due to its enhanced speed and power efficiency. The robustness of charge
sharing is achieved through the utilization of 65-nm CMOS OFF-transistors. According to
HSPICEsimulations, the RSP-14T memory cell demonstrates a 50% improvement in
write speed and a 65% reduction in power consumption compared. SEUs are
nondestructive, soft-error single-event effects (SEEs) [1]. Ionization occurs when a high-
energy ion hits a semiconductor material in radiation. Device sensitive nodes will
collect these additional costs. Thus, such nodes will experience voltage disturbances.
Figure 1 shows that when the voltage perturbation amplitude exceeds the inverter's logic
threshold, SRAM bitcell data switches. This causes a SEU. CMOS scaling reduces inter-
transistor distance. Thus, numerous transistors can now be charged by a single particle
attack [ 2]. Charge sharing causes (SEMNUs), which have increased due to high-energy
particle impacts in nanoscale CMOS technology [3], [4]. Supply voltage reduction
increases circuit radiation vulnerability. Radiation-hardened digital circuitry technology is
crucial [5]. SRAM is more susceptible to soft mistakes than dynamic. Thus, nanoscale
technology increases SRAM soft mistakes [6]. SEUs can be reduced by using alternate
6T SRAM cell designs [7 –15]. The main way to reinforce circuit safety is to create a
cell-level transistor connectivity design. [7] I have successfully developed the Enable-
10T SRAM cell with enhanced soft error resilience. The system offers a differential read
operation and a robust noise buffer. The system is capable of restoring data exclusively
from "1" to "0" following Single Event Upsets (SEUs). Dual node feedback protects the
dual interlocked storage cell (DICE) [8] from single-event transients (SET). The
radiation hardness and immunity of SEMNU require enhancement. The memory cell
based on Schmitt trigger (STB)- 13T, as described in reference [4], successfully achieves
complete immunity against single-event upsets (SEUs). In contrast to DICE, SEMNU's
immune promotion is more limited, resulting in decreased, and a smaller layout space
requirement. Regrettably, there has been a decline in their writing speed and margin.

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According to the reference [10], it is recommended to

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utilize RH memory (RHM)-12T in radiation-hardened systems due to its advantageous

features such as low power consumption and high reliability. However, the utilization of
nMOS as pull-up devices resulted in a reduction of read noise margins. The memory cell
RHD-12T, which is resistant to radiation, was recently introduced as depicted in Figure
2(a) [12]. The system is capable of providing immunity to Single Event Upsets (SEUs) on
its internal nodes for SEMNUs. Regrettably, the device's reduced writing speed and
elevated power consumption impose limitations on its practical application. There are
potential design solutions that could enhance radiation tolerance without the need for
circuit reinforcement, as indicated by previous studies [13, 14]. Subsequently, LEAP-
DICE was developed based on this application. The TCAD simulations demonstrate that
the threshold for LET upset can be effectively increased, yielding positive outcomes.
Researchers used TIARA Monte Carlo simulation to study charge sharing [14]. TIARA
simulation data will prioritize susceptible transistor pairings in layout optimization.

2.5 Efficient Majority Logic Fault Detection With Difference-Set Codes

for Memory Applications
Storage of memory applications are experiencing a growing concern regarding single event
upsets (SEUs), which have an impact on digital circuits. Using majority logic decoding,
this study detects difference-set cyclic code errors. Logic decodable codes can fix many
defects, making them ideal for memory applications. However, decoding slows memory
operations. Without read data mistakes, the suggested fault-detection technique considerably
decreases memory access time. The majority logic decoder's failure detection algorithm
reduces space and power consumption. Spacecraft and avionics electronics are exposed to
severe radiation [1], [2]. ECCs and TMR are common mitigation strategies. Triple Modular
Redundancy (TMR) is a von Neumann application [3]. The majority of voters choose one
of three design iterations in this method. The complexity overhead of the technique is three
times higher than that of the majority voter, resulting in an increase in power usage. Error
Correction Codes (ECC) have been widely recognized as a highly effective method for
mitigating memory soft errors [2]. SEC-DED codes are highlysuitable for terrestrial
radiation environments characterized by low s oft error rates (SER) due to their
straightforward encoding and decoding requirements. However, as integration densities

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increase, there is a corresponding increase in soft mistakes. Consequently, more robust error-
correction methods are needed [4], [5]. The decoding process

involves the utilization of advanced algorithms, such as iterative algorithms like belief
propagation employed by basic graph decoders, as well as complex algebraic decoders that
employ floating point operations or logarithms to ensure timely decoding. Both advanced
options result in increased computational expenses [6]. ML decodable codes are a specific
category of low- density parity check (LDPC) codes that have been extensively researched [9
–11]. Difference- set cyclic codes (DSCCs) find application in Japanese teletext and FM
multiplex broadcasting systems [12–14]. The utilization of machine learning (ML) decoding
offers numerous benefits and is characterized by its straightforward implementation. The
process of ML decoding necessitates the allocation of computational cycles to decode a word
that has been encoded using a bit-coding scheme. This phenomenon has the potential to
negatively impact the performance of the system [6]. The utilization of concurrent encoders
and decoders can potentially address this challenge. This proposed solution would result in an
increase in both complexity and power consumption. The decoder is infrequently activated
due to the high rate of error-free memory retrieval attempts. As a result, a fault detector
module [11] was incorporated to identify code-word defects and initiate the necessary
corrective measures. In this scenario, the correction of code- words results in an acceleration
of the average read memory access. The implementation of this upgrade necessitates
additional hardware and power resources. Flash memory systems provide alternative options
[15].

2.6 Improving Error Correction Codes for Multiple-Cell Upsets in

Space Applications
The higher integrated density of CMOS technology has increased SRAM memory
system flaws. Single-cell or multi-cell disruptions are likely. Single-event upsets (SEUs) in
space- deployed MCUs are caused by cosmic radiation. ECCs are used in many sectors.
ECCs must balance error coverage and redundancy in space applications. ECC encoding and
decoding circuits need area, power, and delay efficiency. Coding using MCQs is suggested.
Matrix codes help MCUs address and identify patterns using Hamming codes and parity

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checks in a two-dimensional framework. The Column-Line-Code (CLC) improves space-

based Microcontroller Units (MCUs). The matrix code uses upgraded Hamming codes and
parity checks to provide Cross-Layer Coding (CLC). These algorithms are redundant. This
work analyzes novel redundancy-reducing Error Correction Codes (ECCs). Innovative Error
Correction Codes

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s(ECCs) correct multiple computing units (MCUs) while reducing storage, energy, and
processing time. Unlike Matrix and CLC codes, the new codes improve memory error
coverage. CMOS technology's reducing physical feature size is responsible for memory
systems' large storage capabilities.

Reducing size increases memory error rates (1), (2). Aggressive scaling has
reduced memory cell critical charge and storage SEU energy. [3]. several-cell upsets
(MCUs)—errors in several memory cells caused by one particle—have been studied.
Energy loss causes MCUs and the more common SCUs. [4–8]. Space fault tolerance
systems must include the MCU problem owing to the harsh environment and high-
energy cosmic radiation. [4], [7], [9]. ECCs have long protected memory systems. Single-
error correction (SEC) or single-error-correction-double-error-detection (SEC-DED)
codes are extensivelyused error correction codes (ECCs) to protect conventional
memories. [ 11]– [13]. SEC codes can fix memory cell faults, while SEC-DED codes can
fix errors in one or two cells. Space applications use complex coding. [14]–[17], [19]–
[21]. Hamming codes and paritychecks in a matrix format are typical coding systems
[17]. The coding system can correct two incorrect bits. A new study [19] uses column-
line-code (CLC) extended Hamming codes with parity bits to correct a maximum of two
consecutive erroneous bits. ECC memory requires redundancy. The extras find and fix
problems. Memory needs more bits to store data words redundantly. Unnecessary
elements use memory proportionally. Only 1 GB of a 2 GB memory module with ECC
redundancy can store the payload, or clean data. The code portions need 1 gigabyte.
ECCs require more area, power, and time from encoder and decoder circuits. Space
applications must minimize overhead costs.

2.7 Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM

Bit- CellDesigns for Highly Reliable Terrestrial Applications
Due to increased CMOS integration density, SRAM memory system defects have
increased. Single-cell or multiple-cell upsets are more likely. Cosmic radiation is known to cause
single-event upsets (SEUs) in space applications. ECCs are extensively used. ECCs must
balance error coverage and redundancy in space applications. ECC encoding and decoding
circuits must also be power-efficient, area-efficient, and latency-efficient. Multiple choice
questions (MCUs) have been suggested for coding. Matrix codes employ Hamming codes and
parity checks within a two-dimensional framework to facilitate the addressing and detection of

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patterns within

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microcontroller units (MCUs). The Column- Line- Code (CLC) was developed with the
purpose of enhancing the functionality of Microcontroller Units (MCUs) in space-based
applications. Matrix code with increased Hamming codes and parity checks is the CLC. These
algorithms share significant redundancy. This paper analyzes novel ECCs with reduced
redundancy. These ECCs rectify multiple computational units (MCUs)

while reducing space, power, and time. These novel codes can enhance memory error
coverage, unlike Matrix and CLC codes. CMOS technology's shrinking physical feature size
has increased memory systems' storage capacity. However, decreasing size has increased
memory error rates (1, 2). As a result of aggressive scaling, there has been a decrease in
the critical charge of memory cells and the energy required for storage single-event upsets
(SEUs). [3]. Multiple studies suggest that energy loss can cause multiple-cell upsets (MCUs).
Single particle impacts cause many memory cell faults in these MCUs. This energy loss
process also affects single-cell upsets (SCUs), which are more common [4–8]. The MCU
problem, caused by space environments and high-energy cosmic rays, must be considered
while building fault tolerance solutions for space applications. [4], [7], [9]. ECCs are
commonly used to secure memory systems. SEC or SEC-DED ECCs are used to protect
conventional memories [11– 13]. SEC codes may fix memory cell difficulties. SEC-DED
codes can fix faults in one or two memory cells. Space apps use complex coding. [14]–
[17], [19]–[21]. Matrix codes with Hamming codes and parity checks have become popular
coding systems. The current setup detects and fixes two errors. A recent study [19] found
that column-line-code (CLC) uses extended Hamming codes and parity bits to correct a
maximum of two consecutive erroneous bits. ECC memory requires redundancy. Additional
components help find and fix issues. Memory needs more bits to store data words
redundantly. Unnecessary elements use memory proportionally. The payload—the "clean"
data—can only be stored in 1 GB of a 2 GB memory module with full redundancy and ECC.
The code portions need 1gigabyte. ECCs require more area, power, and time from encoder
and decoder circuits. Space applications must minimize overhead costs.

2.8 Novel Low-Power and Highly Reliable Radiation

Hardened MemoryCell for 65 nm CMOS Technology
This research offers a low-power, reliable radiation-hardened memory cell (RHM-12T)

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with 12 transistors. TSMC 65 nm CMOS technology should reduce single event upsets.
The ṣ

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microcontroller units (MCUs). The Column- Line- Code (CLC) was developed with the
purpose of enhancing the functionality of Microcontroller Units (MCUs) in space-based
applications. Matrix code with increased Hamming codes and parity checks is the CLC. These
algorithms share significant redundancy. This paper analyzes novel ECCs with reduced
redundancy. These ECCs rectify multiple computational units (MCUs)

bombardment [1]. The occurrence of single event upsets (SEUs) can be attributed to particle-
induced charge resulting from heavy ions, as well as indirect ionization caused by protons and
neutrons. [2]–[5]. An energetic particle dissipates energy and forms electron-hole pairs in a
semiconductor device's sensitive node. The reverse-biased junction's depletion region's
electric field separates electron-hole pairs, improving drift processes. Consequently, the
sensitive node experiences an accumulation of excessive charge. [3]–[5]. The sensitive
node's value temporarily changes when the accumulated charge approaches a threshold and
generates a large voltage transient pulse (Figure 1(a)). High-sensitivity semiconductor device
regions have a considerable reverse bias, causing transient current to flow [4]. As seen in
Figure 1(b), radiation particles interact with PMO S transistors toproduce just a positive
transient pulse. Figure 1(c) shows that radiation particles colliding with NMOS transistors
produce only negative transient pulses.[6]. Unfortunately, particle radiation-induced SEUs are
compromising Nano-scale CMOS memory dependability. Cross-coupled inverter pairs in
SRAMs cause this [1]. Particle- induced charge from heavy ion direct ionization and protons
and neutron indirect ionization causes SEUs. [2]–[5]. An energetic particle dissipates energy
and forms electron-hole pairs in a semiconductor device's sensitive node. The reverse-biased
junction's depletion region's electric field separates electron-hole pairs, allowing drift
processes to efficiently gather particle-induced charge. The sensitive node accumulates excess
charge [3–5]. A large voltage transient pulse might result from accumulated charge reaching a
threshold. If its amplitude and duration meet specific parameters (see Figure 1(a)), this pulse
can momentarily change the sensitive node value. High-sensitivity semiconductor device
regions have a considerable reverse bias, causingtransient current to flow [4]. As seen in 1(b),
radiation particles interact with PMOS transistors to produce justa positive transient pulse.
Figure 1(c) shows that NMOS transistors only generate negative transient pulses when
radiation particles interact [6]. Regrettably, the utilization of radiation-hardened memory cells
results in enhanced resilience against Single Event Upset (SEU) while requiring reduced
space, power, and latency. SRAMs utilize a cross- coupled inverter pair. The memory cell

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Quadro-10T [14] employs negative feedback as a

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mechanism to mitigate specific faults.

2.9 Design for Soft Error Mitigation

Nanometric circuits exhibit increased susceptibility to perturbations. Minor errors that
were previously insignificant in space applications have now become significant concerns
for the reliability of Earth-based systems. SEUs affect memory cells, latches, and flip-flops.
However, latches and flip-flops coupled to combinational logic outputs can intercept SETs.
Alpha and atmospheric neutrons cause them. To overcome this issue, a designer needs a
variety of soft error mitigation strategies to address circuit geometries, design structures, and
design limits. This study analyzes SEU and SET mitigation techniques.This study provides
insights to help designers achieve their goals. VLSI technology has improved electronic
component reliability. However, fault tolerance has been limited to a few domains. Our
advances have reversed the above tendencies. Since nanometric technologies have reduced
device size, complexity, power supply, and operating speeds, deep submicron integrated
circuits (ICs) have become less reliable. Soft mistakes from cosmic ray-generated
atmospheric neutrons and radioactive isotope-emitted alpha particles are a major concern
[1]. Neutrons exhibit interactions with silicon, oxygen, and various other elements present
in chips, thereby leading to the occurrence of soft errors. Electrically charged
secondary particles from this interaction cause soft mistakes. Neutrons have no electric
charge, unlike alpha particles, which form electron-hole pairs. Consider that the contact
can generate several secondary particles that can affect multiple circuit nodes. Modern
methods have eliminated thermal neutrons and soft mistakes by eliminating boro-
phosphosilicate glass (BPSG) [2]. A transient current pulse is formed when an electrically
charged particle ionises near a sensitive node like an idle transistor drain. The sensitive node
collects a lot of charge carriers. This pulse affects the affected node's cell type. SEUs can
occur when a strong pulse is applied to a memory cell, latch, or flip-flop. Cells change.
Often happens. The logic gate collector node converts the transient current pulse into a
single-event transient (SET) voltage pulse. The current pulse, collecting node load, and
transistor strength dictate the SET's waveform and amplitude. Combinational logic
circuits connect pulses to latches and flip- flops. Gates are responsible for generating input-
output pairs. In the context of combinational logic, the propagation of pulses is influenced by
a controlling value applied to one of the gate inputs. This controlling value can be either a

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logical 0 or 1, depending on the specific gate

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being used, such as a NAND or NOR gate. This regulating value prevents gate mistakes
from spreading from input to output. Thus, transient pulse propagation is limited to a
sensitized pathway, where all input gates, except those within the pathway, have non-
controlling values. Pulse dispersion depends on pulse duration. When a pulse is shorter than a
gate's logic transition time, its propagation is inhibited. The pulse propagates unabated when
its duration exceeds twice a gate's logic transition. During propagation, pulses between these
values attenuate significantly.

2.10 A Soft Error Tolerant 10T SRAM Bit-Cell With Differential

Read Capability
Soft error-resistant characteristics and a differential read operation improve sensor
reliability in the quad-node, 10T SRAM cell. The redesigned SRAM cell features 26% less
leakage current and noise buffering of sub-0.45 V. The proposed cell has a noise margin
comparable to a 6T SRAM cell at half the supply voltage. Less leakage than the 6T cell. In
TRIUMF's accelerated neutron radiation experiments, a 90-nm CMOS 32-kb SRAM showed
98% soft error rate compared to the 6T cell. Nanoscale integrated circuits are sensitive to
particle-induced single event transients (SETs) [1]. Intergalactic radiation and some packing
materials cause SETs. Silicon ionization causes voltage transients at sensitive nodes [3].
Figure 1 displays a latch with cross-coupled inverters. Large amplitudes and durations
alter latch values, causing SEUs. A SEU is a "soft error". Soft errors can crash current
microprocessors [4]. Memory has more soft defects than logic. Memory's high component
density and absence of error-masking create this [5]. SRAM makes more soft mistakes than
DRAM due to its smaller node capacitance and larger sensitivity volume per bit [6].
Nanotechnology raises SRAM soft error rate (SER) [2 –7]. ECC or soft error-resistant
SRAM memory cells lower SEUs. Hardened cells are superior because Error Correction Code
(ECC) provides limited error correction and neutron- induced disturbances enhance multiple-
bit upsets [8]. Hardened 10T DICE is popular [9]. CMOS fuels the cellphone. Differential
read requires 12 transistors in Figure 2(a). Differential read reduces PVT-induced bit line
noise. Olson et al. [10] found a differential 10T SRAM cell that reduces SER and matches the
technique. A series NMOS transistor in the read current channel reduces read current in tight
spaces. Figure 2(b) displays a cross- coupled node capacitor 6T SRAM cell that reduces soft
error rate (SER) [11]. MIM capacitors require special methods. Two DRAM-like capacitors

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lower 6T cell soft error rates

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CHAPTER-3
INTRODUCTION TO EDA TOOL

3.1 TECHNOLOGIES USED (EDM)

Tanner EDA is a suite of tools for the design of integrated circuits. These tools allow
you to enter schematics, perform SPICE simulations, do physical design (i.e., chip layout),
and perform design rule checks (DRC) and layout versus schematic (LVS) checks. There
are 3 tools that are used for this process: S-edit – a schematic capture tool T-SPICE – the
SPICE simulation engine integrated with S-edit L-edit – the physical design tool Using S-
Edit (Schematic Entry Tool) & T-SPICE (Analog Simulation Tool).Curves of an NMOS
Transistor S-edit are a schematic entry tool that is used to document circuits that can be
driven forward into a layout of an integrated circuit. It also provides the ability to perform
SPICE simulations of the circuits using a simulation engine called T-SPICE. T-SPICE can
be setup and invoked from within S-edit.
Initially Setup your Directory Structure & download Libraries a) Log onto a
computer on 6th floor Cob Leigh. B) You want to create a directory for all of your Tanner
EDA projects. You also will need to download and unzip a set of library & model files
from the course website that will be used for your simulations. – Create a directory
structure named “EELE414_VLSI_Fall2011\Tanner Projects c) Go to the course website
and download the zip file called “Tanner_Libraries.zip”. Unzip it into your Tanner Projects
directory. These groups of files contain the necessary information to enter components into
S-edit (circuit symbols), perform SPICE simulations (models), and do physical layout
(layer definitions, DRC, LVS).

3.2 START NEW DESIGN & SETUP LIBRARIES

a) Start S-Edit: -
Start – All Programs – Tanner EDA – Tanner Tools v12.6 – S-Edit v12.6.
b) Start a New Design: -
Using the pull-down menus, create a new design: - File – New – New Design A dialog will

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appear asking for a design name and location. When you give the name, S-edit will create a
folder of that name in the directory that you provide that will contain all of the design files.
You should give a descriptive name that represents each simulation you will be running. –
Enter the name “HW03_NMOS_IV_Part1” and browse to your
“EELE414_VLSI_Fall2011\Tanner Projects” directory – Click “OK”.
c) Create a new Cell: -
A “cell” is a design element. A cell can contain multiple views such as schematics and
symbols. Cells can be instantiated in other cells. When performing a simulation, we will
typically call the cell “TOP”. When we are testing a circuit, for example an inverter, the
inverter will have its own cell that contains a schematic of the devices and a symbol. The
inverter cell is instantiated in the TOP cell that contains ideal elements such as voltage
sources and probes that are only used for simulation. This allows us to separate the cells
that are actually going to be implemented on the die versus cells that are only used for
simulation. Using the pull-down menus, create a new cell view: - Cell – New View: - enter
the cell name “TOP”. Ensure the design name is “HW03_NMOS_IV_Part1” and click OK.
You can leave the interface and view names “view0”. A blank schematic page will appear.
It is a good idea to save this right now.
D) Enter the symbol libraries: -
First, you need to include a library which contains the symbols for all basic circuit elements
such as resistors, NMOS, capacitors, etc.… The libraries for all the basic symbols are in the
Tanner_Libraries.zip file you downloaded and unzipped. – On the left side of the S-edit
screen you’ll see a Libraries window, click on the “Add” button. – Browse to “Libraries\
All\All. Tanner” and click “OK” You should see a set of libraries a appear:

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Figure 3.1: Start of new design and setup libraries

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3.3 SETUP THE SPICE MODELS FOR THE GENERIC_025 KIT

The libraries that you just added have symbols for NMOS and PMOS transistors.
However, all non-linear components such as MOS transistors require a model to describe
their behavior. If you simply enter an NMOS symbol in your schematic, SPICE will not
know what to do since each NMOS transistor fabricated in a different technology behave
differently. In this example, we will use a transistor technology called “Generic_025”,
which represents a standard, 0.25um CMOS process. You will need to setup the SPICE
models for this process in S-edit. Once you do that, when you enter an NMOS or PMOS
transistor, you can then associate the 0.25um model to that symbol. Using the pull-down
menus, setup the SPICE models: - Setup – SPICE Simulation – In the dialog that appears,
you should highlight “General” on the left. – On the right, click in the “Library Files” field.
This is where you will specify any SPICE models you will be using in your simulations.
Browse & select “Generic_025_Kit\ Generic_025_SPICE_Models_Level1.lib” – On the
right, click in the “SPICE File Name” field. This is where you specify the name and
location of the SPICE Net list output. Browse to your design directory
“EELE414_VLSI_Fall2011\Tanner Projects\HW03_NMOS_IV_Part1” and enter the
filename “Top’s”. – On the right, click in the “Simulations Results File Name” field. This
is where the results of the simulation will be written. This file is what the waveform viewer
will look for when you go to plot your results.

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Figure 3.2: Setup of SPICE models

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Browse to your design directory “EELE414_VLSI_Fall2011\Tanner Projects\

HW03_NMOS_IV_Part1” and enter the filename “TOP. Out”.
Before you can exit this window, you will need to select an analysis type. We will setup the
details of the analysis later, but for now, just check the “DC Sweep Analysis” and click
“OK” to close the setup window.

Figure 3.3: Selecting DC sweep analysis

3.4 ENTER THE SCHEMATIC TO SIMULATE THE IV BEHAVIOR

OF AN NMOS TRANSISTOR
A) We will be entering the following circuit:
Enter the NMOS transistor – On the left, click on “Devices” in the upper window.
This will display all of the symbols available in this group. You should see all of the
components that you can implement on a CMOS integrated circuit. – On the bottom left
window, click once on “NMOS”. You should see the symbol of the NMOS transistor show
up in the symbol viewer window at the bottom. – To place the NMOS, you will insert-
“Instance” button. Two things happen when you click on this button. First, a dialog will
appear that will allow you to setup the parameters for the NMOS. Second, the symbol will
attach to your mouse. We will place the NMOS in the schematic first and then set its
properties later. This is an easier way to enter the device.

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Click in the schematic window to drop an instance of the NMOS. Hit the “Esc” button to
end the insert-mode.

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Figure 3.4: Setup properties of transistor

Figure 3.5: Schematic diagram of the transistor

The NMOS is now in the schematic. A note on zooming: - [Home] = zoom fit – [-] = zoom
out – [=] = zoom in – the scroll wheel also zooms in/out. – To setup the

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NMOS, click on the NMOS symbol. You will see the properties of the device on the left.
We want to setup the following: - Model: enter “NMOS”. This model is found in the
Generic_025 library you added – Name: M1. The SPICE designation for MOS transistors
is to have the

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name start with an “M”. S-edit automatically appends an M to the name is the final name
will be “MM1” in the Top’s file. But it is good practice to name all MOS transistors with
M’s. – W Set to 2.5u. This is the default. – L Set to 0.25u. This is the default.
B) Enter a DC source for VGS:
Using the same process, you used for the NMOS symbol, enter a “SPICE Elements:
Voltage Source”. This is a generic voltage source symbol that is configured as a DC,
TRAN, PWL, etc. In its properties dialog, – Click on the voltage source and enter the
following: - Master Interface: DC (this is the default but this is how you would change it to
something else. – Name: VGS_Source (it is a good idea to use descriptive names) – V. This
is where you will set the DC voltage (i.e., 4v, 5v). However, for this example we will use a
parameter instead of a hardcoded value. We will enter a parameter name here and then set
up the parameter later. Enter “VGS_param” for the value of V. When performing a DC
sweep, you must use parameters for the sweep.
C) Enter a DC source for VDS:
Using the same process as above, enter a DC source for VGS with the following: - Master
Interface: DC (this is the default but this is how you would change it to something else. –
Name: VDS_Source – V “VDS_param” Position the sources as in the following figure:
Enter wires by clicking on a symbol node and then dragging. Enter corners by
clicking once where you want to turn. – You can label nets using the “Net Label” icon at
the top.
D) ENTER GROUNDS:
Using the same process as above enter 3 grounds from MISC-GND.
The source is connected to the ground.

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Figure 3.7: Connect the ground

E) Enter wire:
You can enter wires by clicking on the “wire “icon at the top.
Enter a Current Probe to monitor IDS.
Enter the SPICE Commands: Print Current component. This doesn’t connect to anything.
You just place it anywhere and then tell it what current to monitor in its properties dialog. –
In its properties dialog, setup:
Terminal: D (this is the Drain of the NMOS)
Device: MM1 (this is the name of the device. Notice that we called it M1, but S-edit
automatically appends another M to the name. You will only see this once you run the
Netlist. Analysis: DC (VERY IMPORTANT TO SELECT THIS!!!!)

3.5 SETUP THE PARAMETERS THAT WILL BE USED DURING

THE DC SWEEP ANALYSIS
When we entered the VGS and VDS sources, we set their values to “VGS param” and “VDS
param”.
We now need to setup these parameters.

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Using the pull-down menus: -

Setup – SPICE Simulations
On the left, click on “Parameters”.

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DC analysis is done in the settings.

In the Figure 3.9 Adding parameters folder on the right, click on the “Add Parameters”
button (it is in the upper right corner next to the red X)
Enter: Name: VGS_param
Value: 1v – On the right, click on the “Add Parameters” button
Enter: Name: VDS_param

Figure 3.8: DC analysis

Figure 3.9: Adding parameters folder

Value: 2.5v
We will overwrite these values during our sweep, but the parameters need to exist first.
Part 5: Setup the SPICE DC Sweep Analysis.
Using the pull-down menus:
Setup – SPICE Simulations

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On the left, click on “DC Sweep Analysis”
On the right, enter the following for Source (this is what will be swept)
Source or Parameter Name: VDS_param

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Start Value: 0
Stop Value: 2.5 Step: 0.1
Sweep Type: Lin
On the right, enter the following for Source (this is what will be swept)
Source or Parameter Name: VGS_param
Start Value: 1
Stop Value: 1.5 Step: 0.5
Sweep Type: Lin
NOTE: The first parameter you setup in this dialog will be plotted on the independent
axis. Part 6: Simulate the Design

Figure 3.10: Graph of VDS VS Current

First, check you design using the pull-down menus:
Tools – Design Checks (any warnings or errors will be shown at the bottom)
Simulate your design:
Clock on the Green Arrow to start the simulator:
The T-Spice window will appear. If everything is OK, the waveform viewer will also
appear. If everything worked, your waveforms should look like this:
a) View the Netlist:
In the T-spice window, right click on the file at the bottom and select “Show Netlist”. This

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will bring up the top’s Netlist that was created and used by the spice engine. This is a good
place to look when you get errors. This is the text-based description of what you entered in

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S-edit.

Figure 3.11: Spice engine to check errors

View the Waveform: - If the windows viewer did NOT automatically appear, you can click
on the file in the T spice window and select “Show Waveform”.

3.6 TRANSIENT ANALYSIS OF A CMOS INVERTER & SYMBOL

CREATION
Part 1: Start a New Design, Setup Libraries & Setup Simulation
In this we will create a CMOS inverter and simulate its transient response. We
will create an inverter design that contains a symbol and then instantiate it in another
schematic to stimulate the circuit.
Symbols are handled by adding another view to a design. We will start by creating a
design called “Inverter” and then create a schematic view. This schematic will contain an
NMOS and PMOS wired as an inverter. We will add “Ports” for the Input, Output, VDD,
and VSS. We will then add a symbol view to this design. The symbol will contain the
inverter shape and the corresponding pins for Input, Output, VDD, and VSS.
We will then create a separate schematic called TOP that will be used to test the
inverter. We will instantiate the inverter symbol in TOP. We only want to put items into the
inverter design that can be fabricated. TOP will contain the ideal voltage sources to provide

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the input waveform, the power supplies, and a mock load. In this way, when we go into
physical design (i.e., layout), we only drive forward the isolated circuits.
-Start S-Edit

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-Create a new design called:

“EELE414_VLSI_Fall2011\Tanner Projects\HW04_INV_Transient_Part1”
-Add the Tanner Projects\Libraries\All\All. Tanner library to the library list on the left
-Create a new Cell called “TOP” using the Pull-down Menus
-Cell – New
View Name =
TOP
View Type = schematic
-Setup the simulation using the Pull-down Menus:
-Setup – SPICE Simulation
-Highlight the General Tab of the Setup SPICE window and set the following:
SPICE File Name: \HW04_INV_Transient_Part1\top’s
Library Files: ..\Generic_025_Kit\Generic_025_SPICE_Models_Level1.lib
Simulation Results File Name: File Name: \HW04_INV_Transient_Part1\TOP.
Out
-Check the “Transient/Fourier Analysis” box on the left and set the following:
Stop Time = 2ns Maximum Time Step = 10ps
-Click “OK”
Part 2: Create the Inverter:
a) Create a new schematic view using the pull-down menus:
-Cell – New
View Name =
Inverter
View Type = schematic
b) Enter the inverter schematic:
Entering the NMOS:
Name =
M1 L =
0.25u W =
2.5u
Model =NMOS

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-Entering the PMOS:
Name =
M2 L =
0.25u W =
5.0u
Model =PMOS
-Entering the Ports:
Ports are entered using the icons on the top of the S-edit window. Enter the following:

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In Port: Name it “IN”

Out Port: Name it
“OUT”
In/Out Port: Name it
“VDD” In/Out Port: Name
it “VSS”
-Wire up the Inverter
Enter wire connections as shown in the previous figure.
a) Export a SPICE Netlist
Exporting a SPICE Net list is a good idea in order to verify that you have entered the
schematic correctly. Also, this Netlist will be used later when performing a “Layout versus
Schematic (LVS)” check. We want to export a Netlist at the Inverter schematic cell level so
that a Netlist of just the inverter exists for LVS. When we conduct the simulation of this
inverter, we will create a TOP level schematic that will have a Netlist containing ideal
voltage sources. This Netlist can’t be used for LVS since it contains components that won’t
be fabricated.
With the schematic open, use the pull-down menus to perform:
-File – Export – Export SPICE.
-Browse to your design directory and give the file name “Inverter.spc”.
-Click “OK”
If you open the Inverter.spc with a text editor, you will see the following:
A note on drawing:
The “Path” icon will put you into a mode where you can draw lines that are not wires.
The “Circle” icon will allow you to enter the inversion bubble.
The ports can be moved by holding down “alt-m”
The ports can be rotated by selecting and pressing the “r” button
Remember to save.

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Figure 3.12: Export SPICE net list

Part 3: Create the TOP schematic to test the Inverter
a) Instantiate the Inverter in the TOP schematic
Open the TOP schematic view using the pull-down menus:
Cell – Open View:
Cell Name: TOP
View Type: schematic
In the library windows on the left of the window, highlight your
“HW04_INV_Transient_Part1” library. In the lower left window, you will see your two
Cells “TOP” and “Inverter”.
-Click on “Inverter” and you will see your symbol show up in the symbol viewer.
-Click on the “Instance” button and place your symbol in the TOP schematic.
a) Enter the following circuit in order to power and stimulate your inverter:
A note on drawing:
The “Path” icon will put you into a mode where you can draw lines that are not wires.

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Figure 3.13: Symbol of inverter

The “Circle” icon will allow you to enter the inversion bubble.
The ports can be moved by holding down “alt-m”
The ports can be rotated by selecting and pressing the “r” button Remember to save.
Part 3: Create the TOP schematic to test the Inverter
a) Instantiate the Inverter in the TOP schematic

Open the TOP schematic view using the pull-down menus:

-Cell – Open View:
Cell Name: TOP
View Type: schematic
In the library windows on the left of the window, highlight your
“HW04_INV_Transient_Part1” library. In the lower left window, you will see your two
Cells “TOP” and “Inverter”.
-Click on “Inverter” and you will see your symbol show up in the symbol viewer.
-Click on the “Instance” button and place your symbol in the TOP schematic.
a) Enter the following circuit in order to power and stimulate your inverter:
Enter the Pulse Voltage Source. All voltage sources are the same component in the SPICE
Elements library. The default is DC, but this can be changed to any other type
of source in the properties dialog.
Name = Vin Source

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Figure 3.14: Symbolic view of inverter

Master Interface = Pulse
Period = 1ns
Pulse Width =
0.5ns
V High =
2.5v V Low =
0v
Rise Time =
10ps Fall Time =
10ps
-Enter a Load capacitor from the Devices library.
Name = Cloud
C =50 fF
-Enter a DC Source for
VDD Name = VDD_Source
Master Interface = DC
V = 2.5v
-Enter the grounds from the Misc. library

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-Enter wire connections and name them Vin and Vout

-Enter a voltage probe for both Vin and
Vout Part 4: Simulate the Design
a) First, check you design using the pull-down menus:
-Tools – Design Checks (any warnings or errors will be shown at the bottom)

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b) Simulate your design:

-Clock on the Green Arrow to start the simulator:
The T-Spice window will appear. If everything is OK, the waveform viewer will also
appear. If everything worked, your waveforms should look like this:

Figure 3.15: Output waveforms of inverter

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CHAPTER- 4
METHODOLOGY WISE ANALYSIS
4.1 Soft Error Hardened Memory Design for Nano-
scale ComplementaryMetal Oxide Semiconductor
Technology
Radiation-induced SEUs degrade nanoscale memory. This study creates a soft-error-
resistant memory cell using SEU physics and a well-structured layout-topology technique.
65 nm CMOS builds the memory cell. Toughened memory cell read/write access time,
power cost, and layout area are also studied. The suggested cell has full fault tolerance for
radiation- rich memory applications. Monte Carlo simulations evaluate PVT variations.
Simulations show that the proposed cell can withstand multiple-node disruptions despite
process, voltage, and temperature (PVT) changes. Single event upsets (SEUs) from alpha
particles, neutrons, and protons from packaging materials and cosmic rays impair Nano- scale
memory design dependability and accessibility [1-3]. CMOS decreases supply voltage and
node capacitance, making memory cells more radiation sensitive [4 -7].voltage and node
capacitance, making memory cells more radiation sensitive [4-7].

Fig. 4.1: Previous radiation hardened memory cells. (a) Cell NS [11], (b) 13T

Single Event Upsets (SEUs) can change memory cell data, disrupting electronic systems [4].
SEUs can be fixed in later write or reset operations, making them soft errors [4], [5]. Soft
mistakes can be essential in critical memory applications like cardioverter defibrillators [8].

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Thus, to reduce the effects of radiation-rich single-event upsets (SEUs), memories must be
protected. Triple modular redundancy (TMR) reduces memory damage from single event
upsets (SEUs). Triple Modular Redundancy (TMR) would require a lot of space and power,
making it impractical for most systems [9], [10]. To boost SEU tolerance, alternative circuit-

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level hardening strategies include utilising radiation-hardened memory cells. NMOS stacked
(NS) memory cells minimize single event upsets (SEUs) between states 0 and 1 [11]. This
fortified cellular structure cannot attenuate single-event upset (SEU) defects, which is a major
problem. As CMOS technology scales, charge sharing- induced multiple-node upset is rising
[12, 13]. Thus, contemporary memory systems must consider this feature. The 13 transistors
memory cell (13T), developed in reference [14], addresses multiple-node upset. This design
enhances essential charge sharing by using the Schmitt trigger's hysteresis effect.

4.2 Design of Area-Efficient and Highly Reliable RHBD 10T

Memory Cell for Aerospace Applications
This research proposes a reliable 10T memory cell for aerospace radiation conditions.
The design considers physical upset mechanisms and transistor size. The memory cell being
proposed exhibits a compact size, minimal power usage, and exceptional stability, it has been
observed that the radiation-hardened-by-design 10T cell exhibits resilience againstsingle node
upsets in both 0 to 1 and 1 to 0 transitions. However, this resilience requires longer read/write
access time. SRAMs are widely used in aerospace electronic systems for their delay, area,
power, and crucial dependability [1]. SRAMs' reliability is limited by energetic particles in
aerospace engineering. Single event upsets (SEUs) are a significant cause of reliability failure,
leading to temporary alterations in stored values and subsequent electrical system malfunctions
[2]. Drift devices have the capability to collect and amass the generated charge resulting from
the collision of a charged particle with a sensitive integrated circuit node. The stored value of
the sensitive node undergoes a change when the accumulated charge surpasses the switching
threshold of the circuit. The 6T SRAM cell is constructed using a pair of interconnected
inverters. The modification of a stored node's value has the potential to trigger a positive
feedback mechanism, resulting in the alteration of another susceptible node's state. Therefore, it
is possible for memory errors to occur.

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Fig. 4.2. Schematic of the proposed RHBD 10T memory cell

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Overwriting processes recover damaged data, resulting in soft errors [3], [4]. In CMOS
process technology scaling, increasing densities, decreasing critical charge, and decreasing
supply voltage exacerbate SRAM cell reliability difficulties [1]. Aeronautical applications
demand improved soft error robustness due to cosmic radiation. As a result, an area-
efficient and dependable radiation-hardened-by-design (RHBD) memory cell is required
[5], [6]. Recent RHBD (Radiation Hardened by Design) cell research has focused on
enhancing memory cell fault tolerance via circuit-level redundancy or reconfiguration.
Jung et al. (2017) used a layered architecture to introduce the PS-10T and NS-10T
radiation- hardened by design (RHBD) memory cells. These memory cells have limited
Single Event Upset (SEU) robustness due to a design flaw. Only 0 1 SEU events can be
recovered by the NS-10T cell. The PS-10T cell can withstand a single event upset (SEU)
that changes a logical 1 to a logical 0. It is unable to respond to a SEU that changes a logical
0 to a 1. Jahinuzzaman et al. (2018) created a RHBD Enable-10T memory cell that
addresses the 1 0 transition to prevent single event upsets (SEUs). This method reduces
SEUs through negative feedback. Reference [9] presents a RHBD 11T memory cell. By
blocking the feedback channel, this memory cell preserves its stored value. Due to its
single- ended form, the RHBD 11T memory cell cannot write or read differentially.

4.3 Radiation-Hardened 14T SRAM Bitcell With Speed and

Power Optimized for Space Application
This study covers the space-applicable radiation-hardened with speed and power optimized
(RSP)-14T 14-transistor SRAM bit-cell. By improving circuit and layout levels, the newly
proposed structure avoids single-event and single-event-multiple-node upsets in 65-nm
CMOS technology, according to 3-D TCAD mixed-mode simulations. Charge-sharing
OFF- transistors strengthen structures. HSPICE calculations demonstrate that the RSP-14T
memory cell writes 65% faster and uses 50% less power than the radiation hardened design
(RHD)-12T. SEUs are harmless SEEs [1]. Radiation ionizes semiconductors. Device-
responsive parts cost more. Voltage fluctuations will affect nodes. Figure 1 shows a Single
Event Upset (SEU) caused by data transfer. CMOS shrinks transistors. Thus, single-
particle charge deposition affects numerous transistors [2].

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Fig. 4.3. (a) RHD-12T bitcell.

Charge sharing causes SEMNUs in nanoscale CMOS [3], [4]. Reduced supply
voltage renders circuits radiation-prone. Radiation-hardened digital circuit technologies
are in demand [5]. SRAM has more soft mistakes than DRAM due to its higher sensitive
volume per bit and lower node capacitance. Nanometer SRAM technology increases the
soft error rate (SER) [6]. To lower SER, several 6T SRAM cell replacements have been
proposed [7 - 15]. Building a cell-level transistor architecture for circuit-level protection is
part of the reinforcement process. The Enable-10T SRAM cell, described in reference
[7], is resistant to soft errors and supports differential read operation with a large noise
margin. It can only go from "1" to "0" and cannot recover from a single event disruption
(SEU). As a result, SEU immunity is restricted, as seen by feedback on its dual node
layout. SEMNU immunity and radiation hardness, on the other hand, can be improved. The
Schmitt trigger- based (STB)-13T memory cell is completely resistant to single-event
perturbations (SEUs) [4].
When compared to DICE, the restricted immunity improvement of SEMNUs
reduces writing speed, increases power consumption, and increases layout area. Reference
[9] launched the STB13T-based RHD-11T and RHD-13T hardened memory cells. Memory
cells that are resistant to radiation are dependable. Unfortunately, they write more slowly
and legibly. In a previous study (reference [10]), the RH memory (RHM)-12T was
introduced for radiation-hardened applications requiring low power and dependability.
nMOS pull-up devices were used in this design to reduce read noise margins. In a recent

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study [12], the RHD-12T memory cell with good radiation hardness was introduced
(Figure 2(a)). SEUs and SEMNUs can be tolerated on any of the system's internal single

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nodes. Unfortunately, the write speed and battery consumption limit its usefulness. Special
designing strategies, in addition to circuit reinforcement, can improve radiation tolerance.
[13], [14].

4.4 SOFT ERROR RATE MITIGATION TECHNIQUES FOR

MODERN MICROCIRCUS
This work introduces a new strategy for reducing alpha and neutron-induced soft
mistakes in deep submicron microcircuits. Temporal sampling hardens against static latch
SEUs and SET-induced mistakes. This method minimizes modem microcircuit soft error
rate (SER) without affecting design flow, physical layout, or circuit. Radioactive decay in
impurities creates alpha particles. Silicon elastic scattering and nuclear reactions damage
deep submicron microcircuits with high-energy neutrons [51]. A heavy ion recoil
reaction passes a hyproduct through a junction, creating a current pulse with equal
charge collection. Cosmic ray showers produce high-energy neutrons on Earth and in high-
altitude airplanes. Space-born energetic heavy ions undertake nuclear reactions in the
atmosphereto create these showers. Temporal sampling has worked well in space-based
microelectronics and can be used [SI]. This work develops actual circuit implementations
for terrestrial, high altitude, and spaceborne to improve the core temporal sampling
methodology. This study will show that temporal sampling can achieve triplespatial
redundancy without atmospheric circumstances. Duplicating actual circuitry is essential.
This research concludes by examining temporal sampling size-speed tradeoffs.

4.5 Efficient Majority Logic Fault Detection With Difference-Set Codes

for Memory Applications
Memory applications now worry about single event upsets (SEUs) modifying digital
circuitry. This study proposes majority logic decoding to detect difference-set cyclic code
problems. Majority logic decodable codes may fix many errors, making them suitable for
memory applications. Decoding these algorithms takes a long time, which hurts memory
performance. Fault-detection decreases memory access time for error-free data reads. The
majority logic decoder detects failures while saving space and electricity. Memory
stability has been harmed by technology scaling, which involves shrinking dimensions,

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increased integration densities, and lowering operating voltages. [1], [2]. SRAM memory
failures are rising, threatening application reliability.

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TMR and ECCs are two typical mitigating strategies. TMR is a von Neumann
method [3]. It entails simultaneously implementing three design alternatives, with the
outcome determined by a majority vote. The proposed methodology would triple the
complexity of the majority voter. The amount of energy consumed would increase. ECC
codes are the most effective at reducing memory soft mistakes [2]. Due to their low
encoding and decoding complexity, SEC-DED codes work well in terrestrial radiation
conditions with low soft error rates (SER). Higher integration density, on the other hand,
increases soft errors, necessitating better error correction [4], [5].

Fig. 4.4. Schematic of an ML decoder. I) cyclic shift register. II) XOR matrix. III)
Majority gate. IV) XOR for correction

This task is incompatible with (BCH). This behaviour could be explained by

complex algebraic decoders with floating point calculations or logarithmic functions.
These decoders decode data for a predetermined period of time. Iterative graph decoders,
such as belief propagation, are also employed. These intricate characteristics raise
computing expenses [6]. Cyclic block codes are ECC codes with robust error correction
and low decoding complexity. According to sources [7, 8], they can be decoded using
majority logic (ML). Previous research looked towards ML decodable LDPC codes [9-
11]. DSCCs are commonly employed Because ML decoding is straightforward to
implement, it is both practical and simple. To decode a coded word with -bits, ML

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decoding requires a specific number of cycles, which might have an impact on system
performance [6]. As a result, a defect detector module [11] examines the code-word
for errors and
commences the rectification procedure. Only the wrong code-words need to be corrected

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in this scenario. As a result, while the average read memory access is faster, hardware
prices and power consumption rise. A similar claim was made in a flash memory study
(reference 15).

4.6 Improving Error Correction Codes for Multiple-Cell Upsets in Space

Applications
CMOS integrated density has increased SRAM memory system defects. SCUs
and MCUs are more likely. Single-event upsets (SEUs) in space-related MCUs are caused
by cosmic radiation. ECCs are often used. In space applications, error coverage and
redundancy must be balanced with efficient area, power, and delay error correcting code
(ECC) encoding/decoding circuits. MCU mistakes can be reduced using various coding
strategies.

Fig. 4.5. Block diagram of the fault injector simulator

Memory mistakes have increased as a result of the size reduction [1], [2]. MCUs are
particle impact-induced mistakes in multiple memory cells. [4]–[8]. Fault tolerance
approaches for space applications must address the microcontroller unit (MCU). Space is
hostile due to high-energy cosmic particles [4], [7], [9]. Memory systems have used
ECCs to prevent errors. In conventional memory, single-error correction (SEC) or SEC-
DED codes are utilised [11-13]. Memory cell defects are repaired using SEC codes. SEC-
DED codes can identify two separate cell mistakes while correcting a single memory cell
error. Complex codes are required for space exploration [14-17], [19-21]. The Matrix
code
[17] is well recognised. configuration detects and corrects two erroneous bits. The
recently devised column-line-code (CLC) [19] corrects up to two consecutive bit errors

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using extended Hamming codes and parity bits.

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4.7 Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-

Cell Designs for Highly Reliable Terrestrial Applications
This study introduces 130 nm CMOS and 10T/12T QUCCE. QUCCE 10T and 12T have
twice and 3.4 times the 6T minimum critical charge. QUCCE 10T and 12T SRAM cells
excel in soft error tolerance, temporal performance, read and hold static noise margins.
Similar QUCCE 10T cell area and leakage power cost. QUCCE 10T uses high-density
SRAMs. The 6T reads twice as fast as the QUCCE 12T. High-speed SRAM. QUCCE
12T has the biggest near threshold voltage read margin after the 8T. This voltage reduces
other cell write failures.

Fig. 4.6. Quadruple cross-coupled storage cell QUCCE 10T.

Thus, the QUCCE 12T is suitable for low-voltage terrestrial dependability

applications. Scaling electronics reduced supply voltage and internal node capacitance.
Reducedcapacitance and voltage reduce the critical charge needed to disturb a circuit
node's logic state. SEE makes circuits more susceptible [1-4]. Aeronautical integrated
circuits and other high-reliability terrestrial applications worry about SEE. SEEs on Earth

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are caused by cosmic ray alpha particles, high-energy neutrons, and thermal neutrons
mixing with 10B in device materials [3].

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Electron-hole pairs emerge when high-energy particles interact with silicon. An

electric field splits electron-hole pairs when the trail hits the depletion area, causing their
immediate buildup and glitch. Reverse-biased diffusion components characterize circuit
sensitivity. When accumulated charge exceeds the critical charge threshold, combinational
logic circuits experience a single event transient (SET). Latch, flip- flop, and memory
SETs create single event upsets (SEUs) [4]. Due to their great density, low node
capacitance, and lack of error masking, SRAMs make soft mistakes [5].

4.8 Novel Low-Power and Highly Reliable Radiation Hardened Memory

Cell for 65 nm CMOS Technology

Low-power, radiation-resistant memory cell RHM-12T. 12-transistor TSMC 65 nm CMOS

reduces single event upset. The cell can survive sensitive node perturbations of any
polarity or severity. The cell recovers from charge sharing on fixed nodes-induced
multiple- node disturbances regardless of stored value. Radiation-hardened memories
match static power, area, and access time. Particle radiation-induced SEUs endanger
nanoscale CMOS memory [1].

Fig. 4.7. SEU in an inverter and upset polarity waves: (a) SEU physics mechanism; (b)
when PMOS is struck, a positive transient pulse is induced ; (c) when NMOS is struck a
negative transient pulse is generated .

4.9 Design for Soft Error Mitigation

Disturbances affect nano-metric circuits more. Soft faults formerly plagued space
applications now affect ground-level systems. Alpha and atmospheric neutrons cause

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memory cell, latch, and flip-flop SEUs. These particles also collect SET in combinational
logic output latches and flip-flops. To solve this, designers must utilize soft error

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mitigation solutions adapted to circuit structures, design architectures, and constraints.

Designers benefit from SEU and SET mitigation. VLSI boosted electronic component
reliability but limited fault tolerance to a few domains. Habits altered suddenly.

Fig. 4.8. Elimination of extra delay in the path of write data.

Nanometric device shrinkage, complexity, power supply drop, and operating speeds
diminish deep submicron integrated circuit reliability. Cosmic ray atmospheric neutrons
and radioactive isotope alpha particles soften packing, bonding, and die materials [1].
Neutrons form electrically charged secondary particles with silicon, oxygen, and other chip
components, causing soft failures. Neutrons are nonconductive. Alpha particle electron
hole pairs. Contact may generate secondary particles that affect many circuit nodes. BPSG
removal lowers thermal neutrons [2]. An electrically charged particle ionizes a sensitive
node, usually an off transistor drain, generating a short current pulse. The sensitive node
collects most produced charge carriers. Cell type determines how this pulse affects nodes.
Strong pulses SEU memory, latches, and flip-flops. Soft error. The collecting node of a
logic gate converts the transient current pulse to a voltage pulse (single-event transient, or
SET) whose form and amplitude depend on the current pulse and node electrical
parameters (load and transistor strength). Combinational logic powers latches and flip-
flops. Multiple gate input-output pairs. Combinational logic prevents gate output faults by
setting one gate input to 0 or 1. Sensitized channels only pass non-controlling transient
pulses.

4.10 A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read
Capability
Quad-node, differential read 10T soft error-resistant SRAM cells enable reliable

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sensing. Intergalactic ray alpha particles and packing material cosmic neutrons form SETs.
Silicon ionization creates sensitive node voltage transients. [3]

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Fig. 4.9. a) 12T DICE cell for differential read/write and b) standard 6T cell with cross-
coupled node capacitor

Fig. 4.9 shows a cross-coupled inverter latch event. SEU occurs when large transient
amplitudes and durations affect the latch value. SEUs are called "soft errors" because they
don't damage the device. Soft mistakes can crash modern microprocessors [4]. SRAM
softerror rate (SER) grows as nanometre technology scales [2], [7]. SRAM SER is limited
by ECC memory cells. ECC's limited multiple-bit error correcting capacity and risk of
neutron- induced multiple-bit upset make hardened cells preferable. [8]. The 10T DICE is
the most popular toughened cell [9]. This cell is CMOS-compliant, however differential
read requires 12 transistors (Fig. 2(a)). Differential reading shields bit line noise from
variations in process voltage and temperature (PVT). Another process-compatible
differential 10T SRAM cell with a lower SER was reported by Olson et al. [10]. A series
NMOS transistor on the read current path reduces read current under area constraints. SER
decreases significantly ina 6T SRAM cell with a cross-coupled node capacitor (Fig. 2(b))
[11]. The top-cell metal- insulator-metal (MIM) capacitor requires special construction.
Two special-process DRAM- like capacitors minimize SER in 6T cells [12].

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CHAPTER -5
DESIGN, IMPLEMENTATION & RESULTS
5.1 Existing method
Figure 5.1 depicts the SARP12T design. Q and QB are SARP12T's storage nodes, S1
andS0 are its internal nodes, while WL and WWL are its word lines. N7 and N8 WL-
controlled access transistors connect storage nodes Q and QB to bit lines BL and BLB.
WWL control links internal nodes S1 and S0 to bit lines BL and BLB via access
transistors N9 and N10. This study investigates SARP12T and comparison cells with a
value of "1," specifically Q = "1" and QB = "0." S1 and S0 are "1" and "0." The
subsequent sections provide elucidations on the fundamental operations of SARP12T and
an analysis of SEU recovery, considering these factors. Standard procedures refer to
established protocols or guidelines that are followed in order to ensure consistency,
efficiency, and effectiveness in various processes or activities. These procedures are
typically based on best This subsection provides an overview of the core functionalities
that have been planned for the SARP12T. Hold Operation: During the hold mode, the
access transistors in both pairs are maintained in the OFF state by grounding both the
wordline (WL) and wordline well (WWL). During the hold mode, the pre-charging of bit
lines to VDD is implemented as a means to minimize the read delay.

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Fig 5.1 12T SRAM with multi-node soft error

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BLB is at VDD and BL is at GND to write a "0" at Q to modify the recorded data.
BL's link to GND-connected N7 and N9 lowers nodes Q and S1. Node Q activates P2 and
deactivates N6, while S1 deactivates N2 and N3. BLB collects QB and S0
simultaneously using N8 and N10. Node QB activation turns N5 ON and P1 OFF. S0
activates N1 and N4. P1- P2 cross-coupling amplifies Q-QB potential difference. N3-N4
connector increases S1
- S0 voltage difference. Thus, writing succeeded.

Fig 5.2 12 simulation results of SRAM with multi-node soft error

Read Operation: WL is connected to VDD and WWL is deactivated during read operation.
Thus, access transistors N7 and N8 activate while N9 and N10 stay dormant.

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Fig 5.3 Write “0” and read operations

Write “0” operation

WL=1,WWL=1,BL=0,BLB=1,Q=0,S1=0,QB=1,S0=1
READ OPERTAION
WL=1,WWL=0,BL=1(PRECHARGED),BLB=0,Q=1,S1=1,QB=0,S0=0

For read operation, Bit-lines have already been charged to VDD. BLB therefore releases
through N8, N2, and N3. N1 and N4 being OFF, however, causes BL to remain at VDD
(Fig. 3). A sensing amplifier can read data when BL and BLB reach 50 mV.

A. Basic Operations
This sub-section covers all SARP12T operations.
1) Hold Operation: Grounding the wordline (WL) and wordline well (WWL)
keeps pairs of access transistors off during hold mode. Pre-charging bit lines to
VDD during hold mode reduces read time. Thus, while the cell is held, only
transistors P1, N2, N3, and N6 are active. Thus, SARP12T data is preserved

2) Write Operation: WL and WWL are active while writing. Writing a "0" at Q via

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BL to GND modifies the stored data. BLB is held at VDD for stability. Due of
BL's connection to GND, N7 and N9 exert a downward pull on nodes Q and S1.
Node

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Q activates P2 and deactivates N6, while S1 deactivates N2 and N3. BLB collects
QB and S0 simultaneously using N8 and N10. Node QB activation turns N5 ON
and P1 OFF. Node S0 activates N1 and N4. P1-P2 cross-coupling amplifies
Q-QB potential difference. N3-N4 connector increases S1-S0 voltage difference.
Thus, writing went well.

B) WRITE O OPERATION

Fig 5.4 Write “0” operation

FOR WRITE “0” OPERTION ,

WL=0,BL=1,BLB=1,S1=0,S0=1,QN=1,Q=0

WL=1,WWL=1,BL=0,BLB=1,Q=0,S1=0,QB=1,S0=1

WRITE 1 OPERATION FOR WRITE 1 OPERATION

W=1,BL=1,BLB=1,S1=1,S0=0,QB=0,Q=1

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Fig 5.5 Write ‘0’ Operation

3) Read Operation: The WL (wordline) is connected to VDD (supply voltage)

during read operation, while the WWL (write wordline) is off. As a result,

Transistors N7 and N8 become active, whilst N9 and N10 continue to be inactive. During
reading, the bitlines are given a precharge to VDD. BLB is produced by the N8, N2, and
N3 molecules. Figure 3 demonstrates that the voltage at node BL stays at VDD even
when nodes N1 and N4 are not receiving power.

C) READ OPERTAION

WL=1,WWL=0,BL=1(PRECHARGED),BLB=0(GND),Q=1,S1=1,QB=0,S0=0

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Fig 5.6 Read Operation

2) SEU @ Q: A Single Event Upset (SEU), as shown in Figure 3, will cause the logic
condition of storage node Q to shift from '1' to '0'. P2 and N6 become temporarily active
and then stop being active. N6's deactivation and N4's hold mode deactivation cause Node
S1's high impedance condition and logic value retention. As a consequence, both N2 and
N3 remain in the ON state. The logic level of QB remains unchanged even when P2 is
activated, owing to the larger size of NMOS transistors N2 and N3 compared to PMOS
transistor P2 (1). P1 remains in the ON state and N5 remains in the OFF state due to the
fact that QB maintains its current state. Furthermore, due to the activation of N3, the
value of S0 remains constant at '0', thereby preserving the deactivated state of N1.
Therefore, Qis able to retrieve its initial dataset.

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5.2 6T SRAM SCHEMATIC

Fig 5.7 6T SRAM Schematic

Fig 5.8 6T SRAM Simulation Results

5.3 OPERATION OF 6T SRAM

The 6T SRAM cell that stores one bit of information is shown in figure . The cell consists
of two CMOS inverters where the output of each is fed as input to other; this loop

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stabilized the inverters to their respective state The access transistors and the word and bit
lines WL and BL are used to write and read, to and from the cell. In the standby mode the
access transistors turn to off by making the word line low. The inverter will be
complementary in this state.

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The PMOS of the left inverter is turned on, the output potential is high and the PMOS of
the second inverter is switched to off. The gates of the transistor that connect the bit line
and the lines of the inverter are driven by the word line. If the word line is kept low the cell
is disconnected from the bit lines.

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CHAPTER -6

SIMULATION OF PROPOSED METHOD

6.1 Proposed method : write enable: SRAMCell

Fig 6.1 writes enable: Radiation-hardened SRAM Cell

A radiation-hardened SRAM cell, may solve the problem, according to this study. In this
statement, "we" stands for "writ-ability enhanced." Enable uses 12 access transistors to
improve the SRAM cell's writ ability. Our write enable design uses SRAM cell
architecture to match the Enable design's cell area. Monte-Carlo (MC) simulations
determine the SRAM cell design's practicality. Despite parametric process changes, write
enable performs well for 16 nm FD-SOI technology writ ability. Thus, we compare write
enable to Enable. This project uses scaled technology to create radiation-resistant SRAM
chips. Thus, we use simulations to compare these cells' soft-error robustness. SRAM cell
effectiveness was confirmed by comparing results.

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Fig 6.2 simulation of 10T SRAM Cell

Figure 5.4 shows the Enable cell with four interconnected storage nodes (A, B, C, and D).
This architecture prevents soft mistakes. 6T SRAM storage nodes connect PMOS and
NMOS transistor gates. Thus, SETs boost NMOS or PMOS pull-down or pull-up effects,
changing cell data. The interlocked Enable layout's storage node is the gate input for t wo
PMOS or NMOS transistors. SETs increase or decrease PMOS and NMOS transistor pull-
up and pull-down effects. Since complementary transistors are unaffected, soft-error
immunity is offered. Figure 2 shows a radiation particle decreasing node 'B''s potential.
These actions may reduce N1 and N4's downward thrust. Since P1 and P4 are
unaffected by noise, nodes "A" and "D" have little voltage changes. Thus, "B" voltage
returns to the power source after a predetermined time. This SET cannot retrieve primary
cell info.
POWER ANALYSIS
Power Results
VV1 from time 0 to 5e-07
Average power consumed -> 1.047340e-05 watts
Max power 6.458073e-05 at time 2.03979e-07
Min power 1.129300e-07 at time 2.04499e-07

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Table :1. Comparison between 12T with 10T

S.NO Technolog Methodology No: Dynamic Static Avg Delay
y Transistors Power Power Power
1 90nm SARP12T 12 4.463 8.20mw 9.60m 100.01
w n
2 16nm 10TSRAM 10 1.129300e- 6.4580 1.047340
07 73e-05 e-05 2.7136n

6.2 APPLICATION OF 10T SRAM IN DESIGNING OF 4X4 ARRAY

The major components required are
1. 2x4 decoder (INVERTER,AND GATE)
2. 4 input OR gate
3. 4X4 Array of SRAM (16 SRAMs)
1. 2X4 DECODER Schematic

Fig 6.3 Schematic of 2x4 Decoder.

The 2-to-4 line binary decoder depicted above consists of an array of four AND gates. The
2 binary inputs labelled A and B are decoded into one of 4 outputs, hence the description of
2-to-4 binary decoder. Each output represents one of the minterms of the 2 input variables

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Fig 6.4 2x4 decoder simulation results

6.3 OPERATION OF 2X4 DECODER

The 2-to-4 line binary decoder depicted above consists of an array of four AND gates. The
2 binary inputs labelled A and B are decoded into one of 4 outputs, hence the description
of 2-to-4 binary

decoder. Each output represents one of the minterms of the 2 input variables

Fig 6.5 Schematic of inverter

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6.3.1 4 Input OR gate

Fig 6.6 Schematic of 4 input OR gate

6.4 4X4 10T SRAM ARRAY

Fig 6.7 SCHMETAIC OF 4X4 ARRAY

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Fig 6.8 Simulation results of 4x4 array 10TSRAM

6.5 Operation of 4X4 ARRAY

This section describes the designing of 4x4 SRAM cell arrays of 4 rows and 4
columns. Each block of the array is of 10T SRAM cell. There are 4 rows and 4 columns
arranged to form a 4x4 SRAM cell array. To address these rows of cells the decoder is used
prior to the array arrangement. As the row consists of 4 cells it constitutes to form SRAM
Operation. The AND based 2:4 decoder is used to generate the address lines, the number of
transistors used for the decoder circuit is 28 (each AND gate uses 6 transistor and NOT
gate made up of 2 transistors). These address lines which form the outputs of decoder are
connected to each row of the array. The input and output data control consists of write and
ready circuitry. From the decoder the address is selected in the array and 4 bits of data
iswritten or read in parallel from DO to D3.
Input-output buffers are also required for each column as the decoder selects only
one row of the array, the other cells may generate glitch, this can be nullified by the
buffers. Also a 4-bit OR can be used to combine all the output of single SRAM cells of
each column to make a single output data.

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Static And Dynamic Power Consumption

1. Power Results
VV8 from time 0 to 1.5e-06
Average power consumed -> 1.531793e-04
watts Max power 5.165359e-04 at time
3.17484e-09 Min power 6.588095e-05 at time
9.05e-07
2. DELAY CALCULATION
Measurement result
summary tdealy = 1.0028u

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CHAPTER- 7

CONCLUSION AND FUTURE SCOPE

7.1 CONCLUSION

As the demand for portable devices are increasing technologies and methods are need
to be developed to reduce the shortcomings of the devices. Power leakage is one such
disadvantage of SRAM. In this project different SRAM parameters are obtained
through simulation. The simulation is carried out using LT Spice for a 16nm
technology node. The power dissipation, delay and the performance parameter Power-
Delay-Product (PDP) of 6T, 7T, 8T and 10T SRAM cells are compared to each other.
Domino Schmitt trigger is added as modification. The domino Schmitt trigger is able
to overcome the disadvantage of CMOS Schmitt trigger and along with its own
benefits it helps to decrease the power of the SRAM circuit. The power, delay and
power-delay product and noise margin of the conventional as well as modified circuit
is calculated. From the calculation it is seen that there is a great decrease in power
dissipation and PDP as well. SRAM being one of the most important part of memory
is constantly a subject of study. Reduction of any parameter related to SRAM will
open more opportunities and applications. Even though here power is reduced area is
still area which can be subject of study.

7.2 FUTURE SCOPE

On the basis of the studies and the investigations carried out in this project as an
extension ofthis work the following points are suggested. The 8T and 10T SRAM cell
can be implemented with 120 nm,90 nm and 32 nm CMOStechnology for the above low
power techniques.12T SRAM cell can be implemented with 120 nm,90 nm and32 nm
CMOS technology for the same logic. Temperature analysis can also be done for all the
circuits using hotspot tool. Static Noise Margin (SNM) is one of the parameters for
designing any SRAM circuit. So, this can be considered for8T,10T and 12T SRAM cell
with 4x4 SRAMs cell array. This designed circuit can be implemented with any type of
processor recently used inmark.

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REFERENCES

[1] J. L. Barth, C. S. Dyer, and E. G. Stassinopoulos, “Space, Atmospheric, and

TerrestrialRadiation Environments”, IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 466–
482, June 2003.
[2] Robert C. Baumann, “Radiation-induced soft errors in advanced semiconductor
technologies,”IEEE Trans. Devi. And Mate. Reli., vol. 5, no. 3, pp. 305-316, 2005.
[3] T. Granlund, B. Granbom, and N. Olsson, “Soft error rate increase for new
generations ofSRAMs,” IEEE Trans. Nucl. Sci., vol. 50, no. 6, pp.2065–2068, Dec.
2003
[4] M. A. Bajura, Y. Boulghassoul, R. Naseer, S. DasGupta, A. Witulski, and J.
Sondeen et al., “Models and algorithmic limits for an ECC-based approach to
hardening sub-100-nm SRAMs,”
IEEE Trans. Nucl. Sci., vol. 54, no. 4, pp. 935–945, Aug. 2007
[5] G. Gasiot, P. Roche, P. Flatresse, “Comparison of Multiple Cell Upset Response
of Bulk & SOI 130nm tech.”, IRPS 2008, pp 192-194
[6] L. Artola, M. Gaillardin, G. Hubert, M. Raine, P. Paillet, "Modeling Single
Event Transients inAdvanced Devices and ICs," IEEE Trans. Nucl. Sci., vol. 62, no. 4,
pp. 1528-1539, Aug. 2015
[7] S. Kiamehr, T. Osiecki, M. Tahoori, and S. Nassif, “Radiation-induced soft error
analysis of SRAMs in SOI FinFET technology: A device to circuit approach,” Proc.
DAC 51th, San Francisco,CA, USA, 2014, pp. 1–6.
[8] T. Calin, M. Nicolaidis, R. Velazco, “Upset Hardened Memory Design for
Submicron CMOS Technology,” IEEE Trans. Nucl. Sci. vol. 43, no. 6, pp. 2874-2878,
Dec. 1996.
[9] Shah M. Jahinuzzaman, David J. Rennie, and Manoj Sachdev, “A Soft Error
Tolerant 10T SRAM Bit-Cell With Differential Read Capability,” IEEE Trans. Nucl.
Sci. vol. 56, no. 6, pp. 3768–3773. Dec. 2009.
[10] Q. Wu et al., “Supply voltage dependence of heavy ion induced SEEs on 65 nm
CMOS bulk SRAMs,” IEEE Trans. Nucl. Sci., vol. 62, no. 4, pp. 1898–1904, Aug.
2015.
[11] Maxim S. Gorbunov, Pavel S. Dolotov, Andrey A. Antonov, Gennady I. Zebrev,
Vladimir V. Emeliyanov, Anna B. Boruzdina, Andrey G. Petrov, Anastasia V.
Ulanova, “Design of 65 nm CMOS SRAM for Space Applications: A Comparative
Study,” IEEE Trans. Nuclear Sci. vol. 61, no. 4, pp. 1575-1582, Aug. 2014.
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A PROJECT REPORT ON DESIGN AND IMPLEMENTATION OF CMOS LOW POWER HIGH
PERFORMANCE 10T SRAM 4*4 ARRAY

[12] R.W.Mann and B.H.Calhoun, “New category of ultra-thin notchless 6T

SRAM cell layout topologies for sub-22 nm,” Proc. ISQED 2011, pp. 1– 6, 2011.
[13] Neil HE Weste, David Money Harris, CMOS VLSI design: a circuits and
systems perspective, Addison-Wesley, fourth edition, 2011
[14] Le Dinh Trang Dang, Myounggon Kang, Jinsang Kim, Ik-Joon Chang,
“Studying the Variation Effects of Radiation Hardened Enable SRAM Bit-Cell,”
IEEE Trans.
Nuclear Science, vol. 63, no. 4, pp. 2399-2401, Aug. 2016
[15] Vibhu Sharma, Francky Catthoor, Wim Dehaene, “SRAM Bit Cell
Optimization,” in SRAM Design for Wireless Sensor Networks - Energy Efficient and
Variability Resilient Techniques,
Springer, 2013, pp. 9-30
[16] S. Mukhopadhyay, H. Mahmoodi, K. Roy, Modeling of failure probability and
statistical design of SRAM array for yield enhancement in nanoscaled CMOS, IEEE
Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 12, pp.
1859-1880, Dec. 2005
[17] E. Grossar, Read Stability and Write-Ability Analysis of SRAM Cells for
Nanometer Technologies, IEEE J.Solid-State Circuits, vol. 41, no. 11, pp. 2577-2588,
Nov. 2006
[18] Kenichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, and Tadahiro Kuroda, A
Bitline Leakage Compensation Scheme for Low-Voltage SRAMs, IEEE Journal of
Solid State Circ., vol. 36, no. 5, pp. 726-734, 2001.

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PERFORMANCE 10T SRAM 4*4 ARRAY

Appendix
* SPICE export by: S-Edit 2019.2.0

* Export time: Thu Mar 14 10:33:58 2024

* Design path: C:\Users\dell\Documents\TannerEDA\4X4ARRAY\lib.defs

* Library: 4X4ARRAY

* Cell: 44

* Testbench: Spice

* View: schematic

* Export as: top-level cell

* Export mode: hierarchical

* Exclude empty: yes

* Exclude .model: no

* Exclude .hdl: no

* Exclude .end: no

* Expand paths: yes

* Wrap lines: no

* Exclude simulator commands: no

* Exclude global pins: no

* Exclude instance locations: no

* Control property name(s): SPICE

********* Simulation Settings - General Section *********

.include "G:/MENTOR/45nmnew/16nm/CMOS_16nm.md"

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*************** Subcircuits *****************

.subckt ANDAGATE A ANDOUT B Gnd Vdd

MM3 ANDOUT N_1 Gnd Gnd NMOS W=32n L=16n AS=28.8f PS=1.864u
AD=28.8f PD=1.864u $ $x=6600 $y=3600 $w=400 $h=600

MM5 N_1 A N_2 Gnd NMOS W=32n L=16n AS=28.8f PS=1.864u AD=28.8f
PD=1.864u $ $x=4600 $y=4200 $w=400 $h=600

MM6 N_2 B Gnd Gnd NMOS W=32n L=16n AS=28.8f PS=1.864u AD=28.8f
PD=1.864u $ $x=4600 $y=3100 $w=400 $h=600

MM1 N_1 A Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=3500 $y=5300 $w=400 $h=600

MM2 N_1 B Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=5500 $y=5300 $w=400 $h=600

MM4 ANDOUT N_1 Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u
AD=57.6f PD=1.928u $ $x=6600 $y=4600 $w=400 $h=600

.ends

.subckt 10TSRAMSYM bl q wl Gnd Vdd

MM1 N_1 q Gnd Gnd NMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=3600 $y=3900 $w=400 $h=600 $m

MM6 bl wl q Gnd NMOS W=32n L=16n AS=28.8f PS=1.864u AD=28.8f

PD=1.864u $ $x=2300 $y=4600 $w=600 $h=400 $r=90 $m

MM7 N_3 wl N_4 Gnd NMOS W=32n L=16n AS=28.8f PS=1.864u AD=28.8f
PD=1.864u $ $x=6900 $y=4700 $w=600 $h=400 $r=90 $m

MM8 N_2 N_3 Gnd Gnd NMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=6000 $y=3900 $w=400 $h=600
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MM9 q N_3 Gnd Gnd NMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=4300 $y=3100 $w=400 $h=600 $m

MM10 N_3 q Gnd Gnd NMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=5200 $y=3100 $w=400 $h=600

MM12 N_4 bl Gnd Gnd NMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=8400 $y=4100 $w=400 $h=600 $m

MM2 N_2 N_1 Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=6000 $y=5600 $w=400 $h=600

MM3 N_1 N_2 Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=3600 $y=5600 $w=400 $h=600 $m

MM4 q N_1 Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=3900 $y=4800 $w=400 $h=600

MM5 N_3 N_2 Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=5600 $y=4800 $w=400 $h=600 $m

MM11 N_4 bl Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=8400 $y=5000 $w=400 $h=600 $m

.ends

.subckt orgatesym a b c d orgate Gnd Vdd

MM1 N_4 c Gnd Gnd NMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=5900 $y=2100 $w=400 $h=600

MM4 N_4 d Gnd Gnd NMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=7200 $y=2100 $w=400 $h=600

MM6 orgate N_4 Gnd Gnd NMOS W=64n L=16n AS=57.6f PS=1.928u
AD=57.6f PD=1.928u $ $x=8800 $y=2500 $w=400 $h=600

MM9 N_4 b Gnd Gnd NMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
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PD=1.928u $ $x=4500 $y=2100 $w=400 $h=600

MM10 N_4 a Gnd Gnd NMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=3500 $y=2100 $w=400 $h=600

MM2 N_4 d N_1 Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=6600 $y=3100 $w=400 $h=600

MM3 N_1 c N_2 Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=6600 $y=4100 $w=400 $h=600

MM5 orgate N_4 Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u
AD=57.6f PD=1.928u $ $x=8800 $y=3500 $w=400 $h=600

MM7 N_2 b N_3 Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=6600 $y=5100 $w=400 $h=600

MM8 N_3 a Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=6600 $y=6200 $w=400 $h=600

.ends

.subckt INV A OUT Gnd Vdd

MM3 OUT A Gnd Gnd NMOS W=32n L=16n AS=28.8f PS=1.864u AD=28.8f
PD=1.864u $ $x=2800 $y=4100 $w=400 $h=600

MM4 OUT A Vdd Vdd PMOS W=64n L=16n AS=57.6f PS=1.928u AD=57.6f
PD=1.928u $ $x=2800 $y=5100 $w=400 $h=600

.ends

***** Top Level *****

X10TSRAMSYM_1 b0 a0 D0 Gnd Vdd 10TSRAMSYM $ $x=2800 $y=5900

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$w=1800 $h=1400

X10TSRAMSYM_2 x0 b0 D0 Gnd Vdd 10TSRAMSYM $ $x=5300 $y=6000

$w=1800 $h=1400

X10TSRAMSYM_3 y0 c0 D0 Gnd Vdd 10TSRAMSYM $ $x=7800 $y=6000

$w=1800 $h=1400

X10TSRAMSYM_4 z0 d0 D0 Gnd Vdd 10TSRAMSYM $ $x=11300 $y=6000

$w=1800 $h=1400

X10TSRAMSYM_5 b0 a1 D1 Gnd Vdd 10TSRAMSYM $ $x=2600 $y=3700

$w=1800 $h=1400

X10TSRAMSYM_6 x0 b1 D1 Gnd Vdd 10TSRAMSYM $ $x=5100 $y=3800

$w=1800 $h=1400

X10TSRAMSYM_7 y0 c1 D1 Gnd Vdd 10TSRAMSYM $ $x=7600 $y=3800

$w=1800 $h=1400

X10TSRAMSYM_8 z0 d1 D1 Gnd Vdd 10TSRAMSYM $ $x=11100 $y=3800

$w=1800 $h=1400

X10TSRAMSYM_9 b0 a2 D2 Gnd Vdd 10TSRAMSYM $ $x=2400 $y=1400

$w=1800 $h=1400

X10TSRAMSYM_10 x0 b2 D2 Gnd Vdd 10TSRAMSYM $ $x=4900 $y=1500

$w=1800 $h=1400

X10TSRAMSYM_11 y0 c2 D2 Gnd Vdd 10TSRAMSYM $ $x=7400 $y=1500

$w=1800 $h=1400

X10TSRAMSYM_12 z0 d2 D2 Gnd Vdd 10TSRAMSYM $ $x=10900 $y=1500

$w=1800 $h=1400

X10TSRAMSYM_13 b0 a3 D3 Gnd Vdd 10TSRAMSYM $ $x=2200 $y=-800

$w=1800 $h=1400

X10TSRAMSYM_14 x0 b3 D3 Gnd Vdd 10TSRAMSYM $ $x=4700 $y=-700

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PERFORMANCE 10T SRAM 4*4 ARRAY

$w=1800 $h=1400

X10TSRAMSYM_15 y0 c3 D3 Gnd Vdd 10TSRAMSYM $ $x=7200 $y=-700

$w=1800 $h=1400

X10TSRAMSYM_16 z0 d3 D3 Gnd Vdd 10TSRAMSYM $ $x=10700 $y=-700

$w=1800 $h=1400

XANDAGATE_1 BBAR D0 ABAR Gnd Vdd ANDAGATE $ $x=-4100

$y=6200 $w=1800 $h=1400 $r=180 $m

XANDAGATE_2 B D1 ABAR Gnd Vdd ANDAGATE $ $x=-4200 $y=4200

$w=1800 $h=1400 $r=180 $m

XANDAGATE_3 BBAR D2 A Gnd Vdd ANDAGATE $ $x=-4100 $y=2200

$w=1800 $h=1400 $r=180 $m

XANDAGATE_4 B D3 A Gnd Vdd ANDAGATE $ $x=-4100 $y=200 $w=1800

$h=1400 $r=180 $m

XINV_1 A ABAR Gnd Vdd INV $ $x=-7100 $y=4100 $w=1800 $h=1200

$r=180 $m

XINV_2 B BBAR Gnd Vdd INV $ $x=-7100 $y=2300 $w=1800 $h=1200

$r=180 $m

Xorgatesym_1 a0 a1 a2 a3 out1 Gnd Vdd orgatesym $ $x=2200 $y=-3200

$w=1800 $h=1800

Xorgatesym_2 b0 b1 b2 b3 out2 Gnd Vdd orgatesym $ $x=5800 $y=-3000

$w=1800 $h=1800

Xorgatesym_3 c0 c1 c2 c3 out3 Gnd Vdd orgatesym $ $x=9500 $y=-2800

$w=1800 $h=1800

Xorgatesym_4 d0 d1 d2 d3 out4 Gnd Vdd orgatesym $ $x=13000 $y=-2700

$w=1800 $h=1800

VV8 Vdd Gnd DC 800m $ $x=-6900 $y=300 $w=400 $h=600

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VV1 B Gnd PULSE(0 800m 0 5n 5n 95n 200n) $ $x=-7800 $y=300 $w=400

$h=600

VV2 b0 Gnd PULSE(0 800m 0 5n 5n 45n 100n) $ $x=1700 $y=8600 $w=400

$h=600

VV3 A Gnd PULSE(0 800m 0 5n 5n 45n 100n) $ $x=-8500 $y=300 $w=400

$h=600

VV4 x0 Gnd PULSE(0 800m 100n 5n 5n 95n 200n) $ $x=4500 $y=8400

$w=400 $h=600

VV6 y0 Gnd PULSE(0 800m 400n 5n 5n 95n 200n) $ $x=7100 $y=8400

$w=400 $h=600

VV7 z0 Gnd PULSE(0 800m 1u 5n 5n 145n 300n) $ $x=10400 $y=8500

$w=400 $h=600

.PLOT V(A) $ $x=-8650 $y=-150 $w=300 $h=1500 $r=90

.PLOT V(a0) $ $x=3550 $y=5050 $w=300 $h=1500 $r=90

.PLOT V(B) $ $x=-7950 $y=-150 $w=300 $h=1500 $r=90

.PLOT V(D0) $ $x=-3350 $y=5550 $w=300 $h=1500 $r=90

.PLOT V(D1) $ $x=-3450 $y=3550 $w=300 $h=1500 $r=90

.PLOT V(D2) $ $x=-3350 $y=1550 $w=300 $h=1500 $r=90

.PLOT V(D3) $ $x=-3350 $y=-450 $w=300 $h=1500 $r=90

********* Simulation Settings - Analysis Section *********

.tran 10n 1500n

********* Simulation Settings - Additional SPICE Commands *********

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PERFORMANCE 10T SRAM 4*4 ARRAY

.end

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