LAB REPORT# 03

SUBJECT: DIGITAL LOGIC DESIGN

INSTRUCTOR: GHUFRAN SHAFIQ

SUBMITTED BY: MOHAMMAD IBRAHIM

REGISTRATION: FA23-EEE-003

DATE: 14-03-2024

COMSATS UNIVERSITY ISLAMABAD (CUI)

 INTRODUCTION TO VERILOG & SIMULATION USING
XILINX ISE:
Theory:
Hardware Descriptive Language (HDL):
Hardware description language (HDL) is a specialized computer language used
to describe the structure and behavior of electronic circuits, and most
commonly, digital logic circuits. We can describe digital logic circuit structure
in ways, which are as.

Verilog HDL:
Verilog HDL allows a hardware designer to describe designs at a high level of
abstraction such as at the architectural or behavioral level as well as the lower
implementation levels such as gate and switch levels. Its syntax is like C
language and is easier to learn.

Data Flow Level:

Designs using the Register-Transfer Level specify the characteristics of a
circuit by operations and the transfer of data between the registers. An explicit
clock is used. RTL design contains exact timing bounds: operations are
scheduled at certain times. Modern RTL code definition is "Any code that is
synthesizable is called RTL code".

Gate Level:
Within the logic level, the characteristics of a system are described by logical
links and their timing properties. All signals are discrete signals. They can only
have definite logical values (`0', `1', `X', `Z`). The usable operations are
predefined logic primitives (AND, OR, NOT, etc.). Using gate-level modeling
might not be a good idea for any level of logic design.
We focus on applying gate-level abstraction all the time.
Switch level:
This is the lowest level of abstraction provided by Verilog. A module can be
implemented in terms of switches.
Behavioral Level:
This level describes a system by concurrent algorithms (Behavioral). Each
algorithm itself is sequential, which means it consists of a set of instructions
that are executed one after the other. Functions, Tasks, and Always blocks are
the main elements. There is no regard for the structural realization of the
design.
Commonly used operators:
~ Complement, & AND, | OR, ~& NAND, ~| NOR etc.

PORTS:
Ports refer to the interfaces through which signals enter or exit a digital circuit.
They provide a connection point for external devices or other parts of the circuit
to communicate with the designed system.

SIGNALS:
Signals are the electrical or logical representations of data that flow through the
digital circuit. They carry information such as control signals, data inputs, and
outputs between different components within the circuit or between the circuit
and external devices. Signals can be either digital (binary) or analog, depending
on the application.
 PRE-LAB:
For AND Gate:
PROCEDURE:
• Create a project in Xilinx.
• Specify inputs and outputs in the main module.
• Implement the Boolean expression using gates.
• Give final output as output function variable.
• Create a test file.
• Test waveform.
• The truth table of AND Gate is the same as the waveform.

A B AND

0 0 0

0 1 0

1 0 0

1 1 1

Verilog Code using Xilinx ISE:

GATE-LEVEL:
DATA FLOW:

Test Bench

Result:
 IN LAB:
For NOT Gate:

PROCEDURE:
• Create a project in Xilinx.
• Specify inputs and outputs in the main module.
• Implement the Boolean expression using gates.
• Give final output as output function variable.
• Create a test file.
• Test waveform.
• The truth table of NOT Gate is the same as the waveform.

INPUT OUTPUT

A B

1 0

0 1

Verilog Code using Xilinx ISE:

Test Bench:

Result:
 For OR Gate:
PROCEDURE:
• Create a project in Xilinx.
• Specify inputs and outputs in the main module.
• Implement the Boolean expression using gates.
• Give final output as output function variable.
• Create a test file.
• Test waveform.
• The truth table of OR Gate is the same as the waveform.

A B OR

0 0 0

0 1 1

1 0 1

1 1 1

Verilog Code using Xilinx ISE:

Test Bench:

Result:
 For NAND Gate:

PROCEDURE:
• Create a project in Xilinx.
• Specify inputs and outputs in the main module.
• Implement the Boolean expression using gates.
• Give final output as output function variable.
• Create a test file.
• Test waveform.
• The truth table of NAND Gate is the same as the waveform.

A B NAND

0 0 1

0 1 1

1 0 1

1 1 0

Verilog Code using Xilinx ISE:

Test Bench:

Result:
 For XOR Gate:

PROCEDURE:
• Create a project in Xilinx.
• Specify inputs and outputs in the main module.
• Implement the Boolean expression using gates.
• Give final output as output function variable.
• Create a test file.
• Test waveform.
• The truth table of XOR Gate is the same as the waveform.

A B XOR

0 0 0

0 1 1

1 0 1

1 1 0

Verilog Code using Xilinx ISE:

Test Bench:

Result:
 For XNOR Gate:

PROCEDURE:
• Create a project in Xilinx.
• Specify inputs and outputs in the main module.
• Implement the Boolean expression using gates.
• Give final output as output function variable.
• Create a test file.
• Test waveform.
• The truth table of XNOR Gate is the same as the waveform.

A B XNOR

0 0 1

0 1 0

1 0 0

1 1 1

Verilog Code using Xilinx ISE:

Test Bench:

Result:
 Post Lab Task:
Module for F x + x’y + yz’

PROCEDURE:
• Create a project in Xilinx.
• Specify inputs and outputs in the main module.
• Implement the Boolean expression using gates.
• Give final output as output function variable.
• Create a test file.
• Test waveform.
Verilog Code using Xilinx ISE:

DATA FLOW MODEL:

GATE-LEVEL MODEL:
TEST BENCH:

Result:
Truth Table:

X Y Z X’ Z’ X’Y YZ’ X + X’Y + YZ’

0 0 0 1 1 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 1 1 1 1
0 1 1 1 0 1 0 1
1 0 0 0 1 0 0 1
1 0 1 0 0 0 0 1
1 1 0 0 1 0 1 1
1 1 1 0 0 1 0 1

CIRCUIT DIAGRAM:
 Critical Analysis:
In this Lab, I have learned about Verilog (HDL) in Xilinx ISE software.
Verilog is used for modeling digital systems, most commonly used in
the designs and verification of digital circuits.I learned how
to use Xilinx ISE.