Department of Electrical Engineering

Faculty Member:____________________ Dated: ________________

Semester:__________________________ Section: ________________

EE122 Computer Architecture and Logic Design

Lab 6: Minimization of Boolean Functions

PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7

Name Reg. No Viva / Quiz / Analysis Modern Ethics and Individual Total
Lab of data in Tool Usage Safety and Team marks
Performance Lab Report Work obtained

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

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 Lab 6: Minimization of Boolean Functions

This Lab has been divided into two parts.

1. The first part is the hardware implementation of a Boolean function given to you. You will have
to first minimize the Boolean functions to minimum the number of literals.
2. In the next part, you will simulate the same circuits using Verilog.

Objectives:

 Understand Minimization of Boolean Functions

 Simulate Basic Circuits using Verilog
 Hardware Implementation of Basic Logic Circuits

Lab Instructions:

✔ This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-lab viva session.

✔ The lab report will be uploaded on LMS before scheduled lab date. Complete the Pre-lab task before
coming to the lab and show it to teacher/lab engineer for subsequent evaluation. Alternately each
group to upload completed lab report on LMS for grading.
✔ The students failing to complete Pre-lab will not be allowed to attend lab session.

✔ The students will start lab task and demonstrate design steps separately for step-wise evaluation.

✔ Remember that a neat logic diagram with pins numbered and nicely patched circuit will simplify
trouble-shooting/fault diagnostic process.
✔ After completion of lab, the students are expected to unwire the circuit and deposit back components
to lab staff.
✔ The students will complete lab task within the prescribed time and submit complete report on LMS.

✔ There will be a viva/quiz session after demonstration for which students will be graded individually.

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Pre-Lab Tasks:

1. Given the following two Boolean functions, simplify the expressions using algebraic
manipulation. Show all the steps in the simplification.

F (A, B, C) = (2, 3, 7)

G (A, B, C) = (4, 5, 7)

Simplification:

2. Mention the number of literals and gates needed for implementing the above functions in
hardware.

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 For F (A, B, C) = (2, 3, 7) 3 Literals and 3 Gates required.

For G (A, B, C) = (4, 5, 7) 3 Literals and 3 Gates required.

Lab Tasks:

Task 1 _______________________________________________________
Provide the truth tables of both of the previous given Boolean expressions.

Truth Table of Equation 1:

Truth Table of Equation 2:

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Task 2 _______________________________________________________
Draw the logic diagrams on Proteus for both of the Boolean expressions. You must show both the
original version (sum-of-minterms) and the simplified version of the circuits. Provide all relevant
screenshots.

Proteus for Function 1:

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Proteus for Function 2:

Task 3 _______________________________________________________
Implement the simplified Boolean functions on hardware. Mention what and how many gates you
would be using? The shown gates are available to you. Provide pictures of your work in hardware.

Hardware for Function 1:

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Hardware for Task 2:

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Task 4 ________________________________________________________

Write the Verilog codes for both the original and minimized functions at gate-level and perform the
waveform simulations. Attach all of the relevant screenshots below.

F (A, B, C) = (2, 3, 7)

ORIGINAL FUNCTION CODE :

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TEST BENCH :

WAVE FORM SS :

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 G (A, B, C) = (4, 5, 7)

SIMPLIFIED FUNCTION CODE :

TEST BENCH :

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WAVEFORM SS :

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Task 5 ________________________________________________________

Consider the given Boolean expression:

G = BAC + E + FCA + ADF + BDA

● Show your simplification of the expression

SIMPLIFICATION :

= BA . (C+D)+E+FA . (C+D)

= (C+D) . (BA+FA)+E

= (C+D) . (A . (B+F))+E

● Show the truth table

● Show both the original and simplified circuits in Proteus
Proteus Simplified:

Proteus Original:

● Perform the simplified circuit in hardware and provide pictures of your work.

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Simplified on Hardware:

● Simulate the simplified expression in Verilog and provide screenshots of code and waveform

SIMPLIFIED FUNCTION :

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TEST BENCH :

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WAVEFORM SS :

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