Experinment 10
Experinment 10
10.1 OBJECTIVES
Design a D to A Convertor with a resolution of 0.3125V using R-2R network. Assume the
logic 1 to be 5V and logic 0 to be 0V.
3 Resistors 2K Ω 5
1K Ω 3
6 Multimeter 1
10.2.2 THEORY
Since the input to the D/A converter has a finite number of digital
combinations, the resulting analog output also has a limited number of possible
values (unlike pure analog signals, which may have an infinite number of values).
The greater the number of possible values, the closer the analog output will be to the
ideal value. The number of possible levels is determined by the number of lines or
bits in the digital number. More specifically, the number of states is computed as 2 N
where N is the number of bits in the digital number. For example, an 8-bit D/A
converter could be expected to produce 2 or 256, discrete output steps. If the full-
8
scale range of the converter is 0 to 10 volts, then each step will be 10/256, or about
39 millivolts. If finer resolution is required, we need more bits in the digital number.
Thus, a converter with 10-bit resolution would provide 2 or 1024, steps with each
10
One of the most popular methods for D/A conversion is shown in Fig 12.3. It
is called an R-2R ladder D/A converter, since the input network resembles the rungs
on a ladder and the resistors in the input network are either equal (R) or have a 2:1
ratio (2R). One advantage of the R-2R converter over the weighted converter is the
resistors have a 2:1 ratio regardless of the number of bits being converted. This
makes matching resistors much easier and even makes the use of integrated resistors
practical.
An easy way to analyze the operation of the circuit is to Thevenize the input
circuit for one or more digital input numbers. Once the input circuit has been
simplified with the Thevenin’s theorem, it is left with a simple inverting amplifier
circuit whose input voltage is the Thevenin equivalent voltage and whose gain is
determined by the ratio of feedback resistance to Thevenin
Design Constraints
Resistance should be use ±1 to ±5 tolerance
4. Find the output voltage Vo for different combinations of digital binary inputs
from 000 to 111.
5. Compare the calculated values with observed values and plot DAC characteristics.
Observations
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
10.5 POST LAB QUESTIONS
1. Determine the output voltage of the DAC in Fig-10.3(a). The sequence of four-
digit binary codes represented by the waveforms in Fig-10.3(b) are applied to the
inputs. A high level is a binary l, and low level is a binary 0. The least significant
binary digit is D0.
Fig-10.3
2. The R-2R ladder DAC shown in Fig-10.4 below consists of 10KΩ & 20KΩ resistors, VREF
= 2V and R1 = 10KΩ. Determine the values required for RF such that VFS = 10V.
3. What is the value of resistor required in weighted resistor DAC if LSB resistor
value is 12KΩ for 4-bit DAC?
4. A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts. What
is the analog output for the input code 0101?
5. What is the major advantage of the R/2R ladder digital-to-analog (DAC), as
compared to a binary-weighted digital-to-analog DAC converter?
Result: