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DC Endsem

This document contains 8 questions related to digital circuits. The questions cover topics such as full adders, half adders, multiplexers, demultiplexers, flip-flops, counters, shift registers, finite state machines, programmable logic arrays, and static and dynamic memories. The document provides detailed instructions to candidates regarding answering questions and includes the maximum marks for each question.

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Aniket baroorkar
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0% found this document useful (0 votes)
34 views2 pages

DC Endsem

This document contains 8 questions related to digital circuits. The questions cover topics such as full adders, half adders, multiplexers, demultiplexers, flip-flops, counters, shift registers, finite state machines, programmable logic arrays, and static and dynamic memories. The document provides detailed instructions to candidates regarding answering questions and includes the maximum marks for each question.

Uploaded by

Aniket baroorkar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Total No. of Questions : 8] SEAT No.

8
23
PA-1191 [Total No. of Pages : 2

ic-
[5925]-213

tat
S.E. (Electronics/E & T.C/Electronics & Computer)

1s
3:3
DIGITAL CIRCUITS

02 91
3:3
(2019 Pattern) (Semester-III) (204182)

0
31
Time : 2½ Hours] 7/0 13 [Max. Marks : 70
0
Instructions to the candidates:
2/2
.23 GP

1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.


2) Neat diagrams must be drawn wherever necessary.
E
80

8
3) Figures to the right indicate full marks.
C

23
ic-
16

Q1) a) Draw the logic diagram of full-adder and its truth table. [7]

tat
8.2

1s
b) Implement a full-adder using Demultiplexer. [5]
.24

3:3
91
c) Implement the given logic function using a 4:1 multiplexer [5]
49

3:3
30

f ( A, B, C ) =  m(0, 2, 4,6)
31
01
02

OR
2/2
GP

Q2) a) Explain the working of a half-adder? Draw its logic diagram. [7]
7/0
CE
80

b) Implement the full subtractor using a 1:8 demultiplexer. [5]

8
23
.23

c) Implement the following function using multiplexer [5]


ic-
16

tat
f ( A, B, C ) =  m(0, 2, 4,6)
8.2

1s
.24

3:3
91
49

3:3

Q3) a) Design a sequence generator using T FFs. [8]


30
31

b) Explain the types of shift register. [5]


01
02

c) Explain with diagram the working of D type Flip-flop. Give its truth table.
2/2
GP

[5]
7/0

OR
CE
80

Q4) a) Design a 3-Bit synchronous counter using JK FF. [8]


.23

b) With the neat diagram, explain the working operation of 4-bit SISO. [5]
16
8.2

c) Explain S-R flip-flop using NOR gates. [5]


.24

P.T.O.
49
8
Q5) a) Design the clocked sequential circuit for the state diagram using JK flip

23
flop. [9]

ic-
tat
1s
3:3
02 91
3:3
0
31
7/0 13
0
2/2
.23 GP
E
80

8
b) Draw ASM chart for 2 bit binary counter having one enable line E such
C

23
that: E=1, [8]

ic-
16

tat
c) Count Enable and E=0, Count Disable.
8.2

1s
OR
.24

3:3
91
Q6) a) Design a sequence detector to detect a sequence 1101 using D FF [9]
49

3:3
30

(Use Moore machine).


31
01

b) Explain in short: [8]


02

i) State Assignment
2/2
GP

ii) ASM chart


7/0
CE
80

8
Q7) a) Explain the classification based on their physical characteristics. [8]

23
.23

b) Explain the concept of PLA with the help of a block diagram. [10]
ic-
16

tat
OR
8.2

1s

Q8) a) Explain the meaning of static and dynamic memories. State their
.24

3:3

applications. [8]
91
49

b) Describe with neat diagram AND-OR structure of PLA and PAL. [10]
3:3
30
31
01
02


2/2
GP
7/0
CE
80
.23
16
8.2
.24

[5925]-213
49

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