Digital Electronics

Faculty of Engineering

USEK

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 Outline

Ø Logic Families (Chapter 5 Book)

q Characteristic Parameters

q TTL

q ECL

q CMOS

q Integrated Circuit Interfacing

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 Characteristic Parameters
§ Current and Voltage Parameters

𝑉!" (𝑚𝑖𝑛): High-Level Input Voltage. 𝑉!$ (𝑚𝑎𝑥): Low-Level Input Voltage.

𝑉#" (𝑚𝑖𝑛): High-Level Output Voltage. 𝑉#$ (𝑚𝑎𝑥): Low-Level Output Voltage.

𝐼!" : High-Level Input Current. 𝐼!$ : Low-Level Input Current.

𝐼#" : High-Level Output Current. 𝐼#$ : Low-Level Output Current.

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 Characteristic Parameters
§ Fan-Out

In general, a logic-circuit output is required to drive several logic inputs. Sometimes all ICs in the digital system

are from the same logic family, but many systems have a mix of various logic families.

The fan-out (also called loading factor) is defined as the maximum number of logic inputs that an output can

drive reliably. For example, a logic gate that is specified to have a fan-out of 10 can drive 10 logic inputs. If this

number is exceeded, the output logic-level voltages cannot be guaranteed. Obviously, fan-out depends on the

nature of the input devices that are connected to an output.

Unless a different logic family is specified as the load device, fan-out is assumed to refer to load devices of the

same family as the driving output.

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 Characteristic Parameters
§ Propagation Delays:
The propagation delay 𝑡% is the time delay between the occurrence of change in the logical level at the input and
before it is reflected at the output. It is the time delay between the specified voltage points on the input and
output waveforms.
§ 𝑡%$" : Delay time in going from logical 0 to logical 1 state (LOW to HIGH).
§ 𝑡%"$ : Delay time in going from logical 1 to logical 0 state (HIGH to LOW).

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 Characteristic Parameters
§ Power Requirements:
Every IC requires a certain amount of electrical power to operate. This power is supplied by one or more power-
supply voltages connected to the power pin(s) on the chip labeled: 𝑉&& for TTL or 𝑉'' for MOS devices.
The amount of power that an IC requires is determined by the current 𝐼&& (or 𝐼'' ) that it draws from the 𝑉&& (or
𝑉'' ). So the power dissipated is the product 𝐼&& ×𝑉&& (or 𝐼'' ×𝑉'' ).
For many ICs, the current drawn from the supply varies depending on the logic states of the circuits on the chip.
(HIGH or LOW).

𝐼&&" + 𝐼&&$
𝐼&& 𝑎𝑣𝑔 =
2

𝑃' 𝑎𝑣𝑔 = 𝐼(( 𝑎𝑣𝑔 ×𝑉&&

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 Characteristic Parameters
§ Noise Immunity:
Stray electric and magnetic fields can induce voltages on the connecting wires between logic circuits. These
unwanted, spurious signals are called noise and can sometimes cause the voltage at the input to a logic circuit to
drop below 𝑉!" 𝑚𝑖𝑛 or rise above 𝑉!$ 𝑚𝑎𝑥 which could produce unpredictable operation. The noise immunity
of a logic circuit refers to the circuit’s ability to tolerate noise without causing spurious changes in the output
voltage. A quantitative measure of noise immunity is called noise margin and is illustrated below:

The high-state noise margin 𝑉)" is defined as:

𝑉)" = 𝑉#" 𝑚𝑖𝑛 − 𝑉!" (𝑚𝑖𝑛)
The low-state noise margin 𝑉)$ is defined as:
𝑉)$ = 𝑉!$ 𝑚𝑎𝑥 − 𝑉#$ (𝑚𝑎𝑥)

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 Characteristic Parameters
§ Invalid Voltage Levels:
For proper operation, the input voltage levels to a logic circuit must be kept outside the indeterminate range. that
is, they must be either lower than 𝑉!$ 𝑚𝑎𝑥 or higher than 𝑉!" 𝑚𝑖𝑛 . For the standard TTL specifications, this
means that the input voltage must be less than 0.8 V or greater than 2 V. An input voltage between 0.8 and 2.0 V
is considered an invalid voltage that will produce an unpredictable output response, and so must be avoided.
In normal operation, a logic input voltage will not fall into the invalid region because it comes from a logic
output that is within the stated specifications. However, when this logic output is malfunctioning or is being
overloaded (i.e., its fan-out is being exceeded), then its voltage may be in the invalid region. Invalid voltage
levels in a digital circuit can also be caused by power-supply voltages that are outside the acceptable range. It is
important to know the valid voltage ranges for the logic family being used so that invalid conditions can be
recognized when testing or troubleshooting.

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 Characteristic Parameters
§ Current-Sourcing Action:
Logic families can be described according to how current flows between the output of one logic circuit and the
input of another.
Figure below illustrates current-sourcing action. When the output of gate 1 is in the HIGH state, it supplies a
current 𝐼!" to the input of gate 2, which acts essentially as a resistance to ground. Thus, the output of gate 1 is
acting as a source of current for the gate 2 input. We can think of it as being like a faucet that acts as a source of
water.

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 Characteristic Parameters
§ Current-Sinking Action:
Current-sinking action is illustrated below. Here the input circuitry of gate 2 is represented as a resistance tied to
+𝑉(( , the positive terminal of a power supply.
When the gate 1 output goes to its LOW state, current will flow in the direction shown from the input circuit of
gate 2 back through the output resistance of gate 1 to ground. In other words, in the LOW state, the circuit output
that drives the input of gate 2 must be able to sink a current, 𝐼!$ , coming from that input. We can think of this as
acting like a sink into which water is flowing.

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 Characteristic Parameters
§ IC Packages:

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 Characteristic Parameters
§ Example 1:

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 Characteristic Parameters
§ Example 2:
The input/output voltage specifications for the standard TTL family are listed in Table below. Use these values to
determine the following.

a) The maximum-amplitude noise spike that can be tolerated when a HIGH output is driving an input.
b) The maximum-amplitude noise spike that can be tolerated when a LOW output is driving an input.

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 Outline

Ø Integrated-Circuit Logic Families (Chapter 5 Book)

q Digital IC Terminology

q TTL Logic Family

q ECL Logic Family

q CMOS Logic Family

q Integrated Circuit Interfacing

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 TTL Logic Family
§ TTL Circuit Operation
TTL stands for Transistor Transistor
Logic.
This figure shows a NAND logic
function in TTL technology.
We use multi-emitter transistors,
which behave like diodes.
The output side of the transistors are
in a totem-pole arrangement.

Basic TTL NAND gate Diode equivalent for 𝑸𝟏

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 TTL Logic Family

Transistors Q3 and Q4 constitute what is known as a totem-pole output arrangement. In such an

arrangement, either Q3 or Q4 conducts at a time depending upon the logic status of the inputs. The
totem-pole arrangement at the output has certain distinct advantages.
The major advantage of using a totem-pole connection is that it offers low-output impedance in both the
HIGH and LOW output states. In the HIGH state, Q3 acts as an emitter follower and has an output
impedance of about 70 . In the LOW state, Q4 is saturated, and the output impedance is approximately 10.
Because of the low output impedance, any stray capacitance at the output can be charged or discharged
very rapidly through this low impedance, thus allowing quick transitions at the output from one state to
the other. Another advantage is that, when the output is in the logic LOW state, transistor Q4 would need
to conduct a large current if its collector were tied to VCC through R3 only. A nonconducting Q3
overcomes this problem.
A disadvantage of the totem-pole output configuration results from the switch-off action of Q4 being
slower than the switch-on action of Q3. Because of this, there will be a small fraction of time, of the order
of a few nanoseconds, when both the transistors are conducting, thus drawing heavy current from the
supply.

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 TTL Logic Family
§ TTL NAND gate in its Low output states

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 TTL Logic Family
§ TTL NAND gate in its High output states

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 TTL Logic Family
§ TTL NOR gate

§ On the input side, the NOR circuit does not use a multi-emitter transistor. Each input is applied to the emitter of a
separate transistor.
§ On the output side, the NOR circuit uses the same totem-pole arrangement as the NAND circuit.
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 TTL Logic Family
§ TTL SERIES CHARACTERISTICS

Ø Standard TTL, 74 Series: These devices are still readily available, but in most cases they are no longer a
reasonable choice for new designs because other devices are now available that perform much better at a lower
cost.
Ø Schottky TTL, 74S Series: These devices causes a storage-time delay when the transistors switch
from ON to OFF, and it limits the circuit’s switching speed.

Ø Low-Power Schottky TTL, 74LS Series (LS-TTL): TTL circuit combining the advantage of the 74Lxx
and 74Sxx circuits, i.e. fast and low current consumption.

Ø Advanced Schottky TTL, 74AS Series (AS-TTL): Very fast logic circuits, can working at high clock
frequencies.

Ø Advanced Low-Power Schottky TTL, 74ALS Series: These circuits combine the advantages of the
74ASxx and 74Lxx: low consumption and very fast. The most used.

Ø Fast TTL, 74F Series: Logic circuit with very low propagation time, therefore increasing speed..
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 TTL Logic Family
§ Typical TTL series characteristics

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 TTL Logic Family
§ Currents when a TTL output is driving several inputs

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 TTL Logic Family
§ Determining the Fan-Out
To determine how many different inputs an output IC can drive, you must know the capacity of the output and
the current requirements of each input. This information is always presented by the manufacturer's technical
datasheet.
A good method for determining the loading of any digital output is:
Step 1: Add the 𝐼!" or all inputs connected to an output. This sum must be less than the output’s 𝐼#"
specification.
Step 2: Add the 𝐼!$ for all inputs connected to an output. This sum must be less than the output’s 𝐼#$
specification.
𝐼"#
𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑖𝑛𝑝𝑢𝑡𝑠 𝐻𝐼𝐺𝐻 = If the fanout (LOW) and the fanout (HIGH) are not
𝐼$#
the same, the fanout is chosen asthe smaller of the
𝐼"%
𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑖𝑛𝑝𝑢𝑡𝑠 𝐿𝑂𝑊 = two.
𝐼$% 23
 TTL Logic Family
§ Current ratings of TTL series logic gates

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 TTL Logic Family
§ Example:
How many 74ALS00 NAND gate inputs can be driven by one 74ALS00 NAND gate output?

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 TTL Logic Family
§ Example:
One 74ALS00 NAND gate output drives three 74S gate inputs and one 7406 input. Determine if there is a
loading problem.

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 TTL Logic Family
§ Example:
The output of a 74AS04 inverter provides the CLEAR signal to a parallel register composed of 74AS74 D flip-
flops. What is the maximum number of flip-flop inputs that the inverter gate can drive?

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 TTL Logic Family
§ Unconnected Inputs (Floating)
Any input to a TTL circuit that is left disconnected (open) acts exactly like a logical 1 applied to that input
because in either case the emitter–base junction or diode at the input will not be forward-biased. This means that
on any TTL IC, all of the inputs are 1s if they are not connected to some logic signal or to ground.

When an input is left unconnected, it is said to be floating.

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 TTL Logic Family
§ Unused Inputs
Frequently, not all of the inputs on a TTL IC are being used in a particular application. A common example is
when not all the inputs to a logic gate are needed for the required logic function. Although the logic is correct, it
is highly undesirable to leave an input disconnected because it will act like an antenna, which is liable to pick up
stray radiated signals that could cause the gate to operate improperly.

Example: Three ways to handle unused logic inputs. 29

 TTL Logic Family
§ Tied-Together Inputs
When two (or more) TTL inputs on the same gate are connected together to form a common input, as in Figure:

the common input will generally represent a load that is the sum of the load current rating of each individual
input.

The only exception is for NAND and AND gates. For these gates, the LOW-state input load will be the same as
a single input no matter how many inputs are tied together.

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 TTL Logic Family
§ Tied-Together Inputs
To illustrate, assume that each input of the three-input NAND gate is rated at 0.5 mA for 𝐼!$ and 20 µA for 𝐼!" .
The common input B will therefore represent an input load of 40 µA in the HIGH state but only 0.5 mA in the
LOW state. The same would be true if this were an AND gate. If it were an OR or a NOR gate, the common B
input would present an input load 40 µA in the HIGH state and 1 mA in the LOW state.
The reason for this characteristic can be found by looking back at the circuit diagram of the TTL NAND gate.
The current 𝐼!$ is limited by the resistance 𝑅* (Figure: Basic TTL NAND gate).
Even if inputs A and B were tied together and grounded, this current would not change; it would merely divide
and flow through the parallel paths provided by diodes 𝐷+ and 𝐷, . The situation is different for OR and NOR
gates, because they do not use multiple-emitter transistors but rather have a separate input transistor for each
input(Figure: Basic TTL NOR gate).

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 TTL Logic Family
§ Example:
Determine the load that output X is driving in Figure below. Make sure each gate is a 74LS series TTL with
𝐼!" = 20 𝜇𝐴 and 𝐼!$ = 0,4 𝑚𝐴.

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 TTL Logic Family
§ Biasing TTL Inputs Low
the situation arises where a TTL input must be held normally LOW and then caused to go HIGH by the actuation
of a mechanical switch.
The resistor R serves to keep the T input LOW while the switch is open. Care must be taken to keep the value of
R low enough so that the voltage developed across it by the current 𝐼!$ that flows out of the OS input to ground
will not exceed 𝑉!$ (𝑚𝑎𝑥).
R must be kept below 𝑅-./ this value to ensure that the OS input will be at an acceptable LOW level while the
switch is open.

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 TTL Logic Family
§ Example
Determine an acceptable value for R if the OS is a TTL 74LS IC with an input 𝐼!$ of 0.4 mA.

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 Outline

Ø Integrated-Circuit Logic Families (Chapter 5 Book)

q Digital IC Terminology

q TTL Logic Family

q ECL Logic Family

q CMOS Logic Family

q Integrated Circuit Interfacing

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 ECL Logic Family
§ ECL logic circuit
The TTL family uses transistors operating in saturated mode. Therefore, their switching speed is limited by the
storage delay time associated with a transistor being driven into saturation. Another family of bipolar logic was
developed to prevent transistor saturation, thereby increasing overall switching speed. This logic family is called
ECL (Emitter-Coupled Logic), s switched from the collector of one transistor to another. Due to this current-
mode operation, this logic form is also called CML (Current-mode logic).

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 ECL Logic Family
§ ECL Logic Circuit
The basic ECL circuit is essentially the
differential amplifier configuration in the
figure opposite.

Two important points should be noted:

§ 𝑉&* and 𝑉&+ are the complements of each other.
§ Output voltage levels are not the same as input logic
Basic ECL circuit
levels.
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 ECL Logic Family
§ ECL Logic Circuit

Basic ECL circuit with addition of emitter followers 38

 ECL Logic Family
§ ECL Logic Circuit

Logic Symbol

ECL NOR/OR circuit 39

 ECL Logic Family
§ Caractéristiques ECL
Ø The transistors never saturate, and therefore the switching speed is very high. Typical propagation time is 360
ps, making the ECL faster than any serial in the TTL or CMOS family.
Ø The logic levels are nominally -0.8 V and -1.7 V for logic 1 and 0, respectively.
Ø Worst-case ECL noise margins are around 150 mV. These low noise margins make ECL unreliable for use in
heavy industrial environments.
Ø An ECL logic block generally produces an output and its complement. This eliminates the need for an
inverter.
Ø The fanout is typically around 25.
Ø Typical power dissipation is 25 mW.
Ø The total current flow in an ECL circuit remains relatively constant, regardless of its logic state. This helps
maintain a constant current on the power supply even during switching transitions.
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 ECL Logic Family
§ High-speed logic comparison

41
 Outline

Ø Integrated-Circuit Logic Families (Chapter 5 Book)

q Digital IC Terminology

q TTL Logic Family

q ECL Logic Family

q CMOS Logic Family

q Integrated Circuit Interfacing

42
 CMOS Logic Family
§ CMOS TECHNOLOGY

CMOS integrated circuits provide not only all of the same logic functions available in TTL but also several

special functions not provided by TTL.

Before looking at the different CMOS series, it will be helpful to define a few terms that are used when ICs from

different families or series are to be used together or as replacements for each other.

Ø Pin-compatible.

Ø Functionally equivalent.

Ø Electrically compatible.

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 CMOS Logic Family

§ CMOS series logic families

Ø 4000/14000 Series
Ø 74HC/HCT (High-Speed CMOS)
Ø 74AC/ACT (Advanced CMOS)
Ø 74AHC/AHCT (Advanced High-Speed CMOS)
Ø BiCMOS 5-V Logic

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 CMOS Logic Family

§ CMOS Series Features

Ø CMOS devices have larger noise margins than TTL. The difference would be even greater if CMOS devices

operated at a supply voltage higher than 5 V.

Ø The dissipated power of CMOS devices varies between 2.5 nW and 10 nW per gate.

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 CMOS Logic Family
§ N-channel MOSFET used as a switch

Symbol Circuit Model N-MOS Inverter Operation 46

 CMOS Logic Family
§ P-channel MOSFET used as a switch

Symbol Circuit Model P-MOS Inverter Operation 47

 CMOS Logic Family
§ P- and N-channel switching characteristics

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