CHAPTER 6

Analog Front End

Mixed-Signal IC Design for Image Sensor 6- 1 Chih-Cheng Hsieh

 Outline
• 6.1 Introduction
• 6.2 Switched-Capacitor Circuit
• 6.3 SC Application
• 6.4 Noise in SC
• 6.5 Non-ideal Effects in SC
• 6.6 Practical Issues

Mixed-Signal IC Design for Image Sensor 6- 2 Chih-Cheng Hsieh

 Outline
• 6.1 Introduction
• 6.2 Switched-Capacitor Circuit
• 6.3 SC Application
• 6.4 Noise in SC
• 6.5 Non-ideal Effects in SC
• 6.6 Practical Issues

Mixed-Signal IC Design for Image Sensor 6- 3 Chih-Cheng Hsieh

 Introduction
• Analog front end
– Correlated double sampling (CDS) : optional
– Programmable gain amplifier (PGA)
– Digital to analog converter (DAC)
– Analog to digital converter (ADC)

Mixed-Signal IC Design for Image Sensor 6- 4 Chih-Cheng Hsieh

 AFE for CCD

Mixed-Signal IC Design for Image Sensor 6- 5 Chih-Cheng Hsieh

 Commercial CIS Product

Mixed-Signal IC Design for Image Sensor 6- 6 Chih-Cheng Hsieh

 Correlated Double Sampling
• Purpose of CDS
– Inter-chip signal sampling, signal clamp (CCD + AFE)
– Offset cancellation
– Fixed pattern cancellation
– KTC cancellation
– Signal buffering & level shifting

Mixed-Signal IC Design for Image Sensor 6- 7 Chih-Cheng Hsieh

 Programmable Gain Amplifier
• Purpose of PGA
– CDS implementation
– Single-to-differential conversion
– Signal amplification
– Color balance in analog domain (white balance)
– ADC input level fitting : signal full-swing tuning

Mixed-Signal IC Design for Image Sensor 6- 8 Chih-Cheng Hsieh

 Switched Capacitor PGA

Mixed-Signal IC Design for Image Sensor 6- 9 Chih-Cheng Hsieh

 Digital to Analog Converter
• Purpose of DAC
– Signal path offset cancellation
– Optical black calibration (analog domain)
– SC implementation with PGA 16Cu
CP

VX Vo
A
8Cu 4Cu 2Cu Cu

VR

b3 b2 b1 b0

Mixed-Signal IC Design for Image Sensor 6- 10 Chih-Cheng Hsieh

 Analog to Digital Converter
• Purpose of ADC
– Digitization for subsequent signal processing
– 8b ~ 12b depends on application
– Single / Column-parallel / Pixel-parallel implementation
depends on required bandwidth
– Pipeline / Single-slope / SAR / Cyclic …

Mixed-Signal IC Design for Image Sensor 6- 11 Chih-Cheng Hsieh

 Outline
• 6.1 Introduction
• 6.2 Switched-Capacitor Circuit
• 6.3 SC Application
• 6.4 Noise in SC
• 6.5 Non-ideal Effects in SC
• 6.6 Practical Issues

Mixed-Signal IC Design for Image Sensor 6- 12 Chih-Cheng Hsieh

 Continuous-Time Integrator

t
C2 1
vo  t     v   d 
R1  C2
in
R1 
Vi Vo  1  1
H s  s  
Vo

Vi R 
 1 2 s
C

  R1  C2
C2

Goal: Vi SC
Vo

Approach: emulating resistors with switched capacitors

Mixed-Signal IC Design for Image Sensor 6- 13 Chih-Cheng Hsieh

 Concept of Switched Capacitor

Ф2 C Ф2 Non-overlapping
R VA VB
VA VB
two-phase clock
Ф1 <i> Ф1
i
Ф1

i
1
VA  VB  i   VA  VB 
q C Ф2
R T T

T T C
 Req 
C
so,   Req ,1  C2 
C1
 C2  T  2
C1

• A switched capacitor is a discrete-time “resistor”

• RC time constant set by capacitor ratio C2/C1 (match considerably
better than R and C) and clock period T (flexibility)

Mixed-Signal IC Design for Image Sensor 6- 14 Chih-Cheng Hsieh

 Switched Capacitors

Shunt-type Series-type 2-phase clock

Ф1 Ф2 Ф1 C
VA VB VA VB
Ф1 Ф2 Ф1 Ф2 Ф1 Ф2
C Ф2

Ф2(Ф1) C Ф2
VA VB
Stray-insensitive
Ф1(Ф2) Ф1

• Shunt- and series-type SCs are simple and cheap to implement

• Stray-insensitive SC requires 2 more switches

Mixed-Signal IC Design for Image Sensor 6- 15 Chih-Cheng Hsieh

 Discrete-Time Integrator (DTI)

Shunt-type Series-type

C2
Ф2 C2
Ф1 Ф2
Ф1 C1
Vi
Vo Vi
Vo
C1

2-phase clock

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

Mixed-Signal IC Design for Image Sensor 6- 16 Chih-Cheng Hsieh

 Shunt-Type DTI
T
Ф1 C2
(sample) Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

Vi
Vo


C1 vi(t)
(n-1)
(n)
0 t

(n+1)
Ф2 C2
(update)
vo(t) (n+1)
(n)
Vi
Vo 0 t
C1 (n-1)

Charge conservation law (ideal):

Total charge on C1 and C2 during Ф1→ Ф2 transition must remain unchanged!

Mixed-Signal IC Design for Image Sensor 6- 17 Chih-Cheng Hsieh

 Shunt-Type DTI

Ф1 Ф2
(sample) C2 (update) C2

Vi
C1
Vo  Vi
C1
Vo

 Q   V n C  V n C

1 i 1 o 2  Q   0  C  V n  1 C
2 1 o 2

 Q    Q 
1 2  Vi n C1  Vo n C2  0  C1  Vo n  1 C2

Vi z  C1  Vo z  C2   z Vo z  C2

Vo  z  C1 z 1
H  z  
Vi  z  C2 1  z 1

Mixed-Signal IC Design for Image Sensor 6- 18 Chih-Cheng Hsieh

 Series-Type DTI
T

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2 Ф1 Ф2
(sample/update)  (reset C1)
vi(t)
(n-1)
(n)
0 t
Ф2 C2
(n+1)
Ф1 C1
Vi vo(t) (n)
Vo
(n-1)
0 t

(n+1)

 Q     Q  
2 1  0  C1  Vo  n   C2  Vi  n  1  C1  Vo  n  1  C2
Vo  z   C2  z Vi  z   C1  z Vo  z   C2

Vo z 
H z  
C 1
VTF:  1
Vi z  C2 1  z 1

Mixed-Signal IC Design for Image Sensor 6- 19 Chih-Cheng Hsieh

 Stray Capacitance

Shunt-type Series-type

Ф1
A
Ф2
C2
Ф1
Ф2

C1
C2 ?
Vi
Vo Vi
C1 A Vo

C2
4
C1
Cu Cu
• Strays derive from D/S diodes and
wiring capacitance
Cu
• VTF is modified due to strays
Cu Cu
• Strays at the summing node is of no
significance (virtual ground)
C1 C2

Mixed-Signal IC Design for Image Sensor 6- 20 Chih-Cheng Hsieh

 Stray-Insensitive SC Integrator
C2

Ф2(Ф1) A C1 B Ф2
Vi
Vo
Ф1(Ф2) Ф1

“Inverting” “Non-inverting”

C1 z 1
H z    1
C 1
H z   
VTF: VTF:
C2 1  z 1 C2 1  z 1

• Capacitors can be significantly sized down to save power/area

• Sizes are eventually limited by kT/C noise, mismatch, etc.

Mixed-Signal IC Design for Image Sensor 6- 21 Chih-Cheng Hsieh

 SC Amplifier

Ф1

C2

Ф1 C1 C1 1
VTF: H  z   z
Vi C2
Vo
Ф2

• Gain implemented by C ratio

• No resistive loading of amplifier (high gain)

Mixed-Signal IC Design for Image Sensor 6- 22 Chih-Cheng Hsieh

 SC Unit Gain Buffer

Mixed-Signal IC Design for Image Sensor 6- 23 Chih-Cheng Hsieh

 Early Sampling

• S2 turning OFF a little earlier than S1

• Reduce signal dependent switching error

Mixed-Signal IC Design for Image Sensor 6- 24 Chih-Cheng Hsieh

 Switching Error

• VX is floating by turning off S2, and define the charge on CH

• S1 turning OFF will not change the charge on CH

Mixed-Signal IC Design for Image Sensor 6- 25 Chih-Cheng Hsieh

 Differential Realization

• Seq turning OFF a little after S2 and earlier than S1

• To solve the mismatch of S2 and S2’

Mixed-Signal IC Design for Image Sensor 6- 26 Chih-Cheng Hsieh

 Finite Gain Effect

VX Vout
VX  0 VX  
Av1 Av1

Q[n]  CH (0  Vin )  CinVX  CH (VX  Vout )  Q[n  1]

Vin  1  Cin  
Vout   Vin 1  1  
1  Cin   A  C H 
1  1  
A  CH 

Mixed-Signal IC Design for Image Sensor 6- 27 Chih-Cheng Hsieh

 Bottom Plate Sampling

• Bottom plate sampling

• Minimize Cin, increase SC gain precision

Mixed-Signal IC Design for Image Sensor 6- 28 Chih-Cheng Hsieh

 SC Gain Stage
Early sampling Finite gain

Vout C1 C  C  C1  Cin 1 

   1 1  2 
Vin C  C2  C1  Cin C2  C2 A
2
A

Mixed-Signal IC Design for Image Sensor 6- 29 Chih-Cheng Hsieh

 Outline
• 6.1 Introduction
• 6.2 Switched-Capacitor Circuit
• 6.3 SC Application
• 6.4 Noise in SC
• 6.5 Non-ideal Effects in SC
• 6.6 Practical Issues

Mixed-Signal IC Design for Image Sensor 6- 30 Chih-Cheng Hsieh

 CT Filter
R L

Vi C Vo RLC prototype

R2

R4

CA R CB
Active-RC
R1 R R3 Tow-Thomas
Vi
Vo CT biquad

Mixed-Signal IC Design for Image Sensor 6- 31 Chih-Cheng Hsieh

 SC DT Filter
R2

R4

CA R CB
Active-RC
R1 R R3 Tow-Thomas
Vi
Vo CT biquad


C2 Ф1

CA C4 CB Ф2

Ф2 C1 Ф2 Ф1 C3 Ф2 SC DT
Ф2
Vi biquad
Vo
Ф1 Ф1 Ф2 Ф1

Mixed-Signal IC Design for Image Sensor 6- 32 Chih-Cheng Hsieh

 Sigma-Delta (ΣΔ) Modulator

CI

Ф1 CS Ф2
Vi
Do
Ф2 Ф1

+VR 1-b
-VR DAC

DTI + 1-bit comparator + 1-bit DAC = first-order ΣΔ ADC

Mixed-Signal IC Design for Image Sensor 6- 33 Chih-Cheng Hsieh

 Pipelined ADC

Φ2

Φ1 C1
Vi
Φ1 C2
-VR/4 Vo
VR/4 Φ1

-VR Φ2
1.5-b
0
DAC
VR

SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC

Mixed-Signal IC Design for Image Sensor 6- 34 Chih-Cheng Hsieh

 Outline
• 6.1 Introduction
• 6.2 Switched-Capacitor Circuit
• 6.3 SC Application
• 6.4 Noise in SC
• 6.5 Non-ideal Effects in SC
• 6.6 Practical Issues

Mixed-Signal IC Design for Image Sensor 6- 35 Chih-Cheng Hsieh

 Noise of CT Integrator

H1(f)
C C

R VN12 R
Vi
Vo Vo

VN22
H2(f)

VN 12 VN 2 2
   1     2   df 
2 2
VoN 2
f  H f df  f  H f
f f

Noise in CT circuits can be simulated with SPICE (.noise)

Mixed-Signal IC Design for Image Sensor 6- 36 Chih-Cheng Hsieh

 Noise of SC Integrator

C2

Ф1 C1 Ф2
Vi
Vo

Ф2 Ф1

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

SC circuits are NOT noise-free! Switches and op-amps introduce noise.

Mixed-Signal IC Design for Image Sensor 6- 37 Chih-Cheng Hsieh

 Sampling (Ф1) Ideal Voltage Source

VN12 R1 C1 VN22
Vi

R2

 VN 12 VN 2 2 
VN 1       1   df
2
2
 f  f  H f
 f f 
0

2
 1
   4kTR1  4kTR2   df
0 1  j 2 f   R1  R2  C
kT

C

• Noise is indistinguishable from signal after sampling

• The noise acquired by C1 will be amplified in Ф2 just like signal

Mixed-Signal IC Design for Image Sensor 6- 38 Chih-Cheng Hsieh

 Integration (Ф2)
H34(f)
C2

VN32 C1 VN42 R4
Vo
R3
VN52
H5(f)

VN 32 VN 4 2  VN 52
VN  2      f   f   H 34  f  df    f   H 5  f  df 
2 2 2

 f f  f

2
C 
  1  VN 1  VN  2
2 2 2
VoN
 C2 

No simulator can directly simulate the aggregated output noise!

Mixed-Signal IC Design for Image Sensor 6- 39 Chih-Cheng Hsieh

Sampling (Ф1) Noise – Cascaded Stages
C2 C2'

Ф2 C1 Ф1 Ф1 C1' Ф2
Ф2
Vi
Vo
Ф1 Ф2 Ф2 Ф1


C2

VN32 C1 VN42 R4 VN12 R1 C 1' VN22

R3
VN52 R2

• Finite op-amp BW limits the noise bandwidth, resulting in less overall kT/C noise
(noise filtering).
• But parasitic loop delay may introduce peaking in freq. response, resulting in more
integrated noise (noise peaking).
Mixed-Signal IC Design for Image Sensor 6- 40 Chih-Cheng Hsieh
 Sampled Noise Spectrum

CT PSD

0
fs 2fs

Alias
DT PSD

0
fs/2 fs 3/2fs

• Total integrated noise power remains constant

• SNR remains constant

Mixed-Signal IC Design for Image Sensor 6- 41 Chih-Cheng Hsieh

 Outline
• 6.1 Introduction
• 6.2 Switched-Capacitor Circuit
• 6.3 SC Application
• 6.4 Noise in SC
• 6.5 Non-ideal Effects in SC
• 6.6 Practical Issues

Mixed-Signal IC Design for Image Sensor 6- 42 Chih-Cheng Hsieh

 Nonideal Effects in SC Circuits
• Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich,
gate cap, accumulation-mode gate cap, etc.)
– PP, MIM, and MOM are linear up to 14-16 bits (nonlinear voltage coefficients
negligible for most applications)
– Gate caps are typically good for up to 8-10 bits

• Switches (MOS transistors)

– Nonzero on-resistance (voltage dependent)
– (Nonlinear) stray capacitance added (Cgs, Cgd, Cgb, Cdb, Csb)
– Switch-induced sampling errors (charge injection, clock feedthrough, junction
leakage, drain-source leakage, and gate leakage)

• Operational amplifiers
– Offset
– Finite-gain effects (voltage dependent)
– Finite bandwidth and slew rate (measured by settling speed)

Mixed-Signal IC Design for Image Sensor 6- 43 Chih-Cheng Hsieh

 Nonzero On-Resistance
C
Ron
Ф PMOS
VGS
… NMOS
VTp VTn
Vout CS

CMOS
Ф
0 Vout VDD

…
CS 1
Ron  Cox
W
VDD  Vth  Vout 
Ф L

• FET channel resistance (thus tracking bandwidth) depends on signal level

• Usually (RonCS)-1 ≥ (3-5)·ω-3dB of closed-loop op-amp for settling purpose

Mixed-Signal IC Design for Image Sensor 6- 44 Chih-Cheng Hsieh

 Clock Bootstrapping

Ф
Ф1 Ф2
…
CS VDD
In Out
Ф M1

CMOS Bootstrapped NMOS

• Small on-resistance leads to large switches → large parasitic caps and

large clock buffers
• Clock bootstrapping keeps VGS of the switch constant → constant on-
resistance (body effect?) and less parasitics w/o the PMOS

Mixed-Signal IC Design for Image Sensor 6- 45 Chih-Cheng Hsieh

 Simplified Clock Bootstrapper

Ф1 Ф2

VDD
In Out
Pros
M1
VDD • Linearity

Ф2 M2
• Bandwidth
Ф2
Cons
Ф2
C • Device reliability
Ф1 Ф1 • Complexity
Out
M1
Ф2
In
VSS

Mixed-Signal IC Design for Image Sensor 6- 46 Chih-Cheng Hsieh

 Double Bootstrapper

Mixed-Signal IC Design for Image Sensor 6- Chih-Cheng Hsieh

 Switch-Induced Errors

Zi Cgs Cgd • Clock feedthrough

Vout
• Charge injection
Vin Qch CS

Channel charge injection and clock feedthrough (on drain side) result in
charge trapped on CS after switch is turned off.

Mixed-Signal IC Design for Image Sensor 6- 48 Chih-Cheng Hsieh

Clock Feedthrough / Charge Injection
Ф
VDD Vin+Vth
Zi Cgs Cgd Ф
Vout 0
Vin Qch CS Switch on Switch off

Charge Injection

• Both phenomena sensitive to Zi, CS, and clock rise/fall time

• Offset, gain error, and nonlinearity introduced to the sampling
• Clock feedthrough can be simulated by SPICE, but charge injection
cannot be simulated with lumped transistor models
Mixed-Signal IC Design for Image Sensor 6- 49 Chih-Cheng Hsieh
 Clock Rise/Fall-Time Dependence
Qch  CoxWL VDD  Vth  Vin 
Ф

VDD Vin+Vth
Zi Cgs Cgd
Vout Ф
0
Vin Qch CS
Switch on Switch off

Clock feedthrough Charge injection

C gs CoxWLVDD  Vth  Vin 

V   V  
2C gs  CS 
Fast turn-off VDD
C gs  CS
C gs
Slow turn-off V   Vin  Vth  V  0
C gs  CS

Mixed-Signal IC Design for Image Sensor 6- 50 Chih-Cheng Hsieh

 Dummy Switch

Ф Ф

Vin Vout
W W
L 2L CS

• Difficult to achieve precise cancellation due to the nonlinear

dependence of ΔV on Zi, CS, and clock rise/fall time
• Sensitive to the phase alignment between Ф and Ф_

Mixed-Signal IC Design for Image Sensor 6- 51 Chih-Cheng Hsieh

 Dummy Switch

Charge injection cancellation

(Signal dependent)

Clock feedthrough cancellation (Depend on W/L only)

Mixed-Signal IC Design for Image Sensor 6- 52 Chih-Cheng Hsieh
 CMOS Switch

Vin Vout Same size for

P and N FETs
CS
Ф

• Very sensitive to phase alignment between Ф and Ф_

• Subject to threshold mismatch between PMOS and NMOS
• Exact cancellation occurs only for one specific Vin (which one?)

Mixed-Signal IC Design for Image Sensor 6- 53 Chih-Cheng Hsieh

 CMOS Switch

Mixed-Signal IC Design for Image Sensor 6- 54 Chih-Cheng Hsieh

 Differential Signaling
Ф

Vip Vop
M1
CSp
Ф

Vin Von
M2
CSn

Balanced diff. input

• Signal-independent errors (offset) and even-order distortions cancelled

• Gain error and odd-order nonlinearities remain

Mixed-Signal IC Design for Image Sensor 6- 55 Chih-Cheng Hsieh

 Switch Performance

1 L2 L2
On-resistance: Ron   
μCox
W
VDD  Vth  Vi  μCox WL VDD  Vth  Vi  μQch
L
1 μQ
Bandwidth: BW   2 ch
RonCS L CS

1 Qch
Charge injection: ΔV 
2 CS

ΔV 1 Qch L2CS L2
Performance FoM: ≈  =
BW 2 CS μQch 2μ

Technology scaling improves switch performance!

Mixed-Signal IC Design for Image Sensor 6- 56 Chih-Cheng Hsieh

 Leakage in SC Circuits

Φ1 = “high”, Φ2 = “low”
C2 Vo(t)
Ф2 Ф2
C1
Vx
Vi
Vo
I3
Ф1 Ф1 I2 I1 A0 Ф1 Ф2 Ф1 Ф2
VB 0 t

• I1 – diode leakage (existing in the old days too)

• I2 – sub-threshold drain-source leakage of summing-node switch
• I3 – gate leakage (FN tunneling) of amplifier input transistors
• Leakage currents are highly temperature- and process-dependent; the
lower limit of clock frequency is often determined by leakage

Mixed-Signal IC Design for Image Sensor 6- 57 Chih-Cheng Hsieh

 Gate Leakage

I GS  WL  exp  tox  exp VGS 

• Direct tunneling through the thin gate oxide

• Short-channel MOSFET behaves increasingly like BJT’s
• Violates the high-impedance assumption of the summing node

Mixed-Signal IC Design for Image Sensor 6- 58 Chih-Cheng Hsieh

 Switch Size Optimization
• To minimize switch-induced error voltages, small transistor size, slow turn-
off, low source impedance should be used.
• For fast settling (high-speed design), large W/L should be used, and errors
will be inevitably large as well.

Guidelines
• Always use minimum channel length for switches as long as leakage
allows.
• For a given speed, switch sizes can be optimized w/ simulation.
• Be aware of the limitations of simulators (SPICE etc.) using lumped device
models.

Mixed-Signal IC Design for Image Sensor 6- 59 Chih-Cheng Hsieh

 Nonideal Effects of Op-Amps
• Offset
• Finite-gain effects (voltage dependent)
• Finite bandwidth and slew rate (measured by settling speed)

Mixed-Signal IC Design for Image Sensor 6- 60 Chih-Cheng Hsieh

 Offset Voltage

C2

Vi
Ф1 C1 Ф2
 Q   V nC  V n  V C
1 i 1 o os 2
Vo
Ф2 Ф1
 Q   V C1  Vo n  1  Vos C2
Vos
2 os

C 
Vo(t) Vi  0  Vo  n  1  Vo  n    1 Vos
 C2 

C1 z 1
Ф1 Ф2 Ф1 Ф2
Vo  z   1 i  
V z
C2 1  z
0 t
Vi = 0

Mixed-Signal IC Design for Image Sensor 6- 61 Chih-Cheng Hsieh

 Autozeroing

 Q   V n  V C  V
Ф1
1 i os 1 C2
os
C2 Ф2

Ф1 C1 Ф1  Q   V
2 os C1  Vo n  Vos C2
Vi
Vo
Ф2 Vos

Vo z  C1
H z   
Vi z  C2

• Also eliminates low-frequency noise, e.g., 1/f noise

• A.k.a. correlated double sampling (CDS)

Mixed-Signal IC Design for Image Sensor 6- 62 Chih-Cheng Hsieh

 Chopper Stabilization

Vn2
A B
Vi A1 A2 Vo

fC
1
-1

Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, “A low-noise

chopper-stabilized differential switched-capacitor filtering technique,” IEEE Journal of
Solid-State Circuits, vol. 16, issue 6, pp. 708-715, 1981.

Mixed-Signal IC Design for Image Sensor 6- 63 Chih-Cheng Hsieh

 Chopper Stabilization

|Vi|2

Vn2
0
A B fC f
Vi A1 A2 Vo
SN(f)

fC
1 0
-1 fC f
2
|VA|

0
Also eliminates DC offset fC f
2
|VB|
voltage of A1
0
fC f

Mixed-Signal IC Design for Image Sensor 6- 64 Chih-Cheng Hsieh

 Chopper-Stabilized Diff. Op-Amp

Ф Ф

Vi+
Ф Ф
Vo+
Vo-
Ф Ф
Vi-

Ф Ф

• Integrators/amplifiers can be built using these op-amps

• Some oversampling is useful to facilitate the implementation

Mixed-Signal IC Design for Image Sensor 6- 65 Chih-Cheng Hsieh

 Ideal SC Amplifier

Ф1

C2

Ф1 C1 C1
ACL 
Vi C2
X ∞ Vo
Ф2

• Closed-loop gain is determined by the capacitor ratio by design

• But this is assuming X is an ideal summing node (the op-amp is ideal)

Mixed-Signal IC Design for Image Sensor 6- 66 Chih-Cheng Hsieh

 Finite-Gain Effect in SC Amplifier
Ф1

C2
Vo C1 1 C  C  C2 
ACL     1  1  1 
Ф1 Vi C2 1  C1  C2 C2 
C1
C2 A 
Vi
X A Vo C2 A
Ф2

 Q    V    V    C  0  C
1 i 1 x 1 1 2  Q    V    C  V    V    C
2 x 2 1 o 2 x 2 2

Vx 1   Vo 1   Vx 1   A Vo 2   Vx 2   A

 Q     Q  
1 2  Vi  C1  Vx  C1  Vo  Vx   C2

Vo  Vx  A

Mixed-Signal IC Design for Image Sensor 6- 67 Chih-Cheng Hsieh

 Outline
• 6.1 Introduction
• 6.2 Switched-Capacitor Circuit
• 6.3 SC Application
• 6.4 Noise in SC
• 6.5 Non-ideal Effects in SC
• 6.6 Practical Issues

Mixed-Signal IC Design for Image Sensor 6- 68 Chih-Cheng Hsieh

 Analog vs. Digital Supply Lines

VA  VDD  VL  VR

did
VL  L VR  id R
dt
id=
Pad

Analog Digital
VDD CBP
circuits circuits

Pad

Sharing sensitive analog supplies with digital ones is a very bad idea.

Mixed-Signal IC Design for Image Sensor 6- 69 Chih-Cheng Hsieh

 Analog vs. Digital Supply Lines

id=
Pad • Dedicated pads for
analog and digital
Pad
supplies
• On-chip bypass
Analog Digital capacitors help (watch
VDD CBP
circuits circuits ringing)
• Off-chip chokes (large
Pad
inductors) can stop
noise propagation at
Pad board level

Mixed-Signal IC Design for Image Sensor 6- 70 Chih-Cheng Hsieh

 “Supply” Capacitance
C2

VDD
Cp
… Cstray
M5 M7
Vo  V 
Cgs C2
Ф1 C1 Ф2 S
Vi M1 M2 Vo
X
Ф2 Ф1
Cgd Y CC

M3 M4 M6

VSS

• Any summing-node stray capacitance can be a potential coupling path.

• VDD, VSS, substrate, clock line, and digital noises, body effect, etc.
• Fully differential circuits help to reject common-mode noise and coupling.
Mixed-Signal IC Design for Image Sensor 6- 71 Chih-Cheng Hsieh
 “Supply” Capacitance

C2

Cbot
p+
p well

n substrate

• Avoid connecting bottom-plate parasitics to the summing node

• Avoid crossing other signal lines with the summing node
• Shielding can mitigate substrate noise coupling

Mixed-Signal IC Design for Image Sensor 6- 72 Chih-Cheng Hsieh

 Clock Generation

CLK Ф2
Ф2

Ф1
Ф1

• Clock-gated ring structure

• Non-overlapping time determined by inverter delays, sensitive to process,
voltage, and temperature (PVT) variations
• DLL is an alternative, often used in high-speed designs

Mixed-Signal IC Design for Image Sensor 6- 73 Chih-Cheng Hsieh

 Review of CMOS Operational
Amplifiers

Mixed-Signal IC Design for Image Sensor 6- 74 Chih-Cheng Hsieh

 Negative Feedback

β
δA CL δA(Vo ) 1
 
Vε A CL A(Vo ) βA(Vo )
Vi δA(Vo ) 1
Vo  
A(Vo ) T
A(Vo)
1 1
THD ~ 
βA(Vo ) T
A(Vo )
V A(Vo ) 1
A CL  o  
Vi 1 βA(Vo ) β

• Closed-loop linearity is achieved by negative feedback with large loop

gain
• Negative feedback reduces gain sensitivity and harmonic distortion
Mixed-Signal IC Design for Image Sensor 6- 75 Chih-Cheng Hsieh
 Folded-Cascode Op-Amp

VDD
• Differential
2VDSAT
• A0 ~ (gm·ro)2 ~ 40-50dB
• Vo,pp ~ 2(VDD-4VDSAT)
• Noise factor ~ 3
Vo Vo
Vi • ωp2 ~ fT/3
• Efficiency ~ 50%

CMFB 2VDSAT • Load-compensated

• Flexible input CM

Most often used single-stage topology, easy to bias

Mixed-Signal IC Design for Image Sensor 6- 76 Chih-Cheng Hsieh

 Telescopic Op-Amp

VDD
• Differential
2VDSAT
• A0 ~ (gm·ro)2 ~ 40-50dB
• Vo,pp ~ 2(VDD-5VDSAT)
Vo Vo
• Noise factor ~ 2
• ωp2 ~ fT/2

Vi • Efficiency ~ 100%
3VDSAT
• Load-compensated
CMFB
• Fixed input CM

2X more power-efficient than the folded-cascode topology, fast

Mixed-Signal IC Design for Image Sensor 6- 77 Chih-Cheng Hsieh

 Two-Stage Op-Amp

VDD • Differential
VDSAT
• A0 ~ (gm·ro)3 ~ 60-70dB

Vo • Vo,pp ~ 2(VDD-3VDSAT)
Vo
• N2 = N1·β·CM/CL
CM
CM • Noise factor ~ 2+2β
• ωp2 ~ gm2/CL
Vi
2VDSAT
• Efficiency < 50%
CMFB CMFB • Miller-compensated
• Fixed input CM

Not as power-efficient as single stage, suitable for low VDD

Mixed-Signal IC Design for Image Sensor 6- 78 Chih-Cheng Hsieh

 Pseudo-Differential Op-Amp

VDD
• Differential

2VDSAT
• A0 ~ (gm·ro)2 ~ 40-50dB
• Vo,pp ~ 2(VDD-4VDSAT)
• Noise factor ~ 2
Vo Vo • ωp2 ~ fT/2
• Efficiency ~ 100%
• Load-compensated
2VDSAT
Vi • Fixed input CM
• No CMFB point

As power-efficient and fast as telescopic, but Vocm is a problem

Mixed-Signal IC Design for Image Sensor 6- 79 Chih-Cheng Hsieh

 CMOS Gain-Boosting
VDD VDD

Vo
Vo
Vi

Vi

CMFB CMFB

• A0 ~ Aa·(gm·ro)2 ~ 60-100dB, limited by substrate current

• Single-stage design, same output swing, suitable for SC circuits
• Auxiliary amplifiers introduce pole-zero doublet (slow settling), additional noise
Mixed-Signal IC Design for Image Sensor 6- 80 Chih-Cheng Hsieh
 Nested CMOS Gain-Boosting
VDD = 1.8 V VDD = 1.8 V

Vcmp

size ratio
Ap
64:8:1
Vo- Vo+
Vcmp

An

Vcmn
Vi + Vi-

PD main amp Folded-cascode booster

• Two levels of recursive gain-boosting → A0 ≈ (gm∙ro)6 ≥ 120 dB

• Pseudo-differential architecture → p-p differential output swing ≥ 2 V
Mixed-Signal IC Design for Image Sensor 6- 81 Chih-Cheng Hsieh
 Reference
• Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012.
• Omnivision Product Datasheet
• J. Ohta, Smart CMOS Image Sensor and Applications, 2008

Mixed-Signal IC Design for Image Sensor 6- 82 Chih-Cheng Hsieh