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MP ASS2 Part 2 of 2

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29 views3 pages

MP ASS2 Part 2 of 2

Uploaded by

ayushsutariya30
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Q3. Design an 8085 microprocessor system with 16KByte of EPROM and 4KByte of RAM, we can use two 8KByte EPROM chips (2764) and two 2KByte RAM chips (6116). 1. EPROM Configuration: © Two 2764 EPROM chips are needed to achieve 16KByte of EPROM. © Each 2764 EPROM chip has a capacity of SkByte (8192 bytes). © We'lluse the address lines Ao-A12 to eddress the EPROM chips. © Both EPROM chips will share the same data bus (Dv-D7). © The chip enable (CE) pin of each EPROM chip will be connected to the microprocessor’s address decoding logic. © The output enable (OE) pin of each EPROM chip will be connected to the mieroprocessor’s control logic. 2, RAM Configuration: © Two 6116 RAM chips are needed to achieve 4KByte of RAM. © Each 6116 RAM chip has a capacity of 2kByte (2048 bytes). © We'll use the address lines Ao-A10 to address the RAM chips. © Both RAM chips will share the same data bus (Do-D7). © The chip enable (CE) pin of each RAM chip will be connected to the microprocessor's address decoding logic. © The output enable (OE) pin of each RAM chip will be connected to the microprocessor’s control logic. 3. Address Decoding: © Address lines Ao-A1z2 will be used to select between the EPROM and RAM chips. © Ao-A12 are connected to the chip enable (CE) pins of the EPROM and RAM chips. © When Ang is low (0), it selects the EPROM chips. © When Aug is high (2), it selects the RAM chips, © Aig and Aig will remain unconnected since the system size does not exceed 64KB. 4. Starting Addresses: © The EPROM will start at address oo00H, which corresponds to Arg being low. © The RAM will start at address 4000H, which corresponds to At3 being high. p- Connections. © All EPROM and RAM chips will share the same data bus (Do-D7) and control signals (CE, 08), © The address lines (Ao-A12) will be connected to the appropriate chip enable (CE) pins of the EPROM and RAM chips for address decoding,

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