UNIT-III

UNIT-II COMPUTER ORGANIZATION

1. Instruction Codes
Every different processor type has its own design (different registers, buses, microoperations,
machine instructions, etc)
Modern processor is a very complex device It contains Many registers, Multiple arithmetic
units, for both integer and floating point calculations, The ability to pipeline several consecutive
instructions to speed execution, etc…
The Basic Computer has two components, a processor and memory. The memory has 4096
words in it, 4096 = 212, so it takes 12 bits to select a word in memory. Each word is 16 bits long

Program -A sequence of (machine) instructions. (Machine) Instruction - A group of bits

that tell the computer to perform a specific operation (a sequence of micro-operation).
The instructions of a program, along with any needed data are stored in memory. The CPU
reads the next instruction from memory. It is placed in an Instruction Register (IR). Control
circuitry in control unit then translates the instruction into the sequence of microoperations
necessary to implement it.
Instruction Formats & Addressing modes:
A computer instruction is often divided into two parts: An opcode (Operation Code) that
specifies the operation for that instruction and an address that specifies the registers and/or
locations in memory to use for that operation
In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12 bit to
specify which memory address this instruction will use. In the Basic Computer, bit 15 of the
instruction specifies the addressing mode (0: direct addressing, 1: indirect addressing). Since the
memory words, and hence the instructions, are 16 bits long.

The address field of an instruction can represent either Direct address - the address in
memory of the data to use (the address of the operand), (or) Indirect address- the address in
memory of the address in memory of the data to use.

Effective Address (EA) - The address, that can be directly used without modification to access
an operand for a computation-type instruction, or as the target address for a branch-type
instruction. Eg: Direct Addressing EA is 457, and Indirect Addressing EA is 1350.

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2. Computer Registers
Since memory is 4K in size, it requires 12 address bits. Each word of memory contains 16 bits
of data. The address register (AR) is 12 bits wide, since this system requires that many bits in
order to access memory. Similarly, the program counter (PC) is also 12 bits wide. Each data word
is 16 bits wide. The Data Register (DR) must also be 16 bits wide, since it receives data from and
sends data to memory. The accumulator (AC) acts on 16 bits of data. The Instruction Register (IR)
receives instruction codes from memory which are 16 bits wide. TR is a temporary register. Only
the CPU can cause it to be accessed. The programmer cannot directly manipulate the contents of
TR. Most CPU’s have one or more temporary registers which it uses to perform instructions. The
input and output registers (INPR and OUTR) are 8 bits wide each. For this CPU, I/O instructions
only transfer 8 bits of data at a time. The 3-bit sequence counter (SC) is used to generate the
correct timing (T) states. Other 1-bit registers are the carry out (E), the indirect register (I), the
interrupt enable (IEN) and the input and output flags (FGI and FGO).
These are shown as below:

1 0
1 P
C Memor
1 0 y
1 4096 x
A 16
R
1 0
5 I
CP
R
U
1 0 1 0
5 T 5 D
R R
7 0 7 0 1 0
OUT INP 5 A
R R C

Registers with bits are showed as below:

Label Bits Register Name Description
--------------------------------------------------------------------------------------------------------
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character

Common Bus:
The registers in the Basic Computer are connected using a bus. This gives a savings in circuitry
over complete connections between registers. It can be showed as below:

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UNIT -III
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Fig: Common Bus System

This is the internal design of the CPU for the Basic Computer. The CPU is designed around an
internal common bus with a common clock. Each register can place its data onto the bus, and has internal
tri-state buffers on the outputs. The control unit must make sure that at most one register (or memory unit)
places data onto the bus at one time. The memory unit is external to the CPU. It always receives its address
from the address register (AR) and makes its data available to the CPU bus. It receives data from the CPU
bus as well. Read and write signals are supplied by the control unit. The address registers, program counter
(PC) and data register (DR) each load data onto and receive data from the system bus. Each has a load,
increment and clear signal derived from the control unit. These signals are synchronous; each register
combines these signals with the system clock to activate the proper function. Since AR and PC are only 12-
bits each, they use the low order 12 bits of the bus. The accumulator makes its data available on the bus but
does not receive data from the bus. Instead, it receives data solely from an ALU, labeled “Adder and
Logic” in the diagram. To load data into AC, place it onto the bus via DR and pass it directly through the
ALU.
The synchronous load, increment and clear signals act as in the previous registers. Note that E, the
1-bit carry flag, also receives its data from the ALU. The input register, INPR, receives data from an
external input port, not shown here, and makes its data available only to AC. The output register makes its
data available to the output port via hardware not shown here. We will examine these two components in
more detail later in this module. The instruction register, IR, can only be loaded; it cannot be incremented
nor cleared. Its output is used to generate Di and Ti . We will look at that hardware later in this module. TR
is a temporary register. The CPU uses this register to store intermediate results of operations. It is not
accessible by the external programs. It is loaded, incremented and cleared like the other registers.
3. Computer Instructions formats
Computer Instructions are classified into three types, based on the Mode bit and Op-code field. Those are;
1)Memory Reference: As their name implies, memory reference instructions are those that
reference memory. Some read data from memory, others write data to memory, and one
instruction does both. For these instructions, the most significant bit is the indirect bit. If
this bit is 1, the instruction must use indirect memory addressing. That is, the address given
is not the address of the operand. It is the address of a memory location which contains the
address of the operand.
The next three bits are the OPR field, or operation field. These three bits may take
on any value except for 111; that is reserved for other instructions. The OPR field tells the
CPU which instruction is to be performed.

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Finally, the 12 low order bits contain the memory address to be used by this
instruction (or in the case of indirection the address of a memory location which contains
the address to be used by this instruction).

2)Register Reference: Register reference instructions are those which access data and
manipulate the contents of registers. They do not access memory. These instructions are
executed in one clock cycle.
Note that the 12 low-order bits serve a different function depending on the
instruction format used.

3)I/O Instructions: This class of instructions accesses I/O devices. The instructions in this
class also enable and disable interrupts. Since this computer only allows for a single input
device and a single output device, no address information is needed.

4. Instruction Cycle
In Basic Computer, a machine instruction is executed in the following cycle:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
After an instruction is executed, the cycle starts again at step 1, for the next instruction.
Note: Every different processor has its own (different) instruction cycle.

Fig: Hardware Circuit for Fetch phase.

Determine the Instruction:

After decoding phase, we are finding which type of instruction is it? This can be shown in
diagrammatically as shown below:
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 UNIT -III
UNIT-II COMPUTER ORGANIZATION

Fig: Determine the Instruction

If we show the clock pulses for finding the Effective Address (EA), then it can be as

Memory Reference Instruction:

The AND instruction performs a bit-wise logical AND.

The ADD instruction performs a regular addition.
The LDA and STA are regular load and store instructions.
The BUN (branch unconditional) is a jump instruction.
The BSA is used to call subroutines in the Basic Computer.
The ISZ instruction is used for program loops. Note the semicolon in this instruction. It
means that the first part is performed, then the second part is performed in the following
clock cycle.
Later in this module, we will examine exactly how each of these instructions is
implemented on the Basic Computer.

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UNIT -III
UNIT-II COMPUTER ORGANIZATION

LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1

Register Reference Instruction:

Each register reference instruction is performed in a single clock cycle. Each instruction
manipulates the contents of a register within the CPU, so the relatively time consuming accesses
to memory are avoided. There are 12 register reference instructions overall, each of which is
encoded by one of the 12 low order bits of the instruction code.

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UNIT -III
UNIT-II COMPUTER ORGANIZATION

I/O Instruction and Interrupt:

The input/output instructions, like the register reference instructions, are performed in a
single clock cycle. Note that there are no instructions to set FGI or FGO to 1. These flags are set
by external hardware when input data is ready or output data is requested. When the CPU
performs the proper input or output instruction (INP or OUT), it resets the flag to allow for future
I/O data transfers.

Possible I/O Instructions are specified below

Open communication only when some data has to be passed. When it getting an interrupt,
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer, it
generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to
the service routine to process the data transfer, and then returns to the task it was performing.
The T signals occur in sequence and are never skipped over. The only two options during a
T-state are to proceed to the next T-state or to return to T state 0.
The D signals decode the instruction and are used to select the correct execute routine.
I is used to select the indirect routine and also to select the correct execute routine for non-
memory reference instructions.
R is used for interrupt processing flip-flop.

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UNIT -III
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- The interrupt cycle is a HW implementation of a branch and save return address operation.
- At the beginning of the next instruction cycle, the instruction that is read from memory is in
address 1.
- At memory address 1, the programmer must store a branch instruction that sends the control to
an interrupt service routine
- The instruction that returns the control to the original program is "indirect BUN 0".

The fetch and decode phases of the instruction cycle must be modified Replace T0, T1,
T2 with R'T0, R'T1, R'T2
The interrupt cycle:
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0.

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