0% found this document useful (0 votes)
23 views

Lecture1 Chapter3 - Introduction To Map Method, Function Simplification Using Three and Four-Variable Map

The document provides an overview of gate-level minimization using Karnaugh maps. It discusses 3-variable and 4-variable Karnaugh maps and includes examples of minimizing Boolean functions with 3 and 4 variables using the map method. The key aspects covered are plotting minterms on the map, identifying adjacent minterms that can be combined to simplify the function, and writing the minimized expression as a sum of products. Examples demonstrate identifying patterns on the map and combining minterms to obtain simplified logic expressions.

Uploaded by

kingmc.chohan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
23 views

Lecture1 Chapter3 - Introduction To Map Method, Function Simplification Using Three and Four-Variable Map

The document provides an overview of gate-level minimization using Karnaugh maps. It discusses 3-variable and 4-variable Karnaugh maps and includes examples of minimizing Boolean functions with 3 and 4 variables using the map method. The key aspects covered are plotting minterms on the map, identifying adjacent minterms that can be combined to simplify the function, and writing the minimized expression as a sum of products. Examples demonstrate identifying patterns on the map and combining minterms to obtain simplified logic expressions.

Uploaded by

kingmc.chohan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 31

Chapter3: Gate-Level Minimization

Lecture1- Three and Four-Variables Function


Simplification using Map Method
Engr. Arshad Nazir, Asst Prof
Dept of Electrical Engineering
SEECS
EE-223 Digital Logic Design Spring 2024 1
EE-223 Digital Logic Design Spring 2024 2
Chapter Contents
Karnaugh Maps
SOP and POS Simplifications
Don’t Care Conditions
NAND and NOR Implementations
Parity Generation and Detection

EE-223 Digital Logic Design Spring 2024 3


Objectives
• Introduction to Map Method
• Plot and Labeling of minterms on Map
• Functions Simplification in Sum-of-Products (SOP) form
using Three and Four-Variables Map

EE-223 Digital Logic Design Spring 2024 4


K-Map Method
• The Karnaugh Map (K-Map) method uses a simple procedure for minimizing Boolean
functions.
➢ The map is a diagram made up of squares with each square representing one
minterm of the function.
➢ The key is to learn to identify visual patterns.
➢ The result is always an expression that is in one of the two standard forms, SOP or
POS.
➢ Much faster and more efficient than previous minimization techniques with Boolean
algebra. It can be used to simplify functions of up to six variables.
➢ It is possible to find two or more expressions that satisfy the minimization criteria.
➢ Rules to consider
o Every cell containing a 1 must be included at least once.
o The largest possible “power of 2 rectangle” must be enclosed.
o The 1’s must be enclosed in the smallest possible number of rectangles.
EE-223 Digital Logic Design Spring 2024 5
Two-Variable Map

• A two-variable map holds four


minterms for two variables.
➢ We mark the squares of the
minterms that belong to a given
function.
➢ Combine adjacent squares to find
minimal expression.
Three-Variable Map
• A three-variable map holds eight minterms for three variables.
➢ Again, we mark the squares of the minterms that belong to a given function.
➢ Note that the sequence is arranged in Gray code to allow only one bit to change
from column to column and row to row.
• Since any two adjacent cells in a 3-variable map represent a change in only a single
bit, we use this to do minimization.
➢ Consider the two cells for m0 and m1 where the difference is the negation of the
bit z.
➢ F = m0 + m1 = x′y′z′ + x′y′z = x′y′(z′ + z) = x′y′

EE-223 Digital Logic Design Spring 2024 7


Minimization Example
• Each of the two adjacent pairs of entries can be simplified by eliminating the
changing bit (z in both cases).
➢ F (x,y,z) = x′y′ + xy

EE-223 Digital Logic Design Spring 2024 8


Notes on Adjacency
• So far, we have assumed that adjacent cells in the map need to touch each
other but this is not always the case.
➢ m0 and m2 are considered adjacent
o m0 + m2 = x′y′z′ + x′yz′ = x′z′(y′ + y) = x′z′
➢ m4 and m6 are considered adjacent
o m4 + m6 = xy′z′ + xyz′ = xz′(y′ + y) = xz′

EE-223 Digital Logic Design Spring 2024 9


3-Variable Map Patterns
• The number of adjacent squares that may be combined always represent
a number that is a power of 2 such as 1, 2, 4, and 8.
➢ One square represents one minterm with three literals.
➢ Two adjacent squares represents a term of two literals.
➢ Four adjacent squares represents a term of one literal.
➢ Eight adjacent squares represents the entire map and produces a
function that is always equal to 1.

EE-223 Digital Logic Design Spring 2024 10


Mapping Functions Example
• Given the function
➢ F = x′z + xy′ + xy′z + yz
F = ∑(1, 3, 4, 5, 7)
• Map the function
• Determine the sum of minterms equation
• Determine the minimum sum of products expression

1 1
1 1 1

• The minimum sum-of-Products (SOP) is


F= = z + xy′
EE-223 Digital Logic Design Spring 2024 11
Example 3-1
Simplify the Boolean function F(x,y,z)=
∑(2,3,4,5) using map method
Solution:
• 1 is marked in each minterm that
represents the function
• Find the possible adjacent squares and
mark them with rectangles
• The upper right rectangle represents the
area enclosed closed by x′y (eliminating
the changing bit)
• Similarly lower left rectangle represents
xy′
• The logical sum of these two terms gives:
F = x'y + xy'
EE-223 Digital Logic Design Spring 2024 12
Example 3-2
Simply the function F(x,y,z) = ∑(3,4,6,7)
Solution:
• 1 is marked in each minterm that
represents the function
• Find the possible adjacent squares
and mark them with rectangles
• Two adjacent squares are combined
in the third column to give a two-
literal term yz
• The remaining two squares with 1’s
are enclosed in half rectangles. This
gives two-literal term xz′
• The logical sum of these two terms
gives: F = yz + xz′
EE-223 Digital Logic Design Spring 2024 13
Example 3-3
Simply the function F(x,y,z) =∑ S(0,2,4,5,6)
Solution:
• 1 is marked in each minterm that represents
the function
• Find the possible adjacent squares and mark
them with rectangles
• We combine four adjacent squares to get a
single literal term z’ as m0+m2+m4+m6
x'y'z'+x'yz'+xy'z'+xyz′= x'z'(y'+y) +xz'(y'+y)
= x'z' + xz′ = z'
• The remaining two squares with 1’s are
enclosed by a rectangle (with one square that
is already used once). This gives two-literal
term xy′
• The logical sum of these two terms gives:
EE-223 Digital Logic Design Spring 2024 14
F = z′ + xy′
Example 3-4
Simplify F = A'C + A'B + AB'C + BC
Solution:
• The two squares corresponding to the first
term A′C. (A′ first row and C two middle
columns)
• A′B has 1’s in squares 011 and 010 in the
same way. AB′C has 1 square 101 and BC
has two 1’s in squares 011 and 111
• The function has total of 5 minterms as
shown in figure
• Find the possible adjacent squares and
mark them with rectangles as shown in
the map
• It can be simplified with only two terms
giving: F = C + A′B
EE-223 Digital Logic Design Spring 2024 15
Four-Variable Map
• A four-variable map holds 16
minterms for four variables.
➢ Again, we mark the squares
of the minterms that belong
to a given function.
➢ Note that the sequence is
not arranged in a binary
way.
➢ The sequence used is a Gray
code and allows only one
bit to change from column
to column and row to row.
4-Variable Map Patterns
• The number of adjacent squares that may be combined always represent a
number that is a power of 2 such as 1, 2, 4, 8, and 16.
➢ One square represents one minterm with four literals.
➢ Two adjacent squares represents a term of three literals.
➢ Four adjacent squares represents a term of two literals.
➢ Eight adjacent squares represents a term of one literal.
➢ Sixteen adjacent squares represents the entire map and produces a
function that is always equal to 1.

EE-223 Digital Logic Design Spring 2024 17


Minimization Example

• The eight adjacent squares can be combined to form the one literal term y.
• Four adjacent squares can be combined by folding property to form the two
literal term wz′.
• The simplified expression will be logical sum of two product terms
producing the function
F = y+wz′

EE-223 Digital Logic Design Spring 2024 18


Another Example

• Four adjacent corners can be combined to form the two literal term x′z′.
• Four adjacent squares can be combined to form the two literal term x′y.
• The remaining 1 is combined with a single adjacent 1 to obtain the three
literal term w′y′z′.
F = x′z′ + x′y + w′y′z′

EE-223 Digital Logic Design Spring 2024 19


Another Example
Simplify the function F=ABC +ACD +ABC+AB CD +ABC +AB C using map
method

CD
00 01 11 10
AB
00 0 0 0 1
01 1 1 0 1
11 1 1 1 1 F=BC +CD + AC+ AD 
10 1 0 1 1

EE-223 Digital Logic Design Spring 2024 20


Another Example
Simplify the function F(A,B,C,D) =∑m(0,3,5,8,9,10,11,12,13,14,15)
F = C + A’BD + B’D’

A 1111
0111
1 0 0 1

0 1 0 0
D
C
1 1 1 1 D
A
C 1000
1 1 1 1 0000 B
B

Solution set can be considered as a coordinate


System!

EE-223 Digital Logic Design Spring 2024 21


Another Example
Magnitude Comparator

A A A
0 0 0 0 1 0 0 0 0 1 1 1

1 0 0 0 0 1 0 0 0 0 1 1
D D D
1 1 0 1 0 0 1 0 0 0 0 0
C C C
1 1 0 0 0 0 0 1 0 0 1 0
B B B

K-map for LT K-map for EQ K-map for GT

LT = A' B' D + A' C + B' C D


EQ = A'B'C'D' + A'BC'D + ABCD + AB'CD’
GT = B C' D' + A C' + A B D'

EE-223 Digital Logic Design Spring 2024 22


Example 3-5
F(w,x,y,z) = S(0,1,2,4,5,6,8,9,12,13,14)
Solution:
• 1 is marked in each minterm that
represents the function
• Find the possible adjacent squares
and mark them with rectangles
• We combine eight adjacent squares to
get a single literal term y′
• The top two 1’s on the right are
combined with the top two 1’s on the
left to give the term w′z′
• We combine the single square left on
right with three adjecent squares that
are already used to give the term xz′
• The logical sum of these three terms
gives:
F = y′ + w′z′+xz′

EE-223 Digital Logic Design Spring 2024 23


Example 3-6
F = A′B′C′+B′CD′+A′BCD′+AB′C′
Solution:
• Each of three literal term in map is
represented by two squares and four
literal term in map is represented by
one square
• We combine the 1’s in the four corners
to give the term B′D′
• The two left hand 1’s in the top row
are combined with two 1’s in the
bottom row to give the term B′C′
• The remaining 1’s may be combined in
the two-square area to give the term
A′CD′
• The logical sum of these three terms
gives:
F = B′D′ + B′C′+ A′CD′

EE-223 Digital Logic Design Spring 2024 24


Prime Implicants Definitions

EE-223 Digital Logic Design Spring 2024 26


Example of Prime Implicants

EE-223 Digital Logic Design Spring 2024 28


Essential Prime Implicants

Essential Prime Implicants:


BD, AC, B′C
Distinguished 1-cells: m2, m5, m14
Other Prime Implicants:
CD
F=BD+AC+B′C

EE-223 Digital Logic Design Spring 2024 29


Functions with Multiple Solutions
Example: Find all the possible solutions of the following function
using map method:-
F(A,B,C,D)=∑(0,2,3,5,7,8,9,10,11,13,15)

EE-223 Digital Logic Design Spring 2024 30


Functions with Multiple Solutions Cont…
• All PIs: BD, B՛D՛,CD, B՛C, AD, AB՛
• EPIs: BD, B՛D՛
• All possible solutions are:-
F=BD+B՛D՛+CD+AD
F=BD+B՛D՛+CD+AB՛
F=BD+B՛D՛+B՛C+AD
F=BD+B՛D՛+B՛C+AB՛
OR
F= BD+B՛D՛+[(CD+AD) or (CD+AB՛) or (B՛C+AD) or (B՛C+AB՛)]

EE-223 Digital Logic Design Spring 2024 31


Algorithm for determining
minimum SOP using a K-map

EE-223 Digital Logic Design Spring 2024 32


The End

EE-223 Digital Logic Design Spring 2024 33

You might also like