Departures from Ideal operational amplifier Behaviour

¾ Input bias and voltage offsets

Input bias current

The inputs of an op amp do actually draw current and this can be represented as a 2
current sources Ib+ and Ib-. These bias currents range from ~ 100nA for bipolar
amplifiers to ~ 10pA for fet and CMOS input amplifiers, therefore, the rule that there is
no current flowing in the inputs doesn’t hold, but for this analysis we assume that the
second rule holds i.e. there is sufficient loop gain to drive the voltage at the positive
terminal, V+ equal to the voltage at the negative terminal, V-

Now , V + = − Ib+ R3 -------1

Vin − V− Vout − V−
Applying the second rule + = Ib−
R1 R2

Vout V V V
Therefore = Ib− + − + − − in ---------2
R2 R2 R1 R1

Now V+ = V- and substituting V- with V+ from equation 1 into equation 2

R2 R R
Vout = − Vin + I os ( R2 − R3 − 2 3 )
R1 R1
Where the underlined part is due to the bias current, Ios, current flowing in the external
resistors and thus causes a voltage offset. To minimize the offset we set this to 0

R2 R3 RR
So R2 − R3 − = 0 and after rearranging this equation R3 = 1 2
R1 R1 + R2
So we can say that to minimize the contribution of the input bias current the resistance
to ground on the inverting terminal should equal the parallel combination of the input and

1
feedback resistances. In reality the –ve and +ve biases may not balance and more
importantly this current has temperature coefficient which will cause further offset as the
temperature changes.

Input offset voltage

The input offset voltage, Vos, is defined as the input voltage applied between the input
and non-inverting terminals to bring the output to zero at a specific temperature.
Standard bipolar amplifiers and cmos amplifiers can have offsets of ~10mV, however,
some precision bipolar amplifiers can be trimed during manufacture to only ~tens of uV.
Below we analyse the effect on inverting and non-inverting amplifiers.

For an inverting stage

We assume that the offset voltage due to the bias current offset has been taken out by
make R3 = R1//R2

A current, Iin, is drawn from the input voltage, Vin, to this stage and Eos represents the
offset voltage to bring the output to zero in open loop or in balance in closed loop.

Vin − V− V − V−
I in = , I f = out where If is the feedback current flowing in R2
R1 R2
Put V- = -Eos and making Iin = If then

R2
Vout = − (Vin + E os ) − E os
R1
Thus the offset voltage is amplified by the gain set by the external resistors. Since it is
fixed the effect of this offset at low gain is proportionately worse.

2
For a non-inverting stage

The offset voltage Eos is again referred to the input terminals.

E os = V+ − V−
∴V− = Vin − E os

R1
Now V- also = = Vout
R1 + R2

Substituting for V- we have

R2
Vout = (1 + )[Vin − E os ]
R1

As before the offset voltage is amplified by the closed loop gain. For dc signals this can
represent a significant problem.

Temperature represents the largest source of drift, both in active and passive components
within monolithic circuits furthermore slopes of bias current and offset voltage verses
temperature are not linear. So in any design the drift caused by the maximum expected
excursion of temperature must be determined and components of the circuit adjusted to
fall within the specification. If large temperature stable gains are required then there 2
solutions that might be considered : first convert your signals into AC and make stage
gains ac coupled ( can you think of how to do this with the non-inverting amplifier ?) or
second use a chopper stabilised amplifier where offsets have been nulled such as the
Intersil ICL7620 ( http://www.intersil.com/data/fn/fn2920.pdf. )

3
Differential Amplifier and common mode rejection ratio

Differential amplifiers are used to measure small voltages riding on much larger,
common-mode, voltages. To accurately sense this voltage the external resistors must be
matched. How does this match effect this measurement ?

The common mode rejection ration, CMRR , is defined

Differential _ Gain A
CMRR = 20 log10 = diff
Common − mod e _ gain Acm

R2
For the circuit above Adiff = and if R1=R2, and R3=R4, the common mode gain
R1
would be 0 and the CMRR would ∞ , In reality, however, we can’t get perfect match –
so lets look at what happens when the resistors are matched to within specified limits.

Put V1= V and V2= V+Vsense. Vo is the output voltage of the differential amplifier.
From ideal operational amplifier analysis

R2 R1 R4
V1 + Vo = V2
R1 + R2 R1 + R2 R3 + R4

R1 R4 R2
Vo = V2 − V1
R1 + R2 R3 + R4 R1 + R2

4
 1 ⎡ R4 ( R1 + R2 ) ⎤
Vo = ⎢V2 − V1R2 ⎥
R1 ⎣ R3 + R4 ⎦

Now reassigning the voltages

R1 + R2 R4 R + R2 R4 R
Vo = ( ) Vsense + V ( 1 ) −V 2
R3 + R4 R1 R3 + R4 R1 R1

R1 + R2 R4 ⎛ R + R2 R4 R 2 ⎞
Vo = Vsense + V ⎜⎜ 1 − ⎟⎟
R3 + R4 R1 ⎝ R3 + R4 R1 R1 ⎠

R2
For ideal case Vo = Vsense
R1

So by equivalence

R1 + R2 R4
The differential gain Adiff =
R3 + R4 R1

R1 + R2 R4 R2
And the common mode gain Acm = −
R3 + R4 R1 R1

If you don’t match R2/R1 to R4/R3 then Acm ≠ 0 and CMRR < ∞

Now, as an example, set Rsense = 10m Ω and Imax = 10A ∴ Vsense = 100mV at Imax.
Also R1=R2=R3=R4 = 100k Ω ± 0.1% and the common mode voltage switches between
0V and 300V.

At the extreme end of resistance tolerance if we have R3 = 99.9k Ω and R1,R2, R4 = 100
k Ω . Then Adiff = 1.0005 and Acm = 5 X 10 = 4 making the CMRR = 66dB

So for the given conditions when

Which means the circuit cannot measure the differential voltage accurately because
CMRR is too low and common mode voltage error dominates the output. So what
CMRR would be required. As an example, put the acceptable common mode error as 1%

desired _ output 0.01 − 0.1

5
If the differential gain is set to 1 then the required CMRR

= 110dB
This is tough specification, and even with 0.02% resistors only 80dB CMRR would be
achieved, however one might take 2 approaches

1. Purchase more expensive opamp - say AD629 or INA114