DXT Plug-In Unit Descriptions: Mbif-C, Mbif-Cr

Nokia
DXT Plug-in Unit Descriptions
MBIF-C, MBIF-CR
DN02176011
Issue 1-2
MBIF-C, MBIF-CR
The information in this document applies solely to the hardware/software product (“Product”) specified
herein, and only as specified herein. Reference to “Nokia” later in this document shall mean the respective
company within Nokia Group of Companies with whom you have entered into the Agreement (as defined
below).
This document is intended for use by Nokia's customers (“You”) only, and it may not be used except for the
purposes defined in the agreement between You and Nokia (“Agreement”) under which this document is
distributed. No part of this document may be used, copied, reproduced, modified or transmitted in any form
or means without the prior written permission of Nokia. If You have not entered into an Agreement
applicable to the Product, or if that Agreement has expired or has been terminated, You may not use this
document in any manner and You are obliged to return it to Nokia and destroy or delete any copies thereof.
The document has been prepared to be used by professional and properly trained personnel, and You
assume full responsibility when using it. Nokia welcomes your comments as part of the process of
continuous development and improvement of the documentation.
This document and its contents are provided as a convenience to You. Any information or statements
concerning the suitability, capacity, fitness for purpose or performance of the Product are given solely on
an “as is” and “as available” basis in this document, and Nokia reserves the right to change any such
information and statements without notice. Nokia has made all reasonable efforts to ensure that the
content of this document is adequate and free of material errors and omissions, and Nokia will correct
errors that You identify in this document. Nokia's total liability for any errors in the document is strictly
limited to the correction of such error(s). Nokia does not warrant that the use of the software in the Product
will be uninterrupted or error-free.
NO WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO
ANY WARRANTY OF AVAILABILITY, ACCURACY, RELIABILITY, TITLE, NON-INFRINGEMENT,
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, IS MADE IN RELATION TO THE
CONTENT OF THIS DOCUMENT. IN NO EVENT WILL NOKIA BE LIABLE FOR ANY DAMAGES,
INCLUDING BUT NOT LIMITED TO SPECIAL, DIRECT, INDIRECT, INCIDENTAL OR CONSEQUENTIAL
OR ANY LOSSES, SUCH AS BUT NOT LIMITED TO LOSS OF PROFIT, REVENUE, BUSINESS
INTERRUPTION, BUSINESS OPPORTUNITY OR DATA THAT MAY ARISE FROM THE USE OF THIS
DOCUMENT OR THE INFORMATION IN IT, EVEN IN THE CASE OF ERRORS IN OR OMISSIONS
FROM THIS DOCUMENT OR ITS CONTENT.
This document is Nokia proprietary and confidential information, which may not be distributed or disclosed
to any third parties without the prior written consent of Nokia.
Nokia is a registered trademark of Nokia Corporation. Other product names mentioned in this document
may be trademarks of their respective owners.
Copyright © 2016 Nokia. All rights reserved.
f Important Notice on Product Safety

This product may present safety risks due to laser, electricity, heat, and other sources of danger.
Only trained and qualified personnel may install, operate, maintain or otherwise handle this
product and only after having carefully read the safety information applicable to this product.
The safety information is provided in the Safety Information section in the “Legal, Safety and
Environmental Information” part of this document or documentation set.
Nokia is continually striving to reduce the adverse environmental effects of its products and services. We
would like to encourage you as our customers and users to join us in working towards a cleaner, safer
environment. Please recycle product packaging and follow the recommendations for power use and proper
disposal of our products and their components.
If you should have questions regarding our Environmental Policy or any of the environmental services we
offer, please contact us at Nokia for any additional information.
2 © 2016 Nokia DN02176011 Issue: 1-2

MBIF-C, MBIF-CR
Table of Contents
This document has 53 pages
Summary of changes .................................................................... 6
1 MBIF-C/-CR overview.................................................................... 7
2 Capacity and performance of MBIF-C/-CR.................................. 10
3 Structure of MBIF-C/-CR.............................................................. 11
3.1 Mechanical structure of MBIF-C/-CR............................................11
3.2 Logical structure of MBIF-C/-CR.................................................. 11
3.3 Operating principles of MBIF-C/-CR............................................ 21
3.4 Interfaces of MBIF-C/-CR.............................................................23
3.4.1 MBIF-C/-CR interfaces................................................................. 23
3.4.1.1 MBIF-C/-CR interface with clock equipment................................ 28
3.4.1.2 MBIF-C/-CR, interface with microcomputer unit...........................29
3.4.1.3 Message Bus interface.................................................................42
3.4.1.4 MBIF-C/-CR, other interfaces.......................................................44
3.4.2 Settings of MBIF-C/-CR............................................................... 45
4 Operation of MBIF-C/-CR.............................................................46
5 Power consumption of MBIF-C/-CR.............................................47
6 MBIF-C C74990, MBIF-CR C104965...........................................48
7 Connector maps of MBIF-C/-CR.................................................. 50
DN02176011 Issue: 1-2 © 2016 Nokia 3

MBIF-C, MBIF-CR
List of Figures
Figure 1 Operating environment of MBIF-C/-CR in microcomputer units........... 8
Figure 2 Segmented Message Bus. An MBRP and one MBIF-C in each rack
has been integrated to MBIF-CR..........................................................8
Figure 3 Implementation principle of Message Bus segment and Repeater Bus
for a single segment............................................................................. 9
Figure 4 Block diagram of the MBIF-C/-CR...................................................... 12
Figure 5 Message Bus receiver........................................................................ 13
Figure 6 Message Bus transmitter.................................................................... 15
Figure 7 Message Bus and Repeater interfaces.............................................. 19
Figure 8 Interfaces of the MBIF-C.................................................................... 24
Figure 9 Interfaces of the MBIF-CR..................................................................25
Figure 10 An asymmetrical current-controlled interface..................................... 28
Figure 11 Timing of the 8M and 8K basic timing signal...................................... 29
Figure 12 Interface of the MBIF-C with the Message Bus.................................. 44
Figure 13 Interfaces of the MBIF-CR with the Message Bus and Repeater Bus....
44
Figure 14 Front panel of MBIF-C/-CR.................................................................46
Figure 15 W6 switch, LED indicators and backplane connectors of MBIF-C and
MBIF-CR.............................................................................................48
4 © 2016 Nokia DN02176011 Issue: 1-2

MBIF-C, MBIF-CR
List of Tables
Table 1 Timing of unit requesting reservation..................................................18
Table 2 Timing of free message bus segment's swapping period...................20
Table 3 Interface signals of the MBIF-C/-CR...................................................25
Table 4 I/O Read operations of the MBIF-C/-CR.............................................29
Table 5 Structure of address and command word...........................................34
Table 6 Selection of command message type.................................................35
Table 7 Structure of command messages.......................................................35
Table 8 I/O Write operations of MBIF-C/-CR plug-in units.............................. 36
Table 9 The principle of operation of the receive program.............................. 40
Table 10 Fill-up level of the receive-FIFO......................................................... 42
Table 11 Use of MB interface signals................................................................43
Table 12 Power Consumption of MBIF-C/-CR.................................................. 47
Table 13 Interchangeability code settings of MBIF-C/-CR (W6)........................48
DN02176011 Issue: 1-2 © 2016 Nokia 5

Summary of changes MBIF-C, MBIF-CR
Summary of changes
Changes between document issues are cumulative. Therefore, the latest document
issue contains all changes made to previous issues.
Changes between issues 1-2 and 1-1
Table 13 corrected.
Changes between Issues 1-1 and 1-0
Figure in Section MBIF-C C74990, MBIF-CR C104965 updated.
Issue 1-0
First issue.
6 © 2016 Nokia DN02176011 Issue: 1-2

MBIF-C, MBIF-CR MBIF-C/-CR overview
1 MBIF-C/-CR overview
Main functions of MBIF-C and MBIF-CR
The Message Bus Interface (MBIF-C) acts as a bi-directional interface between a
microcomputer unit and a 16 bit parallel Message Bus (MB). The MBIF-C independently
controls the Message Bus (MB): all arbitration, request and release functions of the MB
have been decentralised to all MBIF-C plug-in units connected to the MB. The MBIF-CR
includes the same functionality as the MBIF-C, in addition to which it also provides the
repeater function. The MBIF-C/-CR plug-in unit also has built-in hardware and bus
diagnostics.
g Note: In this documentation, MBIF-C/-CR is used to refer to both MBIF-C and MBIF-
CR, as the basic functionality is the same in both plug-in units. MBIF-CR is used only
when repeater-specific information is presented.
When the CPU of the microcomputer unit writes a message to the MBIF-C/-CR, the
compressing logic of the plug-in unit compresses it simultaneously and moves it to the
transmit-FIFO. The transmit command reserves the Message Bus (MB) and sends the
message to the MB without any control from the CPU. The MBIF-C/-CR of the receiving
microcomputer unit receives and uncompresss the message under the control of its own
logic and gives an interrupt to the CPU for the incoming message. The MBIF-C/-CR can
receive messages at four different addresses, two of which are group addresses and can
be chosen as desired with the software.
The MBIF-C/-CR plug-in unit is an interface between the microcomputer and the
message bus segment. It is used in M98 mechanics, having the same basic functions as
the MBIF-B plug-in unit. The repeater function of the MBIF-CR connects the message
bus (MB) segments to the repeater bus (RB). The repeater bus connects MB segments
to form the full length message bus. The task of the MBIF-CR repeater function is to split
the message bus into several blocks so that signal quality is improved and higher
transmission rates can be used.
Operating environment of MBIF-C/-CR
The MBIF-C/-CR is connected to the CPU of the microcomputer unit via the PCI bus and
to the MBIF-C/-CR plug-in units of the other microcomputer units in the exchange via the
MB. The MBIF-C/-CR plug-in units receive their basic timing signals from the Clock
Equipment (CLO).
The figure below illustrates the operating environment of the MBIF-C/-CR plug-in unit in
the microcomputer units.
DN02176011 Issue: 1-2 © 2016 Nokia 7

MBIF-C/-CR overview MBIF-C, MBIF-CR
Figure 1 Operating environment of MBIF-C/-CR in microcomputer units.
REPEATERFUNCTION
BLOCK(RPB)ONLY IN
MESSAGEBUS(MB)
MBIF-CR
OPERATION CGS
AND _INT0
MAINTENANCE ALARMTEST
MBLOAD
UNIT (OMU)
MBAL MBIF-C(R) MSGCOUNT CPU
CLOCK _INT1
EQUIPMENT 8M0,8K0
(CLS) 8M1,8K1
PCIBUS
DN0128737
The figure below shows the connection principle of the microcomputer units to the
duplicated Message Bus (MB) whose total length is approximately 150 m. Both MBs are
normally in use (active) simultaneously. One MB is chosen with the software as the
active bus along which all call control messages are sent to make sure that their order is
retained at the receive end. The other bus can be used to send e.g. various loading
messages. If either MB becomes faulty, the entire load is transferred to the intact MB. No
hardware-based changeover signal is associated with the selection of the MB in the
MBIF-C/-CR plug-in units.
Figure 2 Segmented Message Bus. An MBRP and one MBIF-C in each rack has
been integrated to MBIF-CR.
REPEATERBUS
M MBRP M M
MBIF-CR MBIF-CR
B MBIF-C B B
MBIF-CR
MBIF-C S S MBIF-C S
E MBIF-C E E
MBIF-C G G MBIF-C G
MBIF-C
Cabinet0 Cabinet1 CabinetN

DN03310917
The following figure illustrates the implementation of a message and repeater bus in a
single segment.
8 © 2016 Nokia DN02176011 Issue: 1-2

MBIF-C, MBIF-CR MBIF-C/-CR overview
Figure 3 Implementation principle of Message Bus segment and Repeater Bus for a
single segment.
RearView
RepeaterBus0 RepeaterBus0
RepeaterBus1 RepeaterBus1
1A-1L
1N-1X
2A-2L
MB0
MB1
DN03310905
DN02176011 Issue: 1-2 © 2016 Nokia 9

Capacity and performance of MBIF-C/-CR MBIF-C, MBIF-CR
2 Capacity and performance of MBIF-C/-CR

• Data is hardware compressed.
• Arbitration frequency: 2,048 MHz.
• Transfer frequency: 33 MHz.
• Repeater function MBRP (included in MBIF-CR).
• Built-in HW and bus diagnostics.
• The cabinet arbitration can be selected (3 bits for 8 cabinets, 4 bits for 16 cabinets).
10 © 2016 Nokia DN02176011 Issue: 1-2

MBIF-C, MBIF-CR Structure of MBIF-C/-CR
3 Structure of MBIF-C/-CR
3.1 Mechanical structure of MBIF-C/-CR

The MBIF-C/-CR plug-in unit is constructed on a double-Euro-size printed circuit board
(height 233 mm, depth 220 mm), which has ten layers. The ground is in the surface
layers, and the front panel is also grounded. The ground levels of the MBIF-C/-CR are
connected to each other at the edge of the board.
The MBIF-C/-CR is connected to the motherboard of the cartridge via four five-row
connectors. The connector types are as follows:
• two 25-pin A-type female connectors, J1 and J4

• 19-pin B-type female connector, J3
• 22-pin B-type female connector, J5.
The connectors are numbered from J5 to J1 (from top to bottom).

Message Bus signals are connected to two points at the back plane connector thus
enabling cabling one below the other. Signals are brought to the MBIF-C through one
single point; the MBIF-CR has an additional PIN connector for the Repeater Bus at the
back plane.
3.2 Logical structure of MBIF-C/-CR

The logical structure of the MBIF-C/-CR is as follows:
• PCI bus interface

• Control logic
• Timing logic
• Receiver
• Transmitter
• Arbiter.
DN02176011 Issue: 1-2 © 2016 Nokia 11

Structure of MBIF-C/-CR MBIF-C, MBIF-CR
Figure 4 Block diagram of the MBIF-C/-CR.
PACKED
MAE
MAC
PCIBUS
INTERFACE D31:0 RECEIVER
_INT1 MD15...MD0,MDP
MWR
MESSAGEBUS(MB)
MWR
PCIBUS
MD15...MD0,MDP
TRANS-
MITTER MAC
MAE
_INT0 CONTROL PACKED
LOGIC
MRE,MRE2
ARBITER MSY
8M TIMING
8K
LOGIC
CGS
DN0128749
Generating of timing
The timing of the MBIF-C/-CR plug-in unit is generated by multiplying the 8.192 MHz
basic timing signal by four in a phase lock circuit. The resulting 32 MHz clock signal is
divided to obtain the arbitration frequency (2.048 MHz) and the transmission frequencies
chosen with settings.
The timing of all MBIF-C/-CR plug-in units in the exchange is synchronized to the same
phase with the 8 kHz and 8 MHz basic timing signal. The reserving and releasing of the
Message Bus, the incrementation and synchronization of the arbitration counters and the
entire sending and receiving of the command message take place fully synchronously in
all MBIF plug-in units of the exchange under the sole control of the timing signals with
the same nominal phase formed from the basic timing signals.
The writing of the messages into the receive-FIFO is asynchronous directly under the
control of the write signal sent at the same time as the transmit data.
The basic timing signals are supervised by examining the state of the carry output of a
four-bit synchronous counter incremented with the 8.192 MHz basic timing signal at 125
µs intervals. If the carry output of the counter is not in state 1 at the rising edge of the 8
kHz basic timing signal, or if the frequency of the 8 kHz signal is too low, a clock alarm is
activated.
Message Bus receiver
At the hardware level, the Message Bus receiver of the MBIF-C/-CR uncompresses
automatically messages compressed by the transmitter and saves the uncompressed
message into the FIFO from which the CPU interface can read the messages. The
receiver consists of the following parts:
• Message bus
• Control logic of the receiver
• Receive-FIFO
• Control and uncompressing logic
12 © 2016 Nokia DN02176011 Issue: 1-2

• Read-FIFOs
• (PCI interface).
Figure 5 Message Bus receiver.
Read
FIFO
0
MB
interface
Decompression
andcontrollogic
Receiver Read
Receive
controland FIFO
FIFO
paritylogic CRCcheckand 1
readlogic
PCI
interface
The control logic recognizes the addresses of the unit in the message (unit and group
addresses) and the type of the message (normal message or a command). In addition,
the control logic does the parity count. If a parity-error is detected in a word, receiving is
discontinued at once and the remaining part of the message is not written in the receive-
FIFO. A faulty message is recognized by its length: it is not long enough. If the control
logic recognizes the address designated to the unit, it performs the following:
• It forms the command pulses needed, if the received message is a command. A

command message can be received only at unit address, and it is never written into
a receive-FIFO. The control logic of the receiving must also control both sending and
receiving of the state and acknowledgement byte.
• It controls the writing of the message into receive-FIFO. It also controls MAE error-
acknowledgement signal of the Message Bus and the MAC acknowledgement
signal. Similarly, it controls respective status bits. If receive-FIFO becomes full while
receiving of the message is still in progress, receiving is discontinued immediately,
and it can continue only after receiving a new message when the FIFO is not full
anymore. The control logic of the receiver writes also a start indication bit for a new
message into the FIFO. Parity bit is not written in the receive-FIFO.
The Receive-FIFO is 32 kilobytes and it is organized as follows: 18 x 16k (including data,

PACKED bit and the start indication bit of the new message).
The uncompressing algorithm of a message is the following:
1. The uncompressing algorithm waits in idle state until it notices that the receive-FIFO
is not empty, and it has received a permission from the control logic to start
uncompressing the message.
DN02176011 Issue: 1-2 © 2016 Nokia 13

2. The uncompressing algorithm reads a word from the receive-FIFO and checks from
the PACKED signal, whether it is compressed. At the same time, the counter of the
uncompressing logic is reset. Had the word not been compressed, the
uncompressing logic writes the word into a read-FIFO number 0 or 1, pointed by the
control logic, and step 2 is repeated. Had the word been compressed, the
uncompressing algorithm moves to step 3.
3. The uncompressing logic writes the compressed word into read-FIFO 0 or 1 pointed
by the control logic, and increments its counter (by one). The counter is then
compared to the number of compressed words received from the upper byte of the
compressed word. If the values were equal, the logics return to step 2. If the values
were different, step 3 will be repeated.
The Control logic controls the writing of messages into the read-FIFOs assisted by
uncompressing logic.
After reseting, the control logic remains idle waiting for a message to arrive into the
receive-FIFO. When it notices that the receive-FIFO is not empty anymore, it gives the
uncompressing logic a command to start uncompressing the message. The first
message is always written into read-FIFO 0. While the uncompressing logic reads
receive-FIFO, the control logic looks for the start indication bit of a new message. When
the control logic notices the beginning of a new message and the uncompressing logic
has completed uncompressing of the previous word, the control logic starts writing into
read- FIFO 1 and, at the same time, gives an interrupt concerning the message waiting
in read-FIFO 0. After read-FIFO 1 has been written into, the following message will be
written into read-FIFO 0.
If receive-FIFO empties while receiving is in progress, the uncompressing logic will
remain waiting for the following word, and continues then in normal manner when there
is data in the FIFO again. If a receive-FIFO becomes empty and receiving is not in
progress anymore, the uncompressing logic will be reset, and the following message will
be written into the other FIFO.
The Control logic prevents the uncompressing of the messages when neither of the
read-FIFOs is not empty and the start indication bit following message is noticed. After
this, the uncompressing of the messages can start again when either of the FIFOs is
empty.
When a read-FIFO has been read empty, the control logic allows the writing of a new
message into it. In such case, the read-FIFO cannot be read again before the other FIFO
has been read first. This is to prevent the corruption of the message being written (see
Receiving of messages in Operating principles of MBIF-C/-CR).
The MBIF-C/-CR gives an interrupt only if the whole message has been received into
either read-FIFO, and an interrupt is given for each message. A new receiving interrupt
is given whenever the previous interrupt has been acknowledged and receiving interrupt
is allowed, and there is data in both read-FIFOs or there is data in the other read-FIFO
and the receive-FIFO is empty and receiving is not in progress.
The uncompressing and control logic writes a word (16 bits) into the read-FIFO at every
rising edge of the 66 MHz clock signal when there is data in the receive-FIFO and/or
uncompressing logic has not uncompressed the last word.
Read-FIFOs contain thus only one (uncompressed) message at a time. Therefore, their
size is the same as that of the write-FIFO, in other words, 32 x 2k. To optimize the PCI
interface, the read-FIFOs are 32-bit wide. Because they are written at the width f a word,
14 © 2016 Nokia DN02176011 Issue: 1-2

it must be possible to control the writing into them word for word. This can be achieved
with a signal which activates the writing signal of the upper and lower word in turns while
writing is in progress.
CRC-sum is calculated for every message read from read-FIFO. The CRC counter is
initialized by a read command of the first word. CRC-sum is not written to read-FIFO with
message, it is kept in register inside FPGA. CRC-error sets status bit but it has no other
impact on hardware. Checking the CRC-error (status bit) requires software support.
The uncompressing logic and read-FIFOs are reset with the same signal as the receive-
FIFO.
Control- and uncompressing logics are implemented by the FPGA circuit.
Message Bus transmitter
On hardware level, the Message Bus transmitter compresses messages automatically.
The Message Bus transmitter consists of the following (see also the figure below):
• (PCI interface)
• Write-FIFO
• Compressing logic and parity count
• Transmit-FIFO
• Interface circuits of the Message Bus
• Transmit logic and CRC-check.
Figure 6 Message Bus transmitter.
PCI MB
interface interface
WriteFIFO, Transmit
Compression Transmit and
logic FIFO parity
andCRC logic
calculator
The master CPU writes messages via the PCI interface into write-FIFO. The write-FIFO
is integrated within the FPGA circuit and is three double words deep.
The CRC logic calculates a 16-bit CRC checksum of the message being written. A 16-bit
checksum is calculated from a 32-bit data by performing a XOR-operation to the bits next
to each other and by calculating the needed checksum from the resulting 16-bit word.
Transmit/Send command returns the CRC counter into initial state.
Compressing logic reads the 32-bit write-FIFO. It calculates parity (over 16 bits) from the
compressed data and saves the compressed part of the message and parity bit into
transmit-FIFO. The compressing algorithm is as follows:
DN02176011 Issue: 1-2 © 2016 Nokia 15

1. The compressing algorithm remains in idle state until it notices that the write-FIFO is
not empty anymore. It moves to step 2.
2. Read the double word (32 bits) from the FIFO.
3. Compare bytes within the word. If the bytes are not equal, write two words (2 x 16-bit
addressing) with their parities into transmit-FIFO and return to step 1. Store also the
info that the word is not compressed (PACKED-signal) into the transmit-FIFO. If, on
the other hand, the bytes are equal, proceed to step 4.
4. Initialize value 2 into compressing counter.
5. Read the following double word and compare the bytes to the bytes read in step 3. If
the bytes are not the same or if the value of the compressing counter is FFH, write
the compressed part into the 16-bit transmit-FIFO in the following manner: save the
recurrent byte into the lower byte and the value of the compressing counter (how
many words the byte concerned recurs) into the upper counter together with parity
and compressing information. Return to step 3 and use as data the word you have
read last. If the bytes were the same, proceed to step 6.
6. Increment the compressing counter by one and return to step 5.
When the message is read from the transmit-FIFO the parity is calculated over 17 bits
over data and compressing information signal so that the receiver will be able to identify
faulty compressing information.
The compressing algorithm is implemented with a programmable logic so that the
compressing speed is 30 ns (33 MHz clock frequency) per double word. In other words,
the compressing logic can also function at the full speed of the PCI bus. Because the
transmit-FIFO is a 16-bit device, it must be written with a 66 MHz clock signal. This
signal is formed by the phase-locked loop from the backend clock signal of the PCI
connection.
The compressing algorithm is activated whenever the write-FIFO is not empty. If the
write-FIFO is emptied while the compressing logic as at step 5 and the part of the
message that has been compressed but has not been written into the transmit-FIFO, the
logic remains in idle state waiting for new data in the write-FIFO. Thus, the transmit logic
has to give a transmit command to the compressing logic, after which the compressing
logic writes, if need be, the last word into the transmit-FIFO and returns to initial state. In
addition, the compressing logic always finishes off by reading the CRC-sum and saving it
with its parity to the transmit-FIFO unless the message to be transmitted is a command.
The transmit logic decodes the send command from the master CPU and activates
transmitting as soon as the write-FIFO is empty (compressing is completed).
Command messages are handled with the compressing logic in a normal way because
they cannot be compressed.
The transmit-FIFO's size is 8 kilobytes. Its memory is 18 x 4k (including data,
compressing information and parity).
Transmit logic, CRC-calculation, compressing logic, parity count and write-FIFO are
implemented with a FPGA circuit. Write-FIFO (FPGA's internal) is written by using a
signal coming from the 33 MHz PCI bus. The transmit-FIFO is written by using a 66 MHz
clock signal that has been formed by the phase-locked loop from the 33 MHz clock
signal mentioned above.
The CRC-check requires support from the MBDRIV driver program.
Message Bus arbiter
16 © 2016 Nokia DN02176011 Issue: 1-2

The arbitration algorithm developed for the MBIF-C/-CR improves the performance of the
plug-in unit from that of the MBIF-A when the load factor of the Message Bus (MB) is
relatively low and one or more microcomputer units are waiting for transmission turn.
With the MBIF-C/-CR, the MB arbiter is integrated into the FPGA circuit and only the
2.048 MHz arbitration frequency is available. This means that the arbitration cycle lasts
488 ns.
The MBIF-C/-CR plug-in units of the active side of the duplicated microcomputer unit
which always belongs to the standard equipping of the exchange feed the
synchronization signal MSY to themselves and to all other microcomputer units on the
MB. The MSY signal loads the same initial value to the counters of all arbiters at the
beginning of every arbitration round.
The principle of operation of the new arbitration system is as follows:
• The Message Bus (MB) is divided into eight (16, if four bits is used) groups
(message bus segments) according to the addresses set by the MBRP. Each group
includes always microcomputer units included in the same cabinet (segment). The
first group includes the microcomputer units of the first cabinet (cabinet address 0),
the second group the microcomputers of the second cabinet etc. The arbitration
counter typically has only three bits, that is eight steps. If none of the microcomputer
units waits for transmission turn, one entire arbitration round is 8 × 488 ns = 3.904
µs. If a configuration has more than eight cabinets 4 bit address can be taken into
use with the _CA3EN signal (through the back plane connector).
• When the arbiter is incremented to a group, every microcomputer unit in the group
waiting for transmission turn stops the arbitration with the MRE2 signal. In addition,
each unit in the group controls the bus data bit that corresponds to the D7, D6, D1
AND D0 (UA) signals of their MB address for 180 ns. For example, address 40H
controls MB data bit MD4, and address 04H controls data bit MD0. Each unit
inspects which data bits are active, after which the microcomputer units that control
the lowest data bit have the right to set the data bits corresponding to the four middle
address bits (D5…D2) as active data bit MD1 for address 04H). The unit waiting for
request sets the data bit it controls into state 1 and the unit not waiting for request
sets the bit into state 0. MD signals need only be controlled for 180 ns, since all units
possibly requesting transmission are in the same cabinet and all units can identify
the reservation signal in this time.
• The microcomputer unit that has set the lowest data bit active starts transmitting by
activating the MRE signal. In addition to the unit transmitting a message, the other
units in the group waiting for transmission also hold the MRE2 signal active.
• Once the microcomputer unit has transmitted the entire message, it deactivates MRE
and MRE2 signals and sets the data bits into high impedance state. The deactivation
of the MRE signal is an indication for the other units in the group waiting for their turn
that the next unit in the queue can reserve the bus. This operation takes place within
the next two arbitration cycles. During the first arbitration cycle, all units notice the
bus being free. During the second cycle, they run the data line corresponding to their
address into state they wish (reserve request, that is state 1 or tristate). After these
two cycles, the unit that has activated the lowermost data line starts transmitting.
When even the last unit in the group has sent a message, it deactivates both MRE
and MRE2 signal, after which arbitration counters step forward as usual. In other
words, the arbiter steps whenever the MRE2 signal is passive.
• Only the 2,048 MHz arbitration frequency is available for the MBIF-C/-CR, and thus
the arbitration cycle lasts 488 ns. The termination resistors keep the signals in
deactive state. During the request cycle the timing of the MBIF-C/-CR follows the
values listed in the table below, provided that the microcomputer unit wishes to
DN02176011 Issue: 1-2 © 2016 Nokia 17

reserve the message bus and the arbitration counter receives cabinet addresses. If
the unit does not wish to reserve the message bus, it naturally does not control any
signal.
Table 1 Timing of unit requesting reservation.
Time (ns) Action
0 MRE signal activated.

MDx data bit selected with MB addresses D7, D6, D1 and D0 (UA) set as active.
Once the MBRP notices that the MRE2 signal has been activated, it sets cabinet
address bits MD15…MD12 first to 0 state and then to a state of high impedance.
152,5 Data bits read. Bit MDx set to high impedance.
183 Data bit MDx set to zero.
244 MDx is set to high impedance.
274,5 MDx data bit selected with MB addresses D7, D6, D1 and D0 (UA) set as active. The
microcomputer unit controls the data bit at this stage only if it notices that it has set a
data bit of higher priority status (MD0 highest, MD11 lowest) at the start of the
request cycle.
427 Data bits read. Bit MDx is set to high impedance.
457,5 The winner activates MRE, MRE2 is read, and the arbitration logic stops the
artbitration counter.
518,5 The first word of the message is transmitted to the message bus (30,5 ns after the
start of the arbitration cycle).
• Since the arbitration counter compares cabinet addresses instead of unit addresses,
restrictions for address use in the MBIF-B no longer apply. The equipment enables
any address for a unit within the scope of 00H…BFH. The addresses C0H…FFH are
not available as unit addresses, since these addresses would drive the data bits
MD15…12 at the start of the request cycle and would thus collide with the cabinet
address driven by the MBRP. However, these addresses are available as group
addresses. Cabinet addresses can be read from the MBIF-C status register. The
reservation is directed at the start by with bits D7 and D6, in order to avoid the
aforementioned collision with MBRP (D7 and D6 can not have the status 1 for any
unit). D1 and D0 distribute effectively units in the same cabinet, as one and the same
cabinet often has several sequential addresses.
• If a microcomputer unit requires transmitting turn when the MRE2-signal is active, it
cannot take the turn before the MRE2-signal has been released and the arbiter has
been incremented, even if the group the unit belongs to had a transmission turn. This
is to secure all transmitting groups transmitting turn in due time.
• In estimating the power handling capacity of the terminator resistor. It has to be taken
into account that more than one unit at a time may drive the MRE2 signal.
The arbiter is implemented with an FPGA circuit.

Message Bus repeater
18 © 2016 Nokia DN02176011 Issue: 1-2

The MBIF-CR plug-in unit contains an asynchronic repeater function, the task of which is
to repeat message bus signals that it receives to the opposite segment. In other words, it
repeats messages received from the Repeater Bus (RB) to the Message Bus (MB), and
messages from the RB to the MB. The task of the repeater is to ensure the quality of
signals on a long segment and high transfer frequency.
In addition to bus interfaces, the repeater also includes a control logic, which sets the
interfaces into the desired states in the following way:
Figure 7 Message Bus and Repeater interfaces.
MD15...MD0 MD15...MD0
MBS_MDP RB_MDP
MBS_MRE RB_MRE
MBS_MRE2 RB_MRE2
MESSAGEBUSSEGMENT MBIF-C/-CR REPEATERBUS
MBS_MWR RB_MWR
MBS_MAC RB_MAC
MBS_MAE RB_MAE
MBS_MSY RB_MSY
MBS_PACKED RB_PACKED
DN03310929
The connection direction is recognized from the arbiter counter and cabinet address
during the arbitration cycle. When the arbiter counter corresponds to its own cabinet
address, the transmission direction is from the segment to the Repeater Bus (RB). If the
arbiter counter does not correspond to its own cabinet address, it is possibly the turn of
some other segment to transmit and the connection direction is from the RB to the
segment.
Due to the fault monitor of segments, the signal connection directions are graded during
the arbitration cycle.
Due to transit time delays, address signals driven to the MB segment and fault control
signals all transmit and receive segments are connected separately to the FPGA. The
Data, MWR, PACKED and MDP signals are controlled with the internal logic of the FPGA
depending on the situation at hand. The entry points of the signals are always active,
and only the output ports are controlled when necessary. The repeater function also has
to recognize the message type (the MD8 state of the data bit at the start of the message
transmission).
When the repeater notices a command message it has to change its direction in the
middle of transmitting the message so that the status and receipt bits can be sent from
the receiver to its sender. In other words, the repeater connected to the MB of the sender
of the command message activates its RB connection whereas the repeater of the MB of
the receiver closes its MB connection for data signals and activates its RB connection.
The segment that has received the command message is recognized by the MAC receipt
signal received from it. Sending the command signal takes three arbitration cycles, and
the status and receipt bits are transmitted during the last arbitration cycle. In this case
the change of direction of the repeater has to be timed in the following manner:
• Command message is recognized during the first arbitration cycle.

• The repeater connected to the MB of the sender of a message has to change
direction before the repeater of the receiver.
• Both repeaters have to change direction during the second arbitration cycle (MAC is
also activated during this cycle).
• The change of direction has to be cancelled when the MRE signal (from the segment
or from the RB) is deactivated.
DN02176011 Issue: 1-2 © 2016 Nokia 19

• To prevent simultaneous running of the RB, the deactivation of the MRE signal has to
set RB signals to a state of high impedance.
The above is applicable also when the transmitter and receiver of a command message
are both in the same segment.
The data signals MD12…15 function in the direction of the MB segment differently from
other data signals, as the repeater sets a cabinet address for these when the bus is in
deactivated state. Thus, MD12…15 are active towards the segment when the bus is in
deactive state while the cabinet address delivered from the back connector is directed to
them. When the bus is activated from either direction, cabinet addresses are set first in
state 1 and, approximately 50 ns later, to a state of high impedance. Data bits remain in
state of high impedance if the reservation has come from the MB, and they are
reactivated if the reservation comes from the RB. A cabinet address can be directed to
the segment whenever the MRE2 signal is in deactive state.
Fault control of the MB segment is implemented during the arbitration cycle. Each MBIF-
CR whose arbiter does not correspond to its own cabinet address sets the data bits
MD0…MD11 into state 1 at the start of an arbitration cycle. After 457,5 ns from the
beginning of the arbitration cycle each MBIF-C in the cabinet reads the data bits. Data
bits MD0…MD11 should be '1' for all MBIF-Cs. If this is not the case, the MBIF-C that
noticed the error sets the fault control status register bit D2 and implements an interrupt.
The precise functioning and timing are displayed in table 1 below. Interrupt is edge
sensitive, and a new interrupt occurs only once the previous one has been
acknowledged and the status register bit is off.
Table 2 Timing of free message bus segment's swapping period.
Time (ns)
0 Arbiter counter and cabinet address values different.

MBIF-CR directs cabinet address bits CA0…CA3 of the back connector to MB
MD12…MD15. MD0…MD11 bits set to state 1. MRE and MRE2 directed from the RB
to the MB. MAC and MAE directed from the MB to the RB.
457,5 If MRE2 is active, RD0…RD15, MDP, PACKED and MWR are connected from the RB
to the MB.
The units read the bites MD0...MD11.
Data signals are set into deactive state whenever it is noticed that the MRE signal
(MRE_MB or MRE_RB signals) is in deactive state. Data signals are run for 80…150 ns,
after which they are directed into state of high impedance.
The sender of the synchronization signal MSY is always the same unit that synchronizes
the bus. This unit remains constant practically all the time. The unit can change only due
to a change of sides in the synchronizing unit, but the back-up units must belong to the
same MB segment. In this case the MSY signal scan be connected directly from the
receiver of the MB connector to the RB transmitter, and vice versa. The transmit ports
are closed in initial state. The transmitter of the RB is opened with rising edge of the
MSY signal coming from the MB, and vice versa. Activation of the other transmitter is
prevented simultaneously with opening the transmitter, that is, the MSY signal coming
from the MB prevents the activation of the MB transmitter. Once the transmitter has been
20 © 2016 Nokia DN02176011 Issue: 1-2

activated or closed, it remains in the same state until the unit is zeroed with the reset
signal. In this case the transmitters are reset in both directions in tristate, waiting for the
new synchronization signal. The entry ports of the MSY signal are always active.
The entry ports of the MAC and MAE signals are always active. As with MRE signals, the
signal data of output ports are constantly active (in state 0). The output ports of the MAC
and MAE signals are controlled with the MRE signal and the received MAC and MAE
signals. The output ports can be activated only in the direction from which the MRE
signals have been received. In other words, the MAC and MAE signals can only be
active towards the RB if the MRE signal has been received from the RB direction, and
towards the MB if the MRE signal has been received from the MB direction. This is
because only the sender of a message can read its receipt signals. However, output
ports are opened only if a MAC or MAE signal is received from the opposite segment
than the MRE signal. Output ports controlling the signals are kept active for as long as
the MAC and MAE signals are active. In other words, the deactivation of the MRE signal
does not close the output ports.
The repeater is always functional, even if the MBIF-CR is separated from the bus.
3.3 Operating principles of MBIF-C/-CR

Timing of operation and internal signals
The timing of the MB interface of the MBIF-C/-CR is formed with a phase lock circuit by
multiplying the 8 MHz basic timing signal obtained from the Clock Equipment by four.
The output signals 32M, _16MHz and 8MHz of the phase lock circuit are mutually exactly
in the same phase.
The arbitration frequency of the MB is always 2.048 MHz.
The operation of the phase lock circuit is supervised by comparing the phase difference
between the 8MHz signal of the phase lock circuit and the _8M signal formed directly
from the basic timing signals.
Enabling the MSY signal of the Message Bus
Only one MBIF-C/-CR connected to the Message Bus (MB) is allowed to control the
synchronization signal MSY of the transmission turn counter of the MB. In normal
operation, the MSY signal is controlled by the active Marker (M).
The operation of synchronization signal MSY is enabled in only two cases:
• the SYNC0 signal is in state 0 and the CGS signal is in state 0

• the SYNC1 signal is in state 0 and the CGS signal is in state 1.
Message Bus arbiter
The Message Bus arbiter is integrated into the FGPA circuit.
When the state of the arbitration counter corresponds with that of the MB segment, all
units in the segment can request the bus.
The time supervision of approx. 25 ms of the MB request is implemented in FPGA.
If no MBIF-C/-CR of the MB controls the MSY signal in a failure condition, the bias
resistors on the bus direct the signal into passive state. When the arbitration counters of
all MBIF-C/-CR plug-in units on the MB have been once synchronized correctly, they will
remain synchronized even without the MSY signal if no interference occurs in the basic
DN02176011 Issue: 1-2 © 2016 Nokia 21

timing signals. If the arbitration counter in one MBIF-C/-CR has been incorrectly
synchronized, its transmission turn may overlap with the transmission turn of another
MBIF-C/-CR. This will lead to an error condition only when both MBIF-C/-CRs are
attempting to send a message at the same time.
Sending of messages
The 16–bit words of the message to be sent, the PACKED information is written into the
transmit-FIFO with a memory addressing, which prevents the activation of the interrupt
signal during the writing into the FIFO.
When the message in the transmit-FIFO is written to MB, the transmit logic releases
MRE and drives receive signal to zero for a period of three clock cycles.
Sending of command messages
When sending command messages, the sender deactivates the line transmitter circuits
corresponding to the low byte after the address word has been sent. After one arbitration
cycle, the recipient of the command message activates the line transmitter circuits
corresponding to the low byte for the transmission of the status and acknowledgement
byte. The received status and acknowledgement byte is written at the end of the
command message cycle of FPGA. The MB is reserved for command messages for
three arbitration cycles.
Receiving of messages
The low byte of the received address word is compared with the wired address, with the
programmed group addresses and with the selected 7EH or 7FH general group address
by the FPGA circuit IC26. If one of the four comparators identifies the address, the
receiving of the message begins. The parity of all words to be received are checked.
All the write signals of receive-FIFO circuits are formed by the FPGA circuit from the
MWR signal of the Message Bus.
If a parity error is detected in connection with any byte in the rest of the message, writing
to receive-FIFO is prevented. If acknowledgements are enabled, the enable signal
controlling the MAC signal of the MB is deactivated and the enable signal controlling the
MAE signal of the MB is activated.
Receiving of command messages
All received command messages are decoded by decoding logic which identifies the
different command message types. For a reset command message, output pin 5 of the
monostable multivibrator controlling the _RSTOUT signal is triggered into state 1 for a
duration of approx. 400 µs.
Generating clock alarm
Supervision of basic clock signals is implemented in FPGA. 10 bit counter circuit is
clocked by inverted 8 MHz clock. The counter is always loaded with value 0 when 8 KHz
signal is in state 1. If counter is not 3FF hex when 8 kHz pulse arives or counter reaches
3FF hex and there is no 8 kHz pulse a alarm is given.
When the basic timing signals contain imterference, _ICLOCKALARM signal is set to 0
for approx. 50 ms. When zero, _ICLOCKALARM sets MBAL signal also to zero. MBAL
signal can be made active also by activating the ALTST signal into state 1.
If the alarm is continuous , the _ICLOCKALARM signal will remain continuously in state
0.
22 © 2016 Nokia DN02176011 Issue: 1-2

The operation of all line transceiver circuits of the MB interface is disabled for 0.5 us if
clock interference occurs.
PCI bus interface
The MBIF-C/-CR is connected to the master computer via a PCI bus. The connection
uses DMA burst transmission between the central memory of the CPU and the receive-
FIFO of the MBIF-C/-CR. Other operations to be applied to the MBIF-C/-CRs (writing
commands and reading status registers) are single addressings. The CPU takes care of
initialising the DMA controller on the MBIF-C/-CR by writing to it the transmission start
address in the central memory, the length of the block to be transmitted and the
transmission direction (from the memory to the transmit-FIFO or from the read-FIFO to
the memory). Subsequently, the CPU starts the DMA controller, which transmits
independently the data as a burst. During the DMA transmission, the MBIF-C/-CR
operates as PCI bus master. When the DMA controller has performed the transmission,
it gives an interrupt to the CPU, after which it can be initialised to perform a new
transmission. The DMA transmission is always performed until the end, even if a receive
error is detected while reading the receive-FIFO. The error is identified from error bits
D17, D21 and D22 of the receive status register.
3.4 Interfaces of MBIF-C/-CR

3.4.1 MBIF-C/-CR interfaces
The figures below shows the external interfaces of the MBIF-C/-CR plug-in unit and the
following table describes the interface signals.
DN02176011 Issue: 1-2 © 2016 Nokia 23

Figure 8 Interfaces of the MBIF-C

3.3V
AD[31::00] +5V
POWERSUPPLY
GND
C/_BE[3::0] -5V
PAR
_FRAME TRMCCL SUPERVISIONOF
+5VT TERMINAL UNIT
_TRDY
_IRDY
MBS_MD15...
_STOP MBS_MD0
PCIINTERFACE
_DEVSEL MBS_MDP
_IDSEL MBS_MRE
_PERR MBS_MRE2 MESSAGEBUS
_SERR MBS_MWR SEGMENT
_REQ MBS_MAC
_GNT MBS_MAE
MBS_MSY
CLK
MBS_PACKED
_RST
MBIF-C
AL OPERATION AND
CLOCKEQUIPMENT 8M ALTEST MAINTENANCE
(CLO) 8K
_CA3EN
SETTINGOF UA7...UA0 REPEATER
MESSAGEBUS CA3...CA0 _REPEN FUNCTION
ANDCABINET "0" "0" ENABLE
ADDRESSES "1"
_INT0
SELECTIONOFMB'S CGS
_INT1
SYNCHRONIZATION SYNC0
MSGCOUNT CPU
SYNC1 MBLOAD
_RSTOUT
TDI
TDO
JTAG
TCK
INTERFACE
TMS
DN03493938 _TRST
24 © 2016 Nokia DN02176011 Issue: 1-2

Figure 9 Interfaces of the MBIF-CR

3.3V
AD[31::00] +5V
POWERSUPPLY
GND
C/_BE[3::0] -5V
PAR
_FRAME TRMCCL SUPERVISIONOF
+5VT TERMINAL UNIT
_TRDY
_IRDY
MBS_MD15...
_STOP MBS_MD0
PCIINTERFACE
_DEVSEL MBS_MDP
_IDSEL MBS_MRE
_PERR MBS_MRE2 MESSAGEBUS
_SERR MBS_MWR SEGMENT
_REQ MBS_MAC
_GNT MBS_MAE
MBS_MSY
CLK
MBS_PACKED
_RST
RB_MD15...
RB_MD0
RB_MDP
RB_MRE
RB_MRE2
RB_MWR REPEATERBUS
MBIF-CR RB_MAC
RB_MAE
RB_MSY
RB_PACKED
AL OPERATION AND
CLOCKEQUIPMENT 8M ALTEST MAINTENANCE
(CLO) 8K
_CA3EN
SETTINGOF UA7...UA0 REPEATER
MESSAGEBUS CA3...CA0 _REPEN FUNCTION
ANDCABINET "0" "0" ENABLE
ADDRESSES "1"
_INT0
SELECTIONOFMB'S CGS
_INT1
SYNCHRONIZATION SYNC0
MSGCOUNT CPU
SYNC1 MBLOAD
_RSTOUT
TDI
TDO
JTAG
TCK
INTERFACE
TMS
DN03493926 _TRST
Table 3 Interface signals of the MBIF-C/-CR.
Signal Description
AD[31:0] PCI bus address and data
C/_BE[3:0] Byte selection and command signals
PAR Parity bit
_FRAME Accessing activation signal
_TRDY Accessing target ready
DN02176011 Issue: 1-2 © 2016 Nokia 25

Table 3 Interface signals of the MBIF-C/-CR. (Cont.)
Signal Description
_IRDY Accessing initiator ready
_STOP Accessing interrupt signal
_DEVSEL Target address identification signal
_IDSEL Selection signal used in the configuration
_PERR Parity error signal
_SERR System error signal
_REQ Bus request signal
_GNT Request allocation signal
CLK Bus clock
_RST Initial reset signal
3.3V 3.3 V operating voltage
+5V +5 V operating voltage
-5V -5 V operating voltage
GND Ground
TRMCCL Supervision of presence of terminator unit
+5VT Bias voltage backing up the terminator unit
MBS_MD15…MD0 Data and parity signals of the MB
MBS_MDP Data and parity signal of the MB
MBS_MRE Reserve signal of the MB
MBS_MRE2 Request signal of next transmission turn
MBS_MWR Transmission clock signal of MB
MBS_MAC Positive acknowledgement signal of MB
MBS_MAE Negative acknowledgement signal of MB
MBS_MSY Synchronization signal for arbitration counter
26 © 2016 Nokia DN02176011 Issue: 1-2

Signal Description
MBS_PACKED Signal indicating that the word is compressed
RB_MD15…MD0 Data signals of the RB
RB_MDP Parity signal of the RB
RB_MRE Reserve signal of the RB
RB_MRE2 Request signal of next transmission turn
RB_MWR Transmission clock signal of RB
RB_MAC Positive acknowledgement signal of MB
RB_MAE Negative acknowledgement signal of MB
RB_MSY Synchronization signal for arbitration counter
RB_PACKED Signal indicating that compressed data is included in the word to

be transmitted
AL Clock alarm signal
ALTST Clock alarm test signal for supervision
_INT0 Interrupt signal of the MBIF-C/-CR plug-in unit
_INT1 Interrupt signal of the PCI interface's DMA controller
MSGCOUNT Measurement signal for number of messages on the MB
MBLOAD Load measurement signal of the MB
_RSTOUT Activation signal of the initial reset request coming from the
Message Bus as command message
TDI JTAG interface signal
TDO JTAG interface signal
TCK JTAG interface signal
TMS JTAG interface signal
_TRST JTAG interface signal
CGS Changeover signal of GSW
DN02176011 Issue: 1-2 © 2016 Nokia 27

Signal Description
SYNC0 Enable signal for synchronization signal of MB (MSY)
SYNC1 Enable signal for synchronization signal of MB (MSY)
_CA3EN Enabling of 4-bit cabinet address
UA7…UA0 Setting of wired MB address
CA3...CA0 Setting of wired cabinet address.
"0" State 0, directly from 0 V ground level
"1" State 1 via a 562 Ω resistor connected to +5 V
8M 8.192 MHz basic timing signals
8K 8 kHz basic timing signals
The PCI bus interface signals of the MBIF-C/-CR meets the PCI specification. The
interface signals with the Clock Equipment use asymmetrical current-controlled
interfaces, whereas MB signals comply with the MLVDS stantard. All other interfaces are
TTL or CMOS level. The figure below shows the principle of an asymmetrical current-
controlled interface.
Figure 10 An asymmetrical current-controlled interface.

MLVDS-A
TRM TRM
MLVDS-B
TTL TTL
3.4.1.1 MBIF-C/-CR interface with clock equipment
The MBIF-C/-CR receives the necessary external basic timing signals 8M and 8K from
the Clock Equipment. The figure below shows the timing of the signals.
28 © 2016 Nokia DN02176011 Issue: 1-2

Figure 11 Timing of the 8M and 8K basic timing signal.
8M
8k
DN9987087
A pull-up resistor (10k) is added to the A-signal of the input counters to prevent noise in
case of blockout.
3.4.1.2 MBIF-C/-CR, interface with microcomputer unit

PCI bus interface
The MBIF-C/-CR plug-in unit is connected to the master computer via the CompactPCI
bus. With the MBIF-C/-CR, all mandatory signals for the bus master are implemented:
AD31.. AD0, C/_BE3…C/_BE0, PAR, _FRAME, _TRDY, _IRDY, _STOP, _DEVSEL,
IDSEL, _PERR, _SERR, _REQ, _GNT, CLK and _RST. The MBIF-C/-CR gives the
interrupt with the external interrupt signal of the PCI bus and, consequently, the PCI
interrupts are not used.
The reading of the status registers and the writing of commands are single transactions
on the PCI bus. The reading of the receive-FIFO and the writing into the transmit-FIFO
can be carried out as burst transmission with help of the PCI interface's internal DMA
logic. The burst transmission can be implemented with full speed (transmission on each
edge of the PCI clock).
An initial reset pulse given with a command message via the MBIF-C/-CR activates the
_RSTOUT signal for a minimum duration of 400 µs.
The base address of the MBIF-C/-CR is chosen with the software by writing the desired
address into the configuration registers of the PCI interface. In addition to the normal
registers used by the PCI interface, the interface implements four DMA controller
registers (base address registers, configuration register and status register) at the
addresses 128H, 12CH, 130H and 138H.
Read operations
The read-FIFO of the MBIF-C/-CR plug-in unit is in the memory space. The other read
commands are in the I/O space. The first word of a message is read from a different
address than the remaining part of the message, that is, the first word is read from
address 80000H, and the remaining part of the message from address 00000H onwards.
Otherwise the memory address is not significant because the read command to a
memory (area) will always return the next double word in the read-FIFO. The read-FIFO
can be read in burst mode without wait cycles. The read I/O operations of the MBIF-C/-
CR are presented in the tables below.
Table 4 I/O Read operations of the MBIF-C/-CR.
Base address+ Signal Description
00H Enabling of message receive interrupt, reading of interrupt and

receive status register and acknowledgement of receive errors.
DN02176011 Issue: 1-2 © 2016 Nokia 29

Table 4 I/O Read operations of the MBIF-C/-CR. (Cont.)
In addition to enabling of message receive interrupt, reading this

address functions as does reading from address 10H.
04H Disabling of receive interrupt.

A new receive interrupt is always generated when the previous
interrupt has been acknowledged and receive interrupt is enabled
and there is data in both read-FIFOs or when there is data in the
other read-FIFO and the receive-FIFO is empty and the receiving of
the message is not operating.
08H D15...D0 Reading of wired MB address and speed settings.
D7...D0 Wired MB address (UA7...UA0).
D8 In state 1, if the operation of the MB is disabled due to clock

disturbance (_MBDISABLE = "0").
D9 In state 0, if an error has been detected in the timing of the MBIF-C/-

CR.
D10 In state 0, if the unit has been selected as transmitter of of the

synchronization signal.
D11 In state 0, if the bus terminator is equipped.
D12 Bias voltage (+5VT) of the bus terminal.
D13 In state 0, if the clock alarm output test signal ALARMTEST is active
(state 1).
D14 Always in state 0.
10H or 18H D31…D0 Reading of interrupt and receive status register and
acknowledgement of receive errors. The reading of the register from
address 18H does not acknowledge receive errors.
D0 In state 0, if the receive interrupt is active. An interrupt is given for

each received message.
D1 In state 0, if the previous transmission ended with an error.
D2 In state 0, if the clock alarm interrupt is active.
D3 In state 0, if message has been succesfully transmitted.
D4 In state 0, if the command message receive interrupt is active.
30 © 2016 Nokia DN02176011 Issue: 1-2

D5 In state 0, if the clock alarm is on.
D6 In state 0, either of the following has been detected: synchronization

pulse has failed to come or it has come at a wrong time.
D7 In state 0, if at least one interrupt is active.
D8 In state 0, if the MBIF-C/-CR has experienced a power outage after

the previous initialisation.
10H (18H) D9 In state 0, if the interrupts of the MBIF-C/-CR have been masked.
D10 State of changeover signal CGS.
D14...D11 States of status register signals MBST3...MBST0 of the MB.
D15 In state 1, if there is a CRC error in reading a message.
D16 Diagnostics interrupt is in active state.
D17 In state 1, if the identification bit of the first word of a message has
been erroneusly in 0 state in the read command
In the MBIF-C/-CR this means that the read command of the first
word in the message (change-over command of the read-FIFO) has
been given before the FIFO currently being read is emptied.
D18 In state 0, if the receive-FIFO is full.
D19 In state 1, if a parity error has occurred in the message transmission

on the MB.
D20 In state 1, if an attempt has been made to write into a full receive-
FIFO.
D21 In state 1, if an attempt has been made to read the receive-FIFO

without giving a command for the first word.
D22 In state 1, if an read command attempt has been made when

receive-FIFO and both read-FIFOs are empty, or a read command
has been attempted after errors indicated by bytes D17 and 21.
D24 In state 0, if the receive-FIFO is empty.
D25 In state 0, if the receive-FIFO is more than half-full.
DN02176011 Issue: 1-2 © 2016 Nokia 31

D27 In state 0, if the receive-FIFO is almost empty.
D29 In state 0, if the receive-FIFO is almost full.
D30, D31 Type identification bits

(LSB) (MSB)
0 0 MBIF-C
1 0 MBIF-CR
0CH D23...D0 Reading of the status register on the transmit side and reading of the
received status and acknowledgement byte.
D0 In state 0, if everything is ready to write the message.
D1 In state 0, if the MBIF-C/-CR has reserved the MB and the

transmission is in progress.
D2 In state 0, if the MBIF-C/-CR is separated from the MB.
D3 In state 0, if the MB is reserved.
D4 In state 0, if the message transmission was successful to at least one

unit.
D5 In state 1, if a unit has activated the error acknowledgement signal.
D6 In state 0, if the previous transmission has ended with the expiration

of the timeout of the MB request.
D8 In state 0, if the transmit-FIFO is empty.
D13 In state 0, if the transmit-FIFO is full. The _FULL signals of the

internal counter is connected to this byte. The counter counts
unpacked Dwords (8kb — 1 Dword = “FIFO FULL”).
32 © 2016 Nokia DN02176011 Issue: 1-2

D14 In state 0, if 4–byte cabinet addresses are used. In state 1, if 3–byte

cabinet addresses are used.
This byte is relevant only in a unit that takes care of bus
synchronization.
D15 In state 0, if the internal MB request signal is active.
0CH D23...D16 Status and acknowledgement byte of the MBIF-C/-CR.
D16 In state 0, if the receiving of the status and acknowledgement byte

was successful. D0 is always permanently in state 1 for the recipient
of a command message. D0 is inverted when writing the status and
acknowledgement byte.
D17 In state 1, if the recipient has detected a parity error on the MB.
D18 In state 1, if the receive-FIFO has become full.
D19 State of _RESTART signal of recipient.
D20 State of status data signal (SUPERVISORBIT) of recipient's

supervision program.
D21 State of recipient's load signal LOADRATE0.
D22 State of recipient's load signal LOADRATE1.
D23 Permanently in state 0.
0CH D24...D31 Status of the read- and write-FIFOs.
D24 In state 0, if read-FIFO0 is empty.
D25 In state 0, if read-FIFO0 is full.
D26 In state 0, if read-FIFO1 is empty.
D27 In state 0, if read-FIFO1 is full.
D28...31 Cabinet address bytes CA0...3. The MBRP runs these bytes on
Message Bus signals when the MD12...15 segments are free.
14H D31…D0 Reading the load counters of the Message Bus.
D15...D0 Contents of the Message Bus load counter. The counter counts
MBLOAD signal pulses. The counter turns around and does not have
to be initialised.
DN02176011 Issue: 1-2 © 2016 Nokia 33

D31…D16 Contents of the Message Bus message counter. The counter counts
MSGCOUNT signal pulses. The counter turns around and does not
have to be initialised.
1CH D31...D0 Diagnostics status register.
D0 In state 0, if repeater bus diagnostics has been cancelled (only in

MBIF-CR).
Always in state 1 in MBIF-C.
D1 In state 0, if error has been found in the line circuit of the repeater
(only in MBIF-CR).
Always in state 1 in MBIF-C.
D2 In state 0, if message bus diagnostics has been cancelled.
D31...D3 Always in state 1.
Write operations
A message is written into the write-FIFO. The write-FIFO is in the memory space and the
writing takes place as memory addressing. Every write is decoded as a double word
wide addressing into the write-FIFO. Compressing logic is activated whenever there is
data in the write-FIFO, and it transfers/forwards the compressed message into the
transmit-FIFO.
The total length of the message must be divisible by four. Also the receive-FIFO must
always be read in double words (the MBIF-C/-CR ignores byte selection signals of the
bus). For error conditions, an additional word (content is irrelevant) must therefore be
written into normal messages (not into command messages) after the address and
command word and only after this the message header. The reason for this is that
reading a corrupted message in the FIFO the first complete double word of the next
intact message is lost (the reading will be interrupted when the beginning of a new
message is detected too early). The part of the message getting lost must not contain
header data (e.g. length of the message).
The table below describes the structure of the address and command word to be written.
Table 5 Structure of address and command word.
Signal Description
D7...D0 MB address
D8 = 0 Normal message (not a one-word command message); D14...D9

freely available to the software
34 © 2016 Nokia DN02176011 Issue: 1-2

Table 5 Structure of address and command word. (Cont.)
Signal Description
D8 = 1 One-word command message; D14...D9 are used to choose the

command type
The table below describes the selection of the command message type (chosen with
address and command word bits D14...D9)
Table 6 Selection of command message type.
Signal Description
D9 = 0 Separation from MB
D9 = 1 Connection of MBIF-C/-CR to MB
D10 = 0 No restart; the receiver receives an interrupt form the command

message.
D10 = 1 Restart; the receiver does not receive an interrupt from the
command message.
D11 = 0 Updating of status register of MB
D11 = 1 No updating of status register of MB
D14...D12 Data to be written into status register of MB; no significance with

regard to hardware
The table below describes the structure of the command messages.
Table 7 Structure of command messages.
Command message Description
59XXH (0101 1001 xxxxxxxx) Separation of unit from MB
5BXXH (0101 1011 xxxxxxxx) Connection of unit to bus
5DXXH (0101 1101 xxxxxxxx) Restart; the MBIF-C/-CR remains

separated from the MB after the command
5FXXH (0101 1111 xxxxxxxx) Restart; the MBIF-C/-CR remains

connected to the bus after the command
DN02176011 Issue: 1-2 © 2016 Nokia 35

Table 7 Structure of command messages. (Cont.)
Command message Description
0DXXH (0000 1101 xxxxxxxx) Mere inquiry of status and

acknowledgement byte; no interrupt or
writing into status register
0xxx x0x1 xxxxxxxx Interrupt is given for command message
0xxx 0xx1 xxxxxxxx Writing into status register of MB
X = MB address
The transmit-FIFO of the MBIF-C/-CR plug-in unit is in the memory space and writing
into the memory space is done by memory addressing. Each write operation of the
memory area into the address area of the MBIF-C/-CR is decoded as double word
addressing into the transmit-FIFO. Other write commands of the MBIF-C/-CR are in the
I/O space. The MBIF-C/-CR has all the same I/O-write operations as the MBIF-A. The
reset command of the transmit-FIFO resets the write-FIFO as well as the compressing
logic. Respectively, the resetting of the receive-FIFO resets also the read-FIFOs and
release logic. The enabling of receive interrupt is also in use with I/O-write (OUT base
address + 3CH).
The table below describes the write operations of the MBIF-C/-CR plug-in units.
Table 8 I/O Write operations of MBIF-C/-CR plug-in units.
Address Signal Description
OUT 04H D31...D0 Starting the sending of a command message

(_CMDMSGSEND)
OUT 08H D31...D0 Starting the sending of a normal message

(_TRANSMIT)
OUT 10H D31...D0 Writing of group address 0 (_WRGROUPADDR0)
D7...D0 Group address
D8 = 0 Receiving disabled at group address
D8 = 1 Receiving enabled at group address
D9 = 0 Acknowledgement disabled at group address
D9 = 1 Acknowledgement enabled at group address
D31...D10 The data has no significance
36 © 2016 Nokia DN02176011 Issue: 1-2

Table 8 I/O Write operations of MBIF-C/-CR plug-in units. (Cont.)
OUT 14H D31...D0 Writing of group address 1 (_WRGROUPADDR1)

*
D31...D0 See writing of group address 0
OUT 18H D31...D0 Testing of clock alarm (_MBALTEST)
Used for testing only. Must never be used in

exchanges in operation.
OUT 1CH D31...D0 Writing of initialisations in parallel format into

control register **
16-bit word addressing must be used. The signals

are reset in all resetting operations.
D0 Not used
MBLOADEN
D1 = 0 Disabling of the outputs of the MBLOAD and

MSGCOUNT signals used to measure the load
factor of the MB
D1 = 1 Enabling the outputs of the MBLOAD and

MSGCOUNT signals
7E_7FSEL
D2 = 0 Selection of general group address 7FH
D2 = 1 Selection of general group address 7EH
ALLMSGRECEN
D3 = 0 The unit receives only the messages addressed to

it
D3 = 1 The unit receives all (normal) messages sent to

the MB. This control is needed only when testing
to monitor the messages on the MB in a micro-
computer unit specifically assigned to this
purpose.
D7...D4 Not used
Controls of outgoing status and acknowledgement

byte
DN02176011 Issue: 1-2 © 2016 Nokia 37

Table 8 I/O Write operations of MBIF-C/-CR plug-in units. (Cont.)
D8 State of _RESTART signal
D9 State of SUPERVISORBIT signal
D10 State of LOADRATE0 signal
D11 State of LOADRATE1 signal
D31...D12 Not used
OUT 20H D31...D0 Resetting of receive-FIFO circuits

(_RFIFORESET)
OUT 24H D31...D0 Acknowledgement of clock alarm (_CLALQUIT)
OUT 28H D31...D0 Separation from the MB (_SEPARATE)
OUT 2CH D31...D0 Connection to the MB (_NOSEPARATE)
OUT 30H D31...D0 Resetting of transmit-FIFO circuits, initialisation of

transmit logic in error conditions,
acknowledgement of both transmission interrupts
and disabling of interrupt for successful
transmission (_TRAERRQUIT)
OUT 34H D31...D0 Acknowledgement of interrupt generated when

receiving command messages (_CMDINTQUIT)
OUT 38H D31...D0 Enabling the interrupt for a successful

transmission (_TRAINTEN)
An interrupt is given when the request of the MB

ends. In connection with command messages, the
status and acknowledgement byte is ready for
reading as soon as the interrupt has been
received. The command can also be given when
the transmit-FIFO is empty.
OUT 3CH Enabling of message receive interrupt.
OUT 40H D31...D0 Acknowledgement of diagnostics status register

cancellation.
OUT 44H D31...D0 Resetting of read-FIFO being read.
* The receiving and acknowledgement at the group addresses is disabled in connection

with all resets.
38 © 2016 Nokia DN02176011 Issue: 1-2

** The _POWERUPRES signal is active 1.5...2 s after the +5 V operating voltage is

switched on and while the -5 V operating voltage is missing. During this time, it is not
possible to write into the control register. The state of the _POWERUPRES signal can be
read from the interrupt register.
Sending of messages
The compressing logic is invisible to the interfaces apart from a compressing information
bit sent to the message bus. To ensure the functioning of the arbitration logic, the data
bits of the message bus must be set in state 0 at the same time as the MRE-signal is
released (that is, set into tri-state) after sending a message.
The transmit-FIFOs must always be reset with the _TRAERRQUIT command after the
initial start of the unit.
Messages are sent as follows:
• The status register on the transmit side is examined to find out if everything is ready.
• The message is written into the transmit-FIFO. The total length of the message to be
transmitted must be N x 4 bytes.The transmission must be carried out in double word
mode, because the MBIF-C/-CR does not check the byte selection signals, but
presumes the addressings being always in double word mode.
• The message transmission is started with the _TRANSMIT command. The message
is written into the transmit-FIFO (previous phase) and always sent completely, also in
error conditions. The recipient detects the corrupted message and rejects it.
The transmit-FIFO must be reset after every failed message transmission. It is never
allowed to write a new message into the transmit-FIFO until the transmit-FIFO is empty.
If the message transmission fails, an interrupt is given to the CPU. The cause of the
interrupt is found out by reading the interrupt register. A transmission error interrupt must
be acknowledged with the _TRAERRQUIT command which also resets the transmit-
FIFO.
When writing into the transmit-FIFO, the parity bit of the 16-bit word is not written at the
same time. The parity bit is calculated and added to each data word during transmission
Messages can be sent only when the MBIF-C/-CR is connected to the bus. If a message
transmission is started when the MBIF-C/-CR is separated from the bus (the
_SEPARATED signal in state 0), the transmission will immediately end with a
transmission error interrupt, and the Message Bus is not reserved at all.
All line transmitters of the MBIF-C/-CR are separated from the MB for the duration of a
clock disturbance. The clock disturbance does not in any way affect the actual
_SEPARATED signal which handles the separation. When the clock disturbance ends,
the transmitters remain separated about 0.5 ms longer. Any transmission attempts made
during this time will immediately end with a transmission error interrupt. The receiving of
normal messages and their writing into the FIFO is not disabled during the clock
disturbance. The receiving of command messages is completely disabled during a clock
disturbance.
Receiving of messages
With the MBIF-C/-CR, the reading of the first word is separated from the reading of the
remaining part of the message with one bit address decoding. MBIF-C/-CR accesses 1
MB from the PCI bus, and therefore the MSB it uses is A19. The MBDRIV reads the first
word of the message from address 80000H (A19 is 1) and the remaining part of the
message (with DMA) from address 00000H (A19 is 0).
DN02176011 Issue: 1-2 © 2016 Nokia 39

The principle of operation of the receive program with regard to faultless messages is
presented below:
Table 9 The principle of operation of the receive program.
Operation Bits
Reading the first word from address 80000H. With this 32 bits
command, the receive interrupt is prevented and
acknowledged. Also, with this command, the control
logic changes the read-FIFO to be addressed.
Checking the first word. The MBDRIV copies from the 2 × 32 bits
bus header of the message the information needed
for initializing the DMA controller (the length and the
type of the message) for the first word. The DMA
controller is then initialized and activated with a
memory addressing.
Reading the remaining part of the message (bus n × 32 bits

header and the main body) as burst transmission
performed by the DMA controller.
Reading the interrupt and receive status register and 32 bits

checking and acknowledging errors.
Enabling of receive interrupts by using an I/O write

command.
Enabling of receive interrupt may also be combined
with the previous command (read from 00H) – and
this command may be omitted.
The MBDRIV must also check the CRC-error.

If the Message Bus receiver detects a parity error on the Message Bus (or the receive-
FIFO becomes full), it interrupts the receiving of the message and the message will be
shortened. Subsequently, reading the message ends in an error caused by the read-
FIFO in turn getting empty. The next message is saved in the other read-FIFO and can
be read from there.
If the information on the message length has been wrong (the message is in reality
longer), the attempt to read the first word of the next message will be made too early and
the error appears in the status register after the first word has been read. In this case,
the remaining part of the corrupted message is in the previous read-FIFO. In this case,
the controller is not allowed to change the read-FIFO to be addressed with the read
command of the first word. The remaining part of the message is read from the read-
FIFO with read command of the first word and after read operation it must be checked,
whether the beginning of a new word has been detected (in other words, the read-FIFO
is empty, and the error bit is not set anymore). Control logic can read and check CRC-
sum and set an error bit automatically if needed. The checksum is read when the upper
read-FIFO is circuit is empty but there still is data in the lower read-FIFO (checksum).
The CRC-error is acknowledged when the status register is read with a command
acknowledging errors.
40 © 2016 Nokia DN02176011 Issue: 1-2

If a parity error has been detected in the reading of the receive-FIFO, the read message
is corrupted, but the next message can be read normally.
Sending of command messages
When writing command messages, bit D8 in the recipient's address and command
message must be set into state 1. The command messages are sent with the
_CMDMSGSEND command.
A command message can be received only at the wired address of the unit. The
command messages affecting the state of the microcomputer unit must also have a
certain exact format for them to be accepted.
The error acknowledgement signal MAE is never activated when receiving command
messages, because if a parity error occurs in connection with the transmission, the
recipient will not identify its address.
The command message is never compressed because the bytes of the doubleword are
not identical. Thus the compressing algorithm does not have to individually recognize the
command message and uncompress it at the receiving end.
No CRC sum is to be calculated of the command message.
Databits are to be directed into 1-state also after sending a command message.
Interrupts
The MBIF-C/-CR units use two interrupt outputs (_INT0 and _INT1), which are
connected to the CPU interrupt inputs _INT0.._INT3. The interrupt signals are run with
the LVT circuit. The circuit is closed, when the output is actively run up (to 3 V).
The interrupt signal _INT1 is used to give the DMAREADY interrupt with which the DMA
controller announces to the CPU that it has dispatched the transmission initialised for it
and is ready to start a new transmission.
Five interrupts have been connected to the interrupt signal _INT0:
• receiving of the message interrupted

• transmission error interrupt
• clock alarm interrupt
• end of successful transmission interrupt
• command message changing the state of the unit.
When any one of the above interrupts is on, the outgoing interrupt signal is activated into
state 0. Every interrupt can be acknowledged separately.
A new receive interrupt is always activated whenever the previous interrupt has been
acknowledged and receive interupt is enabled and there is data in both read-FIFOs, or
there is data in one read-FIFO and the receive-FIFO is empty and receiving is not in
progress. This means that a receive interrupt is given separately for each message. The
interrupt is edge sensitive. In this case, there is always a complete message ready in the
receive-FIFO when the interrupt is given.
When reading the first word, the receive interrupt is deactivated and a new receive
interrupt is prevented from passing through. The receive interrupt is enabled with a
separate command or by reading from the interrupt and receive register address 00H.
Receive errors can be acknowledged in connection with the reading of the interrupt and
receive register as it is done when reading a received message (see section ). In other
cases, the interrupt register must be read without acknowledging receive errors.
DN02176011 Issue: 1-2 © 2016 Nokia 41

Monitoring the load of the Message Bus

The MBIF-C/-CR monitors the load of the Message Bus with the MBLOAD and
MSGCOUNT signals. These signals are common to both MBIF-C/-CR units of the
microcomputer unit, but only the MBIF-C/-CR connected to the MB to be measured is
allowed to control these signals. The disabling and enabling of the signals is done with
the output signal MBLOADEN of the control register of the MBIF-C/-CR.
If the MB chosen to be measured is busy, the frequency of the MBLOAD signal is 0.512
MHz regardless of the rate on the MB. The MSGCOUNT signal of the MBIF-C/-CR that
is connected to the MB to be measured goes into state 0 while the messages are
transmitted.
The fill-up level of the receive-FIFO can be monitored with the signals 'empty', 'half full',
'full', 'almost full' and 'almost empty'. The fill-up levels and the state of the status registers
of the MBIF-C/-CR are presented in the table below.
Table 10 Fill-up level of the receive-FIFO.
Bits of
the
receive
status
registe
r
D24 D26 D28 D16 D25 D27 D29 D18 Fill-up level
0 0 1 1 0 0 1 1 = 0%
1 0 1 1 0 0 1 1 0...6.25%
1 1 1 1 0 0 1 1 6.25...25%
1 1 0 1 0 0 1 1 25...43.75%
1 1 0 0 0 0 1 1 43.75...50%
1 1 0 0 1 0 1 1 50...56.25%
1 1 0 0 1 1 1 1 56.25...93.7%
1 1 0 0 1 1 0 1 93.7...100%
1 1 0 0 1 1 0 0 = 100%
3.4.1.3 Message Bus interface

Message Bus interface signals
The MBIF-C/-CR plug-in units are connected to the 24 transmission lines of the Message
Bus by multipoint-low-voltage differential (M-LVDS) line transceiver circuits
(SN65MLVD204D). The impedance of the transceiver circuit in passive state is
42 © 2016 Nokia DN02176011 Issue: 1-2

approximately 120 kohm. The maximum number of units connected to the Message Bus
is 20 units for the Message Bus segments and 10 units for the repeater bus. The line
transceiver circuits do not either cause an adverse load on the bus even if the operating
voltages are missing in the MBIF-C/-CR so the failure of the power supply of any
microcomputer unit, or its intentional switching off, will not prevent the operation of the
MB.
The table below describes the use of the MB interface signals.
Table 11 Use of MB interface signals.
Signal Use
PACKED Signal indicating that compressed data is included in the word to

be transmitted
MAC The message recipient acknowledges every word received with

acknowledgement signal MAC. This signal is in state 0, if at least
one receiver acknowledges the receiving as successful.
MAE The error acknowledgement signal MAE needed in group

transmissions is in state 0, if at least one recipient acknowledges
the message receiving as unsuccessful.
MD15...MD0 The messages are transferred by the data signals in parallel

format one word at a time. The status and acknowledgement
byte is transferred by the MD7...MD0 signals.
MDP The parity of the parity signal is even (e.g. with the 0000H data,
the state of the parity signal is 0).
MRE The message sender reserves the bus by activating the request
signal MRE into state 0 for the entire duration of the message
transmission.
MRE2 MRE2 is set active by all units that are in the same arbitration
group as the unit currently sending and that want to request the
bus.
MSY The synchronization signal MSY is used to synchronize the

arbitration counters of all MBIF-C/-CR plug-in units connected to
the bus to the same phase. Normally only one MBIF-C/-CR can
be selected to control the MSY signal. The signal is active (in
state 1) only at the beginning of the arbitration round.
MWR The transmission clock signal MWR sent at the same time as the
data to be transmitted controls the writing into the receive-FIFO.
The figures below illustrate the interface of the MBIF-C with the MB and the interfaces of
the MBIF-CR with the MB and RB. The MB is terminated at both ends with terminator
units.
DN02176011 Issue: 1-2 © 2016 Nokia 43

Figure 12 Interface of the MBIF-C with the Message Bus.
MBRP _RX_EN
RX_DATA
TX_EN
TX_DATA
MESSAGEBUS
SEGMENT
MBIF-C
DN03403653
Figure 13 Interfaces of the MBIF-CR with the Message Bus and Repeater Bus.
_RX_EN
RX_DATA
MBRP TX_EN
TX_DATA
REPEATERBUS
_RX_EN
RX_DATA
TX_EN 100R
MBIF-C TX_DATA
MESSAGEBUS
SEGMENT
DN03403665
3.4.1.4 MBIF-C/-CR, other interfaces

CGS switch over interface
The MBIF-C/-CR plug-in unit is connected to the symmetrical current-controlled CGS
changeover signal by a comparator circuit with a high input impedance. The inputs of the
circuit are equipped with 100 kΩ serial resistors. The state of the CGS signal can be
read from the status register.
The MBIF-C/-CR uses the CGS changeover signal to choose the MBIF-C/-CR which will
control the synchronization signal MSY of the MB.
Programming interface of the FPGA circuit
The MBIF-C/-CR has an FGPA circuit. It is loaded from a serial EPROM circuit which can
be programmed via test points.
Clock alarm interface
The supervision logic for the basic timing signals gives a clock alarm to the operation
management if the incoming basic timing signals to the MBIF-C/-CR contain interference
or the signals are missing altogether. The clock alarm signal MBAL of the MBIF-C/-CR is
controlled with an open-collector connection whose output is equipped with a 100 Ω
serial resistor. The voltage of the MBAL signal is approx. 0.2 V in alarm state and
otherwise approx. 5 V.
The MBAL signals of several different MBIF-C/-CR plug-in units can be connected to the
same alarm signal. The length of the clock alarm pulse given for a single disturbance is
50...60 ms. If the clock disturbance is continuous, the alarm is continuously on. The clock
alarm is cancelled 50...60 ms after the clock disturbance ends. The operation of the
clock alarm logic is disabled if the -5 V operating voltage is missing.
44 © 2016 Nokia DN02176011 Issue: 1-2

An interrupt is given to the microcomputer unit for a clock alarm generated by the MBIF-
C/-CR so that every microcomputer unit will be able to supervise the basic timing signals.
To supervise the operation of the cabling of the alarm signals and the alarm input of the
alarm interface unit, the unit handling the operation management can activate the clock
alarm signal MBAL by setting the ALARMTEST signal into active state (state 1). The
activation of the ALARMTEST signal does not turn on the LED indicator for clock alarm
or otherwise affect the operation of the MBIF-C/-CR. The inverted state of the
ALARMTEST signal (_ALARMTEST) can be read by the software from the status
register.
The operation of the entire clock alarm logic can also be tested by the software by using
the _MBALTEST command.
3.4.2 Settings of MBIF-C/-CR

Setting of wired Message Bus address
The 8-bit Message Bus address of the MBIF-C/-CR is chosen with the wiring of
connector signals UA7...UA0. Signals UA6...UA0 are equipped with a pull-up resistor, so
only state 0 needs to be wired. Signal UA7 has a pull-down resistor, so only state 1
needs to be wired when necessary.
The arbitration counter compares cabinet addresses instead of unit addresses. The
equipment enables any address for a unit within the scope of 00H…BFH. The addresses
C0H…FFH are not available as unit addresses, since these addresses would drive the
data bits MD15…12 at the start of the request cycle and would thus collide with the
cabinet address driven by the MBRP. However, these addresses are available as group
addresses. Cabinet addresses can be read from the MBIF-C status register. The
reservation is directed at the start by with bits D7 and D6, in order to avoid the
aforementioned collision with MBRP (D7 and D6 can not have the status 1 for any unit).
D1 and D0 distribute effectively units in the same cabinet, as one and the same cabinet
often has several sequential addresses.
Activating 4-bit cabinet addresses
The _CA3EN signal is activated with a special unit address module (MBA 04...07) that
sets the unit MB address, and 4 bit cabinet addresses can then be used as wired cabinet
addresses.
DN02176011 Issue: 1-2 © 2016 Nokia 45

Operation of MBIF-C/-CR MBIF-C, MBIF-CR
4 Operation of MBIF-C/-CR
Front panel
The front panel of the MBIF-C/-CR contains two LED indicators, an upper green one and
a lower red one. The red LED is illuminated when a clock alarm is active and the green
LED is illuminated when the plug-in unit is connected to the MB.
Figure 14 Front panel of MBIF-C/-CR.
DN0283653
Front panel dimensions
The front panel dimensions of the MBIF-C/-CR are 262 x 20 mm.
Backplane connectors
The MBIF-C/-CR is connected to the motherboard of the cartridge via four five-row
connectors. The connector types are as follows:
• two 25-pin A-type female connectors, J1 and J4

• 19-pin B-type female connector, J3
• 22-pin B-type female connector, J5.
46 © 2016 Nokia DN02176011 Issue: 1-2

MBIF-C, MBIF-CR Power consumption of MBIF-C/-CR
5 Power consumption of MBIF-C/-CR

Table 12 Power Consumption of MBIF-C/-CR.
Voltage Current Power
+5 V 250 mA 1.25 W
-5 V 11 mA 55 mW
3.3 V 360 mA 1.20 W
DN02176011 Issue: 1-2 © 2016 Nokia 47

MBIF-C C74990, MBIF-CR C104965 MBIF-C, MBIF-CR
6 MBIF-C C74990, MBIF-CR C104965

Figure 15 W6 switch, LED indicators and backplane connectors of MBIF-C and MBIF-
CR.
J5
J4
LD1
J3
LD3
W6
MBIF-
1 8
C/-CR Interchangeability 2 7
J1 3 6
W6 4 5
DN04108947
The W6 pin header is used for setting the interchangeability code of the plug-in unit,
when required, see the table below.
There are no standard nor alternative settings available on the plug-in unit.
The other jumper groups are used only for tests or other special purposes.
Interchangeability code settings (W6)
Interchangeability is coded with four bits using the W6 pin header. Interchangeability
codes are described in the table below.
Table 13 Interchangeability code settings of MBIF-C/-CR (W6).
ICC code W6 settings
1–8 2–7 3–6 4–5
A OFF OFF OFF OFF
B ON OFF OFF OFF
C OFF ON OFF OFF
D ON ON OFF OFF
E OFF OFF ON OFF
48 © 2016 Nokia DN02176011 Issue: 1-2

MBIF-C, MBIF-CR MBIF-C C74990, MBIF-CR C104965
Table 13 Interchangeability code settings of MBIF-C/-CR (W6). (Cont.)
ICC code W6 settings
F ON OFF ON OFF
G OFF ON ON OFF
H ON ON ON OFF
J OFF OFF OFF ON
K ON OFF OFF ON
L OFF ON OFF ON
M ON ON OFF ON
N OFF OFF ON ON
P ON OFF ON ON
R OFF ON ON ON
Not defined ON ON ON ON
DN02176011 Issue: 1-2 © 2016 Nokia 49

Connector maps of MBIF-C/-CR MBIF-C, MBIF-CR
7 Connector maps of MBIF-C/-CR

Connector J5
1 GND +5V +5V +5V +5V +5V GND
2 GND +5V +5V +5V +5V +5V GND
3 GND -5V -5V -5V -5V -5V GND
4 GND 8M B 8M A MSGCOUNT 8k B 8k A GND
5 GND CGS B CGS A MBLOAD _INT 1 _INT 0 GND
6 GND GND
7 GND GND
8 GND AL ALTST SYNC1 SYNC0 GND
9 GND GND
10 GND PACKED B PACKED A GND MRE 2 B MRE 2 A GND 1A
11 GND MD 1 B MD 1 A GND MD 0 B MD 0 A GND
12 GND MD 3 B MD 3 A GND MD 2 B MD 2 A GND 1C
14 GND MD 7 B MD 7 A GND MD 6 B MD 6 A GND 1E
16 GND MD 11 B MD 11 A GND MD 10 B MD 10 A GND 1G
18 GND MD 15 B MD 15 A GND MD 14 B MD 14 A GND 1J
19 GND MAC B MAC A GND MSY B MSY A GND
20 GND MRE B MRE A GND MAE B MAE A GND 1L
21 GND MDP B MDP A GND MWR B MWR A GND
22 GND PACKED B PACKED A GND MRE 2 B MRE 2 A GND 1N
Connector J4
A B C D E F G
50 © 2016 Nokia DN02176011 Issue: 1-2

MBIF-C, MBIF-CR Connector maps of MBIF-C/-CR
2 GND MD 3 B MD 3 A GND MD 2 B MD 2 A GND 1P
3 GND MD 5 B MD 5 A GND MD 4 B MD 4 A
4 GND MD 7 B MD 7 A GND MD 6 B MD 6 A GND 1R
6 GND MD 11 B MD 11 A GND MD 10 B MD 10 A GND 1T
8 GND MD 15 B MD 15 A GND MD 14 B MD 14 A GND 1V
10 GND MRE B MRE A GND MAE B MAE A GND 1X
12 GND GND
13 GND CODE GND

AREA
14 GND GND
15 GND PACKED PACKED GND MRE 2 B MRE 2 A GND 2A

B A
17 GND MD 3 B MD 3 A GND MD 2 B MD 2 A GND 2C
19 GND MD 7 B MD 7 A GND MD 6 B MD 6 A GND 2E
21 GND MD 11 B MD 11 A GND MD 10 B MD 10 A GND 2G
23 GND MD 15 B MD 15 A GND MD 14 B MD 14 A GND 2J
25 GND MDP B MDP A GND MWR B MWR A GND 2L
Connector J3
DN02176011 Issue: 1-2 © 2016 Nokia 51

Connector maps of MBIF-C/-CR MBIF-C, MBIF-CR
2 GND GND 2N
3 GND +5V T GND TRMCCL GND +5V T GND
4 GND GND 2P
5 GND GND
6 GND “0” “0” “0” “0” “0” GND 2R
7 GND CA3 CA2 _REPEN CA1 CA0 GND
8 GND GND 2T
9 GND GND
10 GND “0” “0” “0” “0” “0” GND 2V
11 GND UA3 UA2 UA1 UA0 GND
12 GND UA7 UA6 _CA3EN UA5 UA4 GND 2X
13 GND “1” “0” “0” “0” “0” GND
14 GND GND
15 GND GND
16 GND GND
17 GND GND
18 GND GND
19 GND GND
Connector J1
1 GND 5V 3.3V 5V GND
2 GND AD[0] 5V AD[1] GND
3 GND AD[2] 5V AD[3] AD[4] 3.3V GND
4 GND AD[5] AD[6] 3.3V GND AD[7] GND
5 GND C/_BE[0] M66EN AD[8] AD[9] 3.3V GND
6 GND AD[10] AD[11] GND AD[12] GND
7 GND AD[13] GND AD[14] AD[15] 3.3V GND
8 GND C/_BE[1] PAR 3.3V GND _SERR GND
52 © 2016 Nokia DN02176011 Issue: 1-2

MBIF-C, MBIF-CR Connector maps of MBIF-C/-CR
9 GND _PERR GND 3.3V GND
10 GND _LOCK _STOP GND _DEVSEL GND
11 GND _TRDY GND _IRDY _FRAME 3.3V GND
12 GND GND
13 GND CODING GND

AREA
14 GND GND
15 GND C/_BE[2] GND AD[16] AD[17] AD[16] GND
16 GND AD[19] AD[20] 3.3V GND AD[21] GND
17 GND AD[22] GND AD[23] IDSEL C/_BE[3] GND
18 GND AD[24] AD[25] GND AD[26] GND
19 GND AD[27] GND AD[28] AD[29] AD[30] GND
20 GND AD[31] CLK 3.3V GND _REQ GND
21 GND _GNT GND _RST GND
22 GND GND GND
23 GND 5V GND
DN02176011 Issue: 1-2 © 2016 Nokia 53

DXT Plug-In Unit Descriptions: Mbif-C, Mbif-Cr

Uploaded by

Copyright:

Available Formats

DXT Plug-In Unit Descriptions: Mbif-C, Mbif-Cr

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DXT Plug-In Unit Descriptions: Mbif-C, Mbif-Cr

Uploaded by

Copyright:

Available Formats

Nokia

DXT Plug-in Unit Descriptions

Copyright © 2016 Nokia. All rights reserved.

f Important Notice on Product Safety

2 © 2016 Nokia DN02176011 Issue: 1-2

Summary of changes .................................................................... 6

2 Capacity and performance of MBIF-C/-CR.................................. 10

5 Power consumption of MBIF-C/-CR.............................................47

6 MBIF-C C74990, MBIF-CR C104965...........................................48

7 Connector maps of MBIF-C/-CR.................................................. 50

DN02176011 Issue: 1-2 © 2016 Nokia 3

4 © 2016 Nokia DN02176011 Issue: 1-2

DN02176011 Issue: 1-2 © 2016 Nokia 5

6 © 2016 Nokia DN02176011 Issue: 1-2

DN02176011 Issue: 1-2 © 2016 Nokia 7

Figure 1 Operating environment of MBIF-C/-CR in microcomputer units.

Cabinet0 Cabinet1 CabinetN

8 © 2016 Nokia DN02176011 Issue: 1-2

DN02176011 Issue: 1-2 © 2016 Nokia 9

2 Capacity and performance of MBIF-C/-CR

10 © 2016 Nokia DN02176011 Issue: 1-2

3.1 Mechanical structure of MBIF-C/-CR

• two 25-pin A-type female connectors, J1 and J4

The connectors are numbered from J5 to J1 (from top to bottom).

3.2 Logical structure of MBIF-C/-CR

• PCI bus interface

DN02176011 Issue: 1-2 © 2016 Nokia 11

Figure 4 Block diagram of the MBIF-C/-CR.

12 © 2016 Nokia DN02176011 Issue: 1-2

Figure 5 Message Bus receiver.

• It forms the command pulses needed, if the received message is a command. A

The Receive-FIFO is 32 kilobytes and it is organized as follows: 18 x 16k (including data,

DN02176011 Issue: 1-2 © 2016 Nokia 13

14 © 2016 Nokia DN02176011 Issue: 1-2

Figure 6 Message Bus transmitter.

DN02176011 Issue: 1-2 © 2016 Nokia 15

16 © 2016 Nokia DN02176011 Issue: 1-2

DN02176011 Issue: 1-2 © 2016 Nokia 17

Time (ns) Action

0 MRE signal activated.

152,5 Data bits read. Bit MDx set to high impedance.

183 Data bit MDx set to zero.

244 MDx is set to high impedance.

427 Data bits read. Bit MDx is set to high impedance.

The arbiter is implemented with an FPGA circuit.

18 © 2016 Nokia DN02176011 Issue: 1-2

Figure 7 Message Bus and Repeater interfaces.

• Command message is recognized during the first arbitration cycle.

DN02176011 Issue: 1-2 © 2016 Nokia 19

Table 2 Timing of free message bus segment's swapping period.

0 Arbiter counter and cabinet address values different.

20 © 2016 Nokia DN02176011 Issue: 1-2

3.3 Operating principles of MBIF-C/-CR

• the SYNC0 signal is in state 0 and the CGS signal is in state 0

DN02176011 Issue: 1-2 © 2016 Nokia 21

22 © 2016 Nokia DN02176011 Issue: 1-2

3.4 Interfaces of MBIF-C/-CR

DN02176011 Issue: 1-2 © 2016 Nokia 23

Figure 8 Interfaces of the MBIF-C

Cabinet0 Cabinet1 CabinetN