GPIO Peripheral

Interrupts

1
2303ENG Embedded Systems(NA and GC)
Enabling interrupts:

 Entire mController level (via CPSIE, CPSID instr)

 System level
(via NVIC Registers) PortB

PortD
e.g. Uart0

 Peripheral level
(via GPIO Registers) PortB Pin2

Uart0 Receive PortD Pin1

Connected to
Connected to terminal
Connected to light switch
key press
motion sensor
 Interrupt Enable / Disable (CPU level)

Embedded C
//DisableInterrupts:
asm("CPSID I") ;

//EnableInterrupts:
asm("CPSIE I");

Keil uVision – Predefined Macros

//DisableInterrupts:
__disable_irq();

//EnableInterrupts:
__enable_irq();
External Interrupts
Eg: Triggered by GPIO pin, UART etc.
GPIO registers (datasheet, p636)
UART Registers (datasheet, p862)
GPIO Interrupts

 The interrupt capabilities of each GPIO port are controlled by a set of

seven registers. These registers are used to select the source of the
interrupt, its polarity, and the edge properties.

 When one or more GPIO inputs cause an interrupt,

a single interrupt output is sent to the interrupt controller
for the entire GPIO port.

 For edge-triggered interrupts, software must clear the interrupt to

enable any further interrupts.

 For a level-sensitive interrupt, the external source must hold the

level constant for the interrupt to be recognized by the controller.
GPIO Interrupt Registers

 Three registers define the edge or sense that causes

interrupts:
GPIO_IS, GPIO_IBE, GPIO_IEV

 Interrupts enabled/disabled via:

GPIO_IM

 When interrupt condition occurs, state of interrupt signal can

be viewed in:
GPIO_RIS, GPIO_MIS

 Interrupts can be cleared via:

GPIO_ICR
 GPIO Interrupt Registers
Register Read / Offset Purpose
Name Write
GPIO_IS R/W 0x404 Interrupt Sensitivity
(Sets level or edge triggering)
GPIO_IBE R/W 0x408 Interrupt Both Edges
(interrupt generation controlled by IEV or both edges)
GPIO_IEV R/W 0x40C Interrupt Event Type
(rising / falling edge OR high / low level)
GPIO_IM R/W 0x410 Interrupt Mask
(Enable / Disable interrupt for GPIO port)
GPIO_RIS RO 0x414 Raw status of interrupt (1= interrupt has occurred on
corresponding pin.)
GPIO_MIS RO 0x418 Masked interrupt status (1= interrupt condition on pin has
triggered an interrupt. 0= interrupt condition on pin
masked or hasn’t occurred).
GPIO_ICR W1C 0x41C Clear interrupt flag for GPIO port
(write 1 to clear interrupt)

Register address is base address for selected GPIO port + offset.

RO = read only, RW = read & write, W1C=write 1 to clear
GPIO pin interrupt : Sense

GPIOX_IS Offset 0x404

| pins 7-0

⚫ Sets the GPIO Pin sense to edge triggered or level triggered

⚫ Then use:
⚫ GPIOx_PORTX_IEV and GPIO_PORTX_IBE are used to set the type of edge
trigger (falling edge, rising edge, or both)
⚫ GPIOx_PORTX_IEV is used to set the level trigger (high or low)

⚫ Setting to 0 sets edge sensitive for that GPIO pin

⚫ Setting to 1 sets level sensitive for that GPIO pin

Where x is A, B, … , Q
GPIO pin interrupt: Level sensitive

GPIOX_IEV (interrupt event) Offset 0x40C

| pins 7-0

GPIO_IEV is used to set the type of trigger event, based on whether edge or level
trigger is selected in register GPIO_IS.

For level sensitive

Set GPIO_IEV to:
0 for low level trigger for that GPIO pin (0V)
1 for high level trigger for that GPIO pin (3.3V)

Where x is A, B, … , Q
GPIO pin interrupt : Edge sensitive

GPIOX_IEV (interrupt event) Offset 0x40C

GPIOX_IBE (interrupt both edges) Offset 0x408

| pins 7-0
For edge sensitive
GPIO_IEV and GPIO_IBE together set the edge interrupt for the GPIO pin to be :
⚫ falling edge triggered ( 3.3V→0V) IBE IEV Edge interrupt
⚫ rising edge triggered ( 0V→3.3V ) , or 0 0 Falling ( )
⚫ both ( & )
0 1 Rising ( )

GPIO_IBE is 0 for single edge, 1 for both 1 0 Both ( & )

GPIO_IEV is 0 for falling, 1 for rising edge 1 1 Both ( & )

Where x is A, B, … , Q
GPIO pin interrupt : Putting it all together

IS IBE IEV Interrupt Type

0 0 0 Falling ( )

0 0 1 Rising ( )

0 1 0 Both ( & )

0 1 1 Both ( & )

1 0 0 Low Level

1 0 1 High Level
 EG: Hi Level trigger on pin 5

EG: Hi Level trigger on pin 5

 EG: Hi Level trigger on pin 5

EG: hi level trigger on pin 5

Pin 5 needs IS=1, IBE=0, IEV=1

IS=00100000 IBE=00000000 IEV=00100000

 EG: Both Edge trigger on pin 5

EG: Both trigger on pin 5

 EG: Both edge trigger on pin 5

EG: both edge trigger on pin 5

Pin 5 needs IS=0, IBE=1, IEV=1

IS=00000000 IBE=00100000 IEV=00100000

GPIO pin interrupt: Mask

GPIOX_IM Offset 0x410

| pins 7-0

 Enables or disables interrupts for the GPIO pin

 This is known as a local interrupt enable/disable since it is a port level as opposed
to a processor level.
 When set, interrupts can be generated by corresponding pin and allowed to be
sent to the interrupt controller in a combined interrupt signal.

 Setting to 0 disables (masks) interrupts for that GPIO pin

 Setting to 1 enables interrupts for that GPIO pin

Where X is A, B, C, D, E, F
GPIO Interrupt configuration:

To configure GPIO pins for external interrupt source we need to calculate

port (base) address of GPIO pin(s) to be used for interrupt.
Then interrupts are setup as follows:

(a) Set Interrupt Sense (GPIO_IS)

(b) If (sense=level) then set low

or high level trigger (GPIO_IEV)
If (sense=edge) then set falling edge,
rising edge, or both
(GPIO_IEV & GPIO_IBE)

(c) Enable Interrupts on GPIO pin(s)

(GPIO_IM)
GPIO Interrupt Status Registers
GPIO Raw Interrupt Status

GPIOX_RIS Offset 0x414

| pins 7-0

 Raw Status register - a bit is set in this register when an interrupt condition occurs
on the corresponding GPIO pin.
 This is read only register.
 If bit set (=1) in GPIO_ICR (interrupt clear) register, the corresponding bit in the
GPIO_RIS register is cleared.

Bit value:
0 = Interrupt condition has not occurred on corresponding pin.
1 = Interrupt condition has occurred on corresponding pin.

Where x is A, B, … , Q
GPIO Masked Interrupt Status

GPIOX_MIS Offset 0x418

| pins 7-0

 Masked Status register - a bit is set in this register when an event has triggered an
interrupt to the interrupt controller. Thus both an event has occurred, and an
interrupt on this pin is enabled.
 This is read only register.
 If bit set (=1) in GPIO_ICR (interrupt clear) register, the corresponding bit in the
GPIO_MIS register is also cleared.

Bit value:
0 = Interrupt condition has not occurred on corresponding pin or is masked.
1 = Interrupt condition has occurred on corresponding pin and triggered an
interrupt to interrupt controller.
Where x is A, B, … , Q
GPIO Interrupt Clear

GPIOX_ICR Offset 0x41C

| pins 7-0

 This register is used to clear the interrupt status registers.

 Writing a 1 to bit clears the corresponding interrupt status bits in GPIOx->RIS and
GPIOx->MIS registers. (Writing a 0 does nothing.)

 This register, in combination with status registers ( GPIOx->RIS and GPIOx->MIS )

are used to identify when you have finished handling the interrupt event.

Where x is A, B, … , Q
EG: How clear interrupt event on pins 6,5?

EG: How check for interrupt event on pins 6,5?

EG: How clear interrupt event on pins 6,5?

EG: How clear interrupt event on pins 6,5?

GPIO ICR Register: GPIOx->ICR |= 01100000 ;  Write a 1 in the bit to clear it

do not use &~
 External Interrupts :
1. Disable ALL interrupts

2. Configure GPIO subsystem: typically a regular I/O port

3. Set GPIO registers to allow interrupts

a) Clear interrupts on GPIO pins (GPIOx->IM)
b) Set interrupt sense (GPIOx->IS)
c) Set sense parameters (GPIOx->IEV & GPIOx->IBE)
d) Enable interrupts on GPIO pins (GPIOx->IM)

4. Set NVIC to enable interrupts for port using designated interrupt number
(NVIC->ENn, NVIC->PRIn)

5. Enable ALL interrupts (CPSIE I)

6. Write ISR routine making sure Flag is cleared using GPIOx->ICR