BTEH 2223 MICROPROCESSOR SYSTEMS

CHAPTER 8: DATA ACQUISITION AND

DISTRIBUTION

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OVERVIEW OF ANALOG VARIABLES
 Most of real variables come to microcontroller s are analog in nature. They
are continuously variable and can take an infinite range of different values,
whether we are talking about temperature, sound level, frequency or other
variables.
 It is necessary, therefore, for the microcontroller to be able to read values
that are analog and if necessary generate output values that are analog, even
though internally the microcontroller is relentlessly a digital device.
 The process of converting an analog signal to digital, along with all the
attendant signal manipulation, is usually called ‘data acquisition’.
 Once data from the outside world has been acquired, it needs to be processed
and put to use. It may also need to be averaged, scaled, linearised or stored.
Quite possibly it will be used for some form of control purpose and it may
need to be displayed, or transmitted to another device.

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PROPERTIES OF ANALOG AND DIGITAL QUANTITIES

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 A Data Acquisition System

When converting an analog signal to digital form, it is usually not enough just to find a suitable ADC
(Analog to Digital Converter). Usually, more than one input is required and the signal needs
processing before it can be converted. In most cases, therefore, it is necessary to build up a complete
data acquisition system. The elements of such a system are shown below. This shows, in block
diagram form, a system with multiple inputs, amplification, filtering, source selection, sample and
hold, and finally the ADC itself. The different elements are outlined in the sections which follow.

Filter Multiplexer
Removes unwanted Selects which ADC
signal components, input channel is Converts its
Transducer usually for anti- connected to its Analog Input to a Voltage
Generates signal aliasing purposes output
Sample & Hold Digital Output Reference
Samples its input
signal, and holds
that voltage as a
steady value at its
output

Sample Digital
Output

Amplify and Offset Start Output

Amplifies signal and
Input Select Conversion Result CPU 4
adds DC offset, to Conversion Control
match ADC input Complete
range.
The Sample and Because most ADCs work better converting a stationary voltage, a Sample
and Hold circuit is commonly used. In this type of circuit a capacitor is
Hold Circuit charged from a source which inevitably has some resistance. Further
resistance comes from internal resistance of the solid-state switch used in
the S&H, and/or in the multiplexer. Therefore the capacitor takes finite
time to charge, with a charging characteristic as shown.
Signal Source
Input
The voltage rise is given by:
Output
R +
VS Control C - Vo
VC
To ensure good accuracy in data conversion, the error
introduced in acquired voltage value, Vc should be less
than the equivalent of half of one LSB.
A Simple Form of VC
Sample and Hold Circuit
0.9995 V
S
0.9980 V
S
 Acquisition time is the amount time 0.9000 V
S
required to charge the holding
capacitor on the front end of an
analog-to-digital converter. The
holding capacitor must be given
sufficient time to settle to the analog
input voltage level before the actual 2.3RC 6.2RC 7.6RC t
conversion is initiated. If sufficient 5
time is not allowed for acquisition, Charging Characteristic of
the conversion will be inaccurate. Sample & Hold
 Analogue
Input
Model

The acquisition time, i.e. the time for the hold capacitor to charge to acceptable final value, called tac, is given by:

tac = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= 2 us (can be ignored sometimes) + 7.6 RC (for 10-bit ADC, 2.3RC is for 8-bit ADC) + Temperature Coefficient(ignored)
= 2 us + 7.6 (RSS + RIC + RS) 120 pF
*Acquisition time increases with increasing resistance, capacitance and with accuracy required.

Overall time needed to complete a single conversion = tac + conversion time of 19.2 us + 2 TAD delay after complete conv.
= sampling rate in term of frequency (approximation)
The Amplifier settling time is specified as 2ms. The Temperature Coefficient applies only when temperatures is above6 25 oC,
and is specified as:
Temperature Coefficient = (Temperature - 25oC)(0.05ms/ oC)
It can be seen that this creates a time delay of only 0.5ms for every 10oC above 25o, so its impact in most cases is slight.
Integrating an ADC onto the Microcontroller

It is now possible to integrate much of a data acquisition system onto a single chip, and/or
into a microcontroller. But note - ADCs don’t easily integrate onto microcontrollers,
mainly because there is the risk of massive digital interference, both radiated, and through
shared earth and supply lines.

A partial solution is to separate the ADC earth and supply from that of the microcontroller,
and to minimise interference during conversion - by synchronising conversion to internal
clock transitions, and minimising all other switching at this time.

Ultimately, you will only find ADCs of limited resolution (generally 8- or 10-bit)
integrated onto a microcontroller.

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 The Analog to Digital Converter (ADC) characteristics
- The ADC accepts an input voltage (within the valid input range of ADC) that is infinitely variable, and converts
this to one of a fixed number of output values. The input range is set by high and low voltage references.
- An example ADC conversion characteristic is shown, where the input voltage is represented on the horizontal
axis, and digital output on the vertical.
- The term quantization refers to subdividing a range into small but measurable increments.
- For an n-bit ADC, the maximum output value will be (2 n – 1). For example, for an 8-bit ADC, the maximum value
will be (28 – 1), or (256 – 1), i.e. 255 decimal or 11111111 binary.

Resolution = input voltage range / 2n

This is the amount by which the input has to change to go from one output value up to the next.

Digital
Output
(2n - 1)
(2n - 2)

100

011

010

...001

0
0 Vmax Analogue 8
Input
Input Range
Operation of Successive Approximation analog-to-digital converter (SAR ADC)

The successive approximation converter performs a conversion on one bit at a time, beginning with the most
significant bit (MSB) and ending with the least significant bit (LSB) as shown in figure below.

The value of the most significant bit is determined by whether the input signal is in the upper or lower half of the
valid input range. The next most significant bit is determined by whether the input is in the upper or lower half of
the remaining range, and so on, until the least significant bit is determined.

The most significant bit will be converted as a 1, because the input is in the upper half of the range. The next bit
would be converted as a 0, because the test range for this bit is between 1/2 and 1, and the input is less than 3/4,
which is the mid-point of the test range. The next bit is also converted as a 0, because the test range is between 1/2
and ¾ and the input is below 5/8 which places it in the lower half of the test range. The following bit will be
converted as a 1 because it is above 9/16 placing it in the upper half of the test range.

This process is repeated until all the bits are determined. Each bit requires one analog-to-digital converter clock
period for conversion.

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The 16F873A ADC
The 16F873A has a versatile 10-bit ADC module, shown below. This provides a subset of the overall data acquisition
system. The particular ADC design used incorporates the function of Sample and Hold. The input multiplexer, seen to
the right, has 5 channels for the 16F873A or 8 channels for the 16F874A. The inputs are shared with five of the six
Port A bits. Port A bit four is not used, as it already shares with the Timer 0 input. Port bits can be allocated in a
flexible way to analog or digital input.
External input for
Input select voltage reference
bits

Input
Multiplexer
An external voltage reference
can be used for applications
requiring reasonable
accuracy. Provision of the
negative connection means
that the reference does not
have to be referred to system
ground, or it can at least be
connected to a “clean”
ground. For lower cost, lower
accuracy conversions, the
power supply voltage can be
used as reference. The input
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range is equal to whatever
voltage reference is chosen.
The ADCON0
Register
The ADC is controlled by
two SFRs, ADCON0 and
ADCON1. The result of the
conversion is placed in two
further SFRs, ADRESH and
ADRESL. These four
registers can all be seen in
the SFR Memory Map. Any
bits used for analog input
must also be set as inputs in
TRISA.

Registers PIR1 and PIE1,

which contain the ADC
interrupt flag and interrupt
enable bits respectively, are
also used.

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The ADCON1
Register

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 The ADC Conversion Clock

Operation of the ADC is governed by the ADC clock, which has a period TAD. TAD is defined as
A/D conversion time per bit. Afull 10-bit conversion takes around 12 TAD cycles, depending
slightly on which clock source is chosen. The user can select the clock frequency from a number
of options. Although one generally wants a conversion to take place as quickly as possible, there
is an upper limit to the clock frequency. For the 16F87XA the minimum clock period for correct
operation is specified as a period of 1.6ms, or a frequency of 625 kHz (from data sheet). This
implies a fastest conversion time of 19.2 us.

A slow ADC, with a high conversion time, will only be able to convert low-frequency signals

At the other extreme, if conversion is too slow, charge leaks from the storage capacitance, and
the conversion becomes inaccurate. Best practice is therefore to set the ADC clock frequency
such that it has a period equal to or just more than 1.6ms.

Selection of the ADC clock source is controlled by bits ADCS2 in ADCON1, and ADCS1 and
ADCS0 in ADCON0. The RC oscillator has a typical period of 4ms, but may range from 2 to
6ms.

If the system clock is fast, it is usually appropriate to use it to derive the clock source. If the
system clock is slow however, it is better to use the RC oscillator.
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Completion of conversion may therefore be detected by testing either of the bits GO=DONE or
ADIF
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Typical Timing Requirement of one A to D Conversion

Configure i/o pins

Select the channel to convert Select multiplexer input

Configure and enable the A/D

“Sample” Input Signal
Wait the acquisition time Delay for signal acquisition
“Hold” Input Signal

Initiate the conversion

Wait for the conversion to complete

Delay for conversion

to complete

Read Data
 Step 1: Configure i/o pins
banksel TRISA ; assembler directive to select bank
movlw b’11111111’
movwf TRISA ; set all PORTA pins as inputs

 Step 2: Select the channel to convert

All pins used for analog-to-digital conversion should also be configured as analog pins. The
value in the ADCON1 register determines if pins are configured as analog or digital, and the
source of the analog-to-digital converter voltage references. Consult the data sheet of the device
for a table that shows the allowable configuration options for ADCON1.
banksel ADCON1 ; assembler directive to select bank
movlw b’00000010’
movwf ADCON1 ; RA0,1,2,3,5 set to analog input, VREF = VDD

 Step 3: Configure and enable the A/D

The input channel and the analog-to-digital converter clock are selected, and the converter is
enabled, by the options selected in the ADCON0 register. In this example, the analog-to-digital
converter clock is selected as the main oscillator frequency divided by eight, the input channel
selected is channel zero, and the converter is being enabled.
It is important to note that the converter is being enabled but the conversion is not being
started at this time. The conversion should not be initiated in the same instruction that enables
the converter, since this will violate the acquisition time requirements.
banksel ADCON0 ; assembler directive to select bank
16
movlw b’01000001’
movwf ADCON0 ; channel 0, Fosc/8, enable A/D
 Step 4: Wait the acquisition time
After a channel is selected in the ADCON0 register, you must allow for sufficient acquisition
time before initiating the conversion. A period equal to or greater than the required S&H
acquisition time must elapse An easy way to wait the acquisition time is through the use of a
delay loop. In this example, assume that a minimum acquisition time of 20us (as refer to 19.72us
in datasheet) is required.
; 20us delay loop with 4MHz oscillator frequency
banksel count ; select the bank where count is in
movlw 0x06
movwf count ; initialize count with value 6h
loop: decfsz count, F ; decrement count, store back in count
goto loop ; not finished
 Step 5: Initiate the conversion
After the acquisition time has passed, the conversion can be started. This is accomplished by
setting the GO bit in the ADCON0 register.
banksel ADCON0 ; select bank
bsf ADCON0, GO ; initiate conversion

 Step 6: Wait for the conversion to complete

Once the conversion has been initiated, the conversion time must be allowed for before reading
the result. The status of the analog-to-digital conversion is indicated by the GO/DONE bit in the
ADCON0 register, which is automatically cleared when the conversion is complete.
banksel ADCON0 ; select bank 17
test: btfsc ADCON0, GO ; conversion done?
goto test ; not done yet
 Step 7: Wait the acquisition time
Once the analog-to-digital conversion has completed, the result can be read. The result of the
conversion is automatically placed in the ADRESH, ADRESL register upon completion. In this
example, the contents of the ADRESH register are moved into the W register for further
processing by the user’s application.
banksel ADRESH ; select bank
movf ADRESH, W ; move result into working register

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