TI Designs

Isolated IGBT Gate Driver Evaluation Platform for 3-Phase

Inverter System

TI Designs Design Features

This reference design consists of a 22-kW power • 3-Phase Inverter System With
stage with TI’s new reinforced isolated IGBT gate – 1200-V Rated IGBT Module of Current Ratings
driver ISO5852S intended for 3-phase inverters in From 50 to 200 A (Supporting Multiple Vendors)
various applications like AC drives. This design allows
performance evaluation of the ISO5852S in a 3-phase – Seven Reinforced Isolated IGBT Gate Drivers:
inverter incorporating 1200-V rated IGBT modules of ISO5852S With Working Voltage Isolation of
current ratings ranging from 50 to 200 A. 1.5 kVRMS With Minimum CMTI of 50 kV/μs
a • Incorporates Protection Against Overcurrent and
Some of the important functionality and performance False Turn ON Using
evaluated are short circuit protection using DESAT – DESAT Detection
detection, soft-shutdown, effectiveness of the Active
Miller Clamp at different inverter dv/dt, ESD, and EFT – Soft Shutdown
performance of the IGBT gate driver at system level – Active Miller Clamp
derived from adjustable speed electrical power drive • Meets IEC61800-3 EMC Immunity Requirements:
systems (IEC61800-3). Piccolo LaunchPad
LAUNCHXL-F28027 generates the PWM signals – ±8-kV ESD CD per IEC 61000-4-2
required for controlling the inverter. – ±4-kV EFT per IEC 61000-4-4
• Onboard Half-bridge Isolated Power Supply
Design Resources Generating 16 V/–8 Vfor Gate Drivers With
Provision to Operate Gate Drivers With Unipolar or
TIDA-00195 Design Folder
Bipolar Supply With External BJT/MOSFET Buffers
ISO5852S Product Folder
• Can Configure Gate Driver Input for Inverting or
AMC1200 Product Folder
Non-Inverting Operation
SN6501 Product Folder
UCC27211 Product Folder
• Option to Evaluate the System With
CSD88537ND Product Folder – Twisted Pair Cable Between the Gate Driver
TPS54286 Product Folder and IGBT
LP38691 Product Folder – External Capacitance Between Gate and
SN74ALVC125 Product Folder Emitter

Featured Applications
ASK Our E2E Experts • Industrial Variable Speed Drives
WEBENCH® Calculator Tools
• Servo Drives
• Solar Inverters
• UPS

+24-V DC

VDC_PLUS IGBT power

module
SMPS
HALF +16 V
PWMs
BRIDGE Reinforced
-8 V
C2000 LaunchPAD interface

SMPS isolated Inverter

+16 V IGBT gate output
driver ±
-8 V ISO5852S
Gate
Inverter PWM signals
drive
signals

VDC_MINUS
DC bus sensing

NTC output

IGBT brake

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Introduction to IGBT Gate Drivers www.ti.com

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.

1 Introduction to IGBT Gate Drivers

Insulated gate bipolar transistors (IGBTs) are considerably used in 3-phase inverters that have numerous
applications like variable-frequency drives that control the speed of AC motors, uninterruptible power
supply, solar inverters, and other similar inverter applications.
IGBTs have the advantages of high input impedance as the gate is insulated, has a rapid response ability,
good thermal stability, simple driving circuit, good ability to withstand high voltage, snubber-less operation,
and controllability of switching behavior providing reliable short-circuit protection. The IGBT is a voltage-
controlled device, which gives it the ability to turn ON/OFF very quickly.
A typical application of a three-phase inverter using six isolated gate drivers is shown in Figure 1. Note
that each phase uses a high-side and a low-side IGBT switch to apply positive and negative high-voltage
DC pulses to the motor coils in an alternating mode.
The output voltage to the motor is controlled by pulse-width modulation (PWM). PWM is accomplished by
turning the transistor on and off several times. The output voltage is an average of the peak or maximum
voltage and the amount of time the transistor is turned on or off.
VBUS VBUS VBUS

+16 V +16 V +16 V

ISOLATION

ISOLATION

ISOLATION

From From From

Controller Controller Controller

±8V ±8V ±8V

TI
'DYH¶V
Control
Center

+16 V +16 V +16 V

+
+5 V

+
ISOLATION

ISOLATION

ISOLATION

+5 V
From From From
Controller Controller Controller

To ADC or Controller

±8V ±8V ±8V

VGND VGND VGND

Figure 1. 3-Phase Inverter With Isolated Gate Drive

The ISO5852S is a reinforced isolated IGBT gate driver from TI intended for use in applications such as
motor control, industrial inverters, switched-mode power supplies, and so on. In these applications,
sophisticated PWM control signals are required to turn the power-devices on and off, which at the system
level eventually may determine, for example, the speed, position, and torque of the motor or the output
voltage, frequency, and phase of the inverter. These control signals are usually the outputs of a
microcontroller (MCU), and are at low-voltage levels such as 3.3 or 5.0 V. The gate controls required by
the IGBTs, on the other hand, are in the range of 15 to 20 V, and need high current capability to be able
to drive the large capacitive loads offered by those power transistors. Also, the gate drive needs to be
applied with reference to the emitter of the IGBT and by inverter construction, the emitter node of top
IGBT swings between 0 to the DC bus voltage, which is several hundreds of volts in magnitude. As the
IGBT can float with respect to ground at the power stage, both the power supply and the gate circuitry
should be isolated from the inverter ground. This gives room to a limited number of gate-driver
configurations:
• Gate drivers with potential separation
• Gate drivers without potential separation

2 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System TIDUA15A – June 2015 – Revised August 2015
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www.ti.com Introduction to IGBT Gate Drivers

The ISO5852S belongs to a family of gate drivers with potential separation and can level shift the
incoming 3.3-V and 5.0-V control signals from the microcontroller to the 15-V to 20-V drive required by
IGBT while ensuring high-voltage isolation between the driver side and the MCU side.
This reference design consists of a 22-kW power stage with TI’s reinforced isolated gate drivers
ISO5852S intended to drive AC induction motor used in various industrial applications. This reference
design demonstrates the following functionality and performance of ISO5852S IGBT gate driver in the real
system:
• Unipolar and bipolar IGBT gate driver supply operation
• Undervoltage shutdown
• Interface with external BJT based current buffers
• DESAT detection
• Miller clamp
• Soft turn OFF
• Propagation delay
• ESD and EFT immunity performance of IGBT gate driver at system level
IGBT power module has been chosen such that its footprint fits multiple devices so as to perform gate
driver validation on IGBTs from different manufacturers. The footprint supports:
• Fuji Electric: 6MBL150VX-120-50, 6MBL100VX-120-50
• Mitsubishi: CM150TX-24S1
• Infineon: FS50R12KT4, FS200R12KT4R, FS100R17N3E4
The C2000 Piccolo LaunchPad evaluation kit, based on the F28027 MCU is been used to control the
inverter.
The power stage includes protection against IGBT overcurrent, over temperature of power module, and
DC bus sensing for protection against overvoltage.

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Key System Specifications www.ti.com

2 Key System Specifications

Table 1. Key System Specifications of Power Stage

PARAMETER SPECIFICATION
DC link input voltage 400 to 1100 V
Control voltage 24-V DC
IGBT power module 1200 V/50 to 150 A
Maximum input DC current 50 A with 200 CFM Airflow
Rated power capacity 22 kW
Inverter switching frequency 16 kHz (Default); adjustable through software
Isolation Reinforced (IEC61800-5)
Operating ambient temperature –25°C to 65°C
Inverter efficiency ≥ 97% (Theoretical) at rated load
Controller TMS320F28027
Motor 3-phase 400-V Induction motor
Provision for resistive braking Yes
Power supply specification for MCU 3.3 V ±5%
Feedbacks DC bus voltage, IGBT temperature
Protections Short circuit, over temperature, DC bus under- or overvoltage
ESD (IEC61000-4-2) ±8-kV Contact discharge
EFT (IEC61000-4-4) ±4-kV on motor cables (shielded and unshielded)
PCB 370 × 240 mm / 4 Layer, 2Oz copper

4 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System TIDUA15A – June 2015 – Revised August 2015
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www.ti.com System Description

3 System Description
The system consists of
• IGBT power module: hex bridge IGBTs to provide three phases output for variable-frequency drives to
control the speed of AC motors (up to 22 kW). The PCB footprint supports mounting of different current
rated modules from different manufactures
• ISO5852S reinforced isolated gate driver capable of sourcing a 2.5-A and 5-A sink current is used to
drive the IGBTs. Half-bridge converter powered from 24-V with isolated 16-V/-8-V rails are used to
power gate drivers. The half-bridge transformer has been designed to meet safety requirements as
described in IEC61800-5
• Isolated amplifiers for measuring DC link voltage
• C2000 LaunchPad for controlling the inverter. This design uses F28027 InstaSPIN™ FOC-enabled
MCU. The sinusoidal voltage waveform applied to the motor is created by using the Space Vector
modulation technique implemented in the F28027 MCU
• Buck converters for powering control electronics, operated from a 24-V supply and generates multiple
voltage rails like 15 V and 5 V. An LDO is used to generate 3.3 V from a 5-V supply for powering the
C2000 LaunchPad
• Local DC link capacitor of ~220 μF. Relay is used to bypass NTC after power up
• Discrete brake IGBT for braking during regeneration
• Provision to measure the power module temperature using NTC
• Provision for operating the FAN
PCB is designed to fulfill the requirements of IEC61800-5. Figure 2 depicts the block diagram of the
power stage.

4 Block Diagram

+24-V DC

+800-V DC IGBT power

module
SMPS
HALF +16 V
PWMs
BRIDGE Reinforced
-8 V
C2000 LaunchPAD interface

SMPS isolated
+16 V IGBT gate
driver ±
-8 V 3N ACIM
ISO5852S
Gate
Inverter PWM signals
drive
signals

DC bus sensing

NTC output

Figure 2. Power Stage Block Diagram

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Highlighted Products www.ti.com

5 Highlighted Products
Key features of the highlighted devices can be taken from product datasheets. The following are the
highlighted products used in the reference design.

5.1 ISO5852S
The ISO5852S is a 5.7 kVRMS, reinforced isolated, IGBT gate driver with split outputs, OUTH and OUTL,
providing 2.5-A source and 5-A sink currents. The primary side operates from a single 3-V or 5-V supply.
The output side allows for a supply range from minimum 15 V to maximum 30 V. An internal DESAT
detection recognizes when the IGBT is in an overload condition. Upon a DESAT detect, a Mute logic
immediately blocks the output of the isolator and initiates a soft-turn-off procedure, which disables OUTH
and reduces the voltage at OUTL over a minimum time span of 2 μs. When OUTL reaches 2 V with
respect to the most negative supply potential, VEE2, the output is hard-clamped to VEE2.
During normal operation with bipolar output supply the output is hard clamp to VEE2 when the IGBT is
turned OFF. If the output supply is unipolar, an active miller clamp connects the output to VEE2.

5.2 CSD88537
The CSD88537 is a 60-V, dual N Channel, SO-8 NexFET™ power MOSFET with very low Drain-to-
Source ON resistance of 12.5 mΩ. FET is capable of handling continuous current of 8 A. CSD88537 is
designed to serve in half-bridge power supplies and motor control applications to generate gate driver
supplies.

5.3 UCC27211
The UCC27211 is a MOSFET driver delivering peak source and sink current of up to 4 A. The inputs are
independent of the supply voltage and have a maximum rating of 20 V. The floating high-side driver can
operate with supply voltages of up to 120 V. The high-side driver is referred to the switch node (HS),
which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The
low-side driver is referenced to VSS, which is typically ground. Features of the UCC27211 include input
stages UVLO protection, level shift, and built-in boot diode.

5.4 Piccolo LaunchPad

The C2000 LaunchPad is based around the C2000 Piccolo TMS320F28027 MCU, which features a 60-
MIPS processing core, 64-KB integrated flash, 8 PWM channels with high resolution capability, 12-bit 4.6-
MSPS ADC, capture interface, serial connectivity, and more. It is used to generate the PWM signals for
the 3-phase inverter.

5.5 TPS54286
The TPS54286 is a dual output non-synchronous buck converter capable of supporting 2-A output
applications that operate from a 4.5-V to 28-V input supply voltage, and provides output voltages between
0.8 V and 90% of the input voltage. The outputs can be enabled independently, or it can be configured to
allow either ratio metric or sequential startup.
With an internally-determined operating frequency, soft start time, and control loop compensation, this
converter provides many features with a minimum of external components. Other features include pulse-
by-pulse overcurrent protection and thermal shutdown protection at 148ºC.

6 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System TIDUA15A – June 2015 – Revised August 2015
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www.ti.com Highlighted Products

5.6 AMC1200
The AMC1200 is a precision isolation amplifier with an output separated from the input circuitry by a
silicon dioxide (SiO2) barrier that is highly resistant to magnetic interference. This barrier has been certified
to provide galvanic isolation of up to 4000 VPEAK according to UL1577 and IEC60747-5-2. The input of the
AMC1200 is optimized for direct connection to shunt resistors with a voltage range of ±250 mV. The
device has low offset error of 1.5 mV max, BW of 60 KHz and CMMR of 108 dB. The AMC1200 has a
working voltage rating of 1200 VPEAK.
The MC1200 is fully specified over the extended industrial temperature range of –40°C to 105°C and are
available in a wide-body SOIC-8 package (DWV) and a gullwing 8 package (DUB).

5.7 SN6501
The SN6501 is a monolithic oscillator/power-driver, specifically designed for small form factor, isolated
power supplies in isolated interface applications. The device drives a low-profile, center-tapped
transformer primary from a 3.3-V or 5-V DC power supply. The secondary can be wound to provide any
isolated voltage based on transformer turns ratio. The SN6501 consists of an oscillator followed by a gate
drive circuit that provides the complementary output signals to drive the ground referenced N channel
power switches. The internal logic ensures break-before-make action between the two switches. The
SN6501 is available in a small SOT-23 (5) package, and is specified for operation at temperatures from
–40°C to 125°C.

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6 System Design Theory

6.1 Main Power Input

The main power input section is shown in Figure 3. D1 is the reverse polarity protection diode and has
reverse breakdown voltage of 1600 V. The input bulk aluminum electrolytic capacitors C3, C6, and C7
serve as local reservoirs for the IGBT module. These capacitors are rated to carry ripple current of 7.7 A.
The rest of ripple current is expected to be sourced from external capacitors. In addition to the bulk
aluminum capacitor, a polyester capacitor is used across the DC bus to suppress high frequency noises.
The startup current through the bulk capacitor is limited using thermistor, and the thermistor is bypassed
after one second using a relay.
CN1 D1
1 A C

Terminal bush RHRG75120

R208
200K
C3

680µF
R209
200K

R212
C7 200K
680µF C154
FILM CAP
R213 0.22µF
200K

R210
200K
C6
680µF
R211
200K
PGND INRUSH_BYPASS
1

RL1
RT1
100R_PTC
HE1aN-P-DC24V-Y5 t° B59109J0130A020
5
6

+24V CN2
R103 1
10R
C

C131 D22
10µF SK310A-LTP
A

DNP
C

PGND
R104 B Q5
BYPASS_RELAY PZT2222A
470R
E

DGND

Figure 3. Main Power Input

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6.2 Inverter Stage

The IGBT-based 3-phase hex bridge inverter is shown in Figure 4. The decoupling capacitor (C154)
should be placed near to DC bus entry of inverter for better filtering. An improper layout or position of the
decoupling capacitors can cause undesired switching voltage spikes. IGBT (Q1) and free-wheeling diode
(D2) is added externally to the hex bridge IGBT module for braking.
The brake IGBT (APT70GR120L) is rated for 70 A (at TC = 110°C) current rating and 1200 V.
When DC bus voltage increases above the pre-defined value (this reference design uses a 1-kV
threshold) brake operation is enabled through controller and the excessive energy will be dissipated
through the resistive bank. The resistor bank is connected across the terminal blocks CN11 and CN12.
The rating of external brake resistor is selected on the basis of the VFD rating, braking duty cycle, and
magnitude of the energy to be dissipated.
IGBT Module
U1

FS200R12KT4R
30 27
DC_VOLT_POS1 MOT_R_PHASE1
31 28 MOTOR_R_PHASE
DC_VOLT_POS2 MOT_R_PHASE2
CN11
1 DC_POS 32 29
DC_VOLT_POS3 MOT_R_PHASE3
C

Terminal bush 16
C154 D2 DC_VOLT_POS4
FILM CAP RHRG75120
17
0.22 µF DC_VOLT_POS5
CN12
A

1 BRAKE 18
DC_VOLT_POS6
26
MOT_Y_PHASE3
C

25 MOTOR_Y_PHASE
Q1 MOT_Y_PHASE2
GATE_BRAKE G 33
DC_VOLT_NEG1
24
MOT_Y_PHASE1
APT70GR120L 34
DC_VOLT_NEG2
E

35
DC_VOLT_NEG3
15
DC_VOLT_NEG6
14 21
DC_VOLT_NEG5 MOT_B_PHASE1
13 22 MOTOR_B_PHASE
DC_VOLT_NEG4 MOT_B_PHASE2
23
MOT_B_PHASE3
GATE_R_TOP 1
GATE_R_TOP
GATE_R_TOP_RTN 2
GATE_R_TOP_RTN 19 NTC_1
NTC_1
GATE_Y_TOP 5
GATE_Y_TOP 20 NTC_2
NTC_2
GATE_Y_TOP_RTN 6
GATE_Y_TOP_RTN
GATE_B_TOP 9
GATE_B_TOP DGND
GATE_B_TOP_RTN 10
GATE_B_TOP_RTN

GATE_R_BOTTOM 3
GATE_R_BOTTOM
GATE_R_BOT_RTN 4
GATE_R_BOT_RTN
GATE_Y_BOTTOM 7
GATE_Y_BOTTOM
GATE_Y_BOT_RTN 8
GATE_Y_BOT_RTN
GATE_B_BOTTOM 11
GATE_B_BOTTOM
GATE_B_BOT_RTN 12
GATE_B_BOT_RTN

IC_FS200R12KT4R

Figure 4. 3-Phase Inverter of Power Stage

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6.2.1 IGBT module

This reference design is intended to support various makes of IGBT modules like Infineon, Fuji &
Mitsubishi, and so on. The power stage is designed to deliver up to 22-kW power. The power stage was
supplied with 800-V DC replicating high DC bus voltage during regeneration. Considering the safety factor
and switching spikes, IGBTs were selected with the voltage rating greater than or equal to 1200 V. The
current rating of the IGBT depends on the peak winding current.
The 3-phase inverter bridge is switched such that the sinusoidal current is injected into the motor
windings.
• Motor rating = 22 kW
• Line-to-line voltage = 415-V AC
• Power factor considered = 0.8
• Motor efficiency = 85%
Pout
I LL =
h motor ´ V LL ´ 3 ´ cos Æ (1)
Current through the winding = 47 A
Therefore, the peak value of the winding current = √2 × IRMS = 66 A. (2)
Considering an overloading of 200%, the peak winding current would be 132 A.
The IGBT module used in this reference design (CM150TX-24S1) has continuous collector current
carrying capacity of 150 A at TC = 100°C and peak current capacity of 300 A.
The selection of IGBT module with inbuilt NTC Thermistor is preferred to avoid thermal breakdown of the
IGBT. This IGBT temperature rise information is routed to the MCU to take necessary action.
IGBTs can be driven into saturation to provide a very low voltage drop between the emitter and collector.

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6.3 DC Link Voltage Sense Circuit

The DC bus input voltage to the inverter module is scaled down and fed to the MCU using the AMC1200
isolation amplifier, which has a gain of 8. The differential output of the AMC1200 can directly drive an
analog-to-digital converter (ADC) input or can be further filtered before being processed by the ADC.
The resistor divider network is chosen considering the maximum voltage for the MCU ADC input as 3.3 V
and the maximum DC link voltage to be measured as 1200 V.
To achieve better linearity and the noise performance of the device, the allowable input voltage between
the amplifier pin VINP and VINN is ±250 mV. The voltage divider resistor is selected such that input voltage
to the amplifier is less than ±250 mV at maximum DC bus condition.
Resistors R76 to R81 (see Figure 5) are selected as 1-M high-voltage resistors and R85 = 1K and R88 =
10K. The differential output of the AMC1200 is directly routed to ADC of MCU.
AMC Output = AMC Gain × VIN
æ R 85 ö
V IN = ç ÷ ´ V DC
ç R IN ÷
è ø (3)

æ 1K ö
V IN = ç ÷ ´ V DC
è 6 M + 11 K ø
V IN = 0.00017 ´ V DC
For 400-V DC input
VIN = 0.00017 × 400 ≈ 0.0665 V and VOUT = 8 × 0.0665 V ≈ 0.532 V.
For 1200-V DC
VIN = 0.00017 × 1200 ≈ 0.2 V
VOUT = 8 × 0.2 V ≈ 1.6 V
A decoupling capacitor of 4.7 μF and 0.1 μF is used for filtering the power-supply path of the AMC1200. A
capacitor (C166 and C84 in Figure 5) should be placed as close as possible to the VDD1 pin for best
performance.
+5V_ISO
3V3
R76 R77 R78 R79 C166 4.7µF
DC_POS
C83
1M 1M 1M 1M
R80
1M
0.1µF
0.1µF C84
R81 U14
1M GND_ISO
DGND
R83 1 8
VDD1 VDD2
10 Ohm 2 7 R84 0R DC_BUS_SENSE_POS
VINP VOUTP
R85
C85
1K 3 6 R86 0R DC_BUS_SENSE_NEG
0.01µF VINN VOUTN
R87
4 5
10 Ohm GND1 GND2
R88
C86 C87
10K AMC1200SDUBR
10pF 10pF
DGND

GND_ISO
GND_ISO

Figure 5. DC Voltage Sensing Module

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6.4 ISO5852S: Isolated IGBT Gate Driver

The ISO5852S is a 5.7-kVRMS, reinforced, isolated IGBT gate driver with split outputs OUTH and OUTL
capable of providing a 2.5-A source and 5-A sink currents. The primary side operates from a single 3.3-V
or 5-V supply. The output side allows for a supply range from minimum of 15 V to maximum 35 V. The
ISO5852S has both inverting and non-inverting gate control inputs, an active low reset input, and an open
drain fault output suitable for wired-OR applications.
Figure 6 shows the one section of the gate driver schematic. This IC can be powered with either a
unipolar or bipolar supply. If the IC is powered by unipolar supply, the VEE2 PIN should be connected to
GND2. The supply bypass capacitors provide the large transient currents necessary during a switching
transition.
The ISO5852S has the following features:
• 5.7-kVRMS reinforced isolation voltage
• 1.5-kVRMS working voltage
• 12-kV surge rating
• Split outputs providing 2.5-A peak source and 5-A peak sink currents
• Short propagation delay: 76 ns typical
• Active miller and short-circuit clamp
• Soft turn-off during short circuit
• FAULT alarm and RESET
• Input and output supply UVLO with ready (RDY) output
• CMOS compatible inputs
+15V R

NOTE:
Unipolar supply- Populate J1 only
C172 C25 C28
3V3 U7 Bipolar supply- Populate J2 only
1µF 0.1µF
10uF
10R R219 15 5
VCC1 VCC2
GATE_R_TOP_GND
C31
C29
1

0.1µF
9 3
4.7µF GND1 GND2 C173 J1
16 C174 C35 C33
GND1 QPC02SXGN-RC
DNP 1µF 1µF 0.1µF
1 10uF
VEE2 J2
IN+_R_TOP 10 8 TP1
IN+ VEE2 QPC02SXGN-RC
2

VEE_R 2 1 D4 D23
DGND -8V R
R39

1
IN-_R_TOP 11 2 A C A C DC_POS
IN- DESAT
1k
GL41Y-E3/96 GL41Y-E3/96
C

1
RDY1 12 7 R34 0R
RDY CLAMP
TP44 D69 D24 C39 J4
C40
RB160M-60TR

200pF 100pF QPC02SXGN-RC

MM3Z12VB

FLT1 13 4 R35 220R

A

FLT OUTH
1

TP17 R48 0R DNP

RST1 14
RST OUTL
6 R38 220R R37 0R 1 2 GATE_R_TOP 2
1

GATE_R_TOP_GND
J3
QPC02SXGN-RC
NOTE:
ISO5852 C38
10nF
To disable DESAT
DNP DESAT Capcitor
3V3 Populate Jumper
DNP
2
R60 R49
0R 0R
R61 1
IN+_R_TOP
0R
J16
PWM_DRV_R_TOP
R62 2 QPC02SXGN-RC
IN-_R_TOP
GATE_R_TOP_GND 2 1 GATE_R_TOP_RTN
0R
1
DNP R63 3
0R R233
0R

DGND

NOTE :
1. Non-inverting Configuration
2. Inverting Configuration

Figure 6. ISO5852S Application Schematic

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6.4.1 Power Supply

VCC1 and GND1 are the supply pins for the input side of the ISO5852S. The supply voltage at VCC1 can
range from 3 to 5.5 V with respect to GND1, thus supporting the direct interface to 3.3 V low-power
controllers as well as legacy 5 V controllers.
VCC2 and GND2 are the supply pins for the output side of the ISO5852S. VEE2 is the supply return for
the output driver and GND2 is the reference for the logic circuitry. The supply voltage at VCC2 can range
from 15 V up to 30 V with respect to VEE2.
A positive VGE of typically 15 V is required to switch the IGBT well into saturation. In this design, VCC2 is
fed with 16 V to ensure that IGBT is in full saturation.
For low power IGBTs, miller clamp functionality of the gate driver enables it to be operated with unipolar
voltage (VEE2 connected to GND2). For larger IGBTs, negative values of VGE, ranging from a required
minimum of –5 V up to the recommended –15 V, are necessary to keep the IGBT turned off and to
prevent it from unintentional conducting due to noise transients, particularly during short circuit faults. The
board has provision for connecting VEE2 to either 0 V or –8 V through jumpers.
+15V B_BOT

C98
3V3 U26 C187 10uF C155
1µF 0.1µF
10R R217 15 5
VCC1 VCC2
GATE_B_BOT_GND
C156 C157

1
4.7µF 0.1µF
9 3
GND1 GND2 C188 J37
16 C101
GND1 1µF C189 C159 QPC02SXGN-RC
DNP 10uF
1 1µF 0.1µF
VEE2 J38
IN+_B_BOT 10 8
IN+ VEE2 QPC02SXGN-RC

2
DGND
VEE_B_BOT 2 1
-8V B_BOT
IN-_B_BOT 11 2
IN- DESAT

RDY6 12 7
RDY CLAMP

FLT6 13 4
FLT OUTH

RST6 14 6
RST OUTL

ISO5852

Figure 7. ISO5852S Supply Voltages

6.4.2 Control Signal Inputs

The two digital control inputs, IN+ and IN–, allow for inverting and non-inverting control of the gate driver
output. In the non-inverting configuration, IN+ receives the control input signal and VIN– is connected to
GND1. In the inverting configuration, VIN– is the control input while VIN+ is connected to VCC1.
U26

15 5
VCC1 VCC2
3V3
DNP
9 3
2 GND1 GND2
R167 16
GND1
0R
1
R1681 IN+_B_BOT 10
VEE2
8
IN+ VEE2
0R
PWM_DRV_B_BOT
R169 2
IN-_B_BOT 11 2
IN- DESAT
0R 1
DNP R170
0R 12 7
RDY CLAMP

13 4
FLT OUTH
DGND
14 6
RST OUTL

ISO5852

Figure 8. ISO5852 Non-Inverting and Inverting Input Configurations

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6.4.3 Gate Resistance

The gate current and the appropriate power of the voltage supply depend on the operating frequency, bias
control voltages, and total gate charge. The total gate charge is published in IGBT datasheets, depending
on gate-control voltage. The gate charge necessary for switching is very important to establish the
switching performance of a MOSFET or IGBT. The lower the charge, the lower is the gate-drive current
needed for a given switching time. The gate current can be controlled using external gate resistor between
driver output and gate of IGBT. The value of the gate resistor determines the peak charge and discharge
currents.
The ISO5852S device features a split-output configuration where the gate drive current is sourced through
the OUTH pin and sunk through the OUTL pin. This pin arrangement provides flexibility to apply
independent turn-on and turn-off resistors to the OUTH and OUTL pins respectively and easily control the
switching slew rates. The value of the gate resistor influences different aspects of the switching process
like:
• IGBT switching losses
• Control di/dt
• Cross conduction
• Reverse recovery losses of the diode
The value of gate resistor is system dependent and usually chosen a value to provide optimum
performance. Strong sink capability (5 A) in an asymmetrical drive also boosts immunity against parasitic
Miller turn-on effect.
U7

15 5
VCC1 VCC2

9 3
GND1 GND2
16
GND1
1
VEE2
10 8
IN+ VEE2

11 2
IN- DESAT

12 7
RDY CLAMP

13 4 RG(ON) 220R
FLT OUTH
GATE
14 6 RG(OFF) 220R
RST OUTL

ISO5852

Figure 9. Gate Drive Split Outputs

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6.4.4 Optional External Current Buffer

When driving larger IGBTs requiring gate currents more than 5 A, an external current boost circuit can be
built with discrete NPN/PNP complimentary pair. One possible implementation is shown in Figure 10. The
selected BJT should be of fast switching and to have sufficient current gain to deliver the desired peak
output current. The circuit, in Figure 10, with a MJD3055T4/MJD2955 pair can drive gate currents up to 10
A.
+15V R_BOT

+15V R_BOT
+15V R_BOT

2
MJD3055T4
220R
OUTH 1

2
2

MJD3055T4 MJD3055T4
220R 220R
OUTH 1 OUTH 1

3
3
3

2.2R SK310A-LTP
C A 2.2R
10R 10R C A GATE
GATE GATE
SK310A-LTP
0R

2.2R 0R
2.2R
3

220R
MJD2955T4 3 MJD2955T4
OUTL 1 220R
OUTL 1

3
MJD2955T4
220R
OUTL 1
2

VEE_R_BOT
VEE_R_BOT

2
VEE_R_BOT

Figure 10. Options in Using External Current Buffer

6.4.5 Undervoltage Lockout

The undervoltage lockout feature prevents the application of insufficient gate voltage (VGE-ON) to the power
device by forcing OUTH/OTL low during power-up and whenever supply voltage drops below 11 V. IGBTs
typically require gate voltages of VGE = 15 V to achieve their rated, low saturation voltage, VCES. At gate
voltages below 13 V typically, their VCE-ON increases drastically, especially at higher collector currents. At
even lower voltages, that is VGE < 10 V, an IGBT starts operating in the linear region and quickly
overheats. The UVLO feature of ISO5852S avoids operating the IGBT in linear region by shutting it off
during insufficient gate supply voltage.
The UVLO feature has a hysteresis of 1 V typical and the typical values for the positive and negative
going input threshold voltages are VTH+ = 12 V and VTH– = 11 V.

6.4.6 Desaturation Protection (DESAT)

The DESAT fault detection prevents IGBT destruction due to excessive collector currents during a short
circuit fault. Short circuits caused by bad wiring, or overload conditions induced by the load can cause a
rapid increase in IGBT current, leading to excessive power dissipation and heating. IGBTs become
damaged when the current approaches the saturation current of the device and the collector-emitter
voltage, VCE, rises above the saturation voltage level, VCE-sat. The drastically increased power dissipation
overheats and destroys the IGBT.
To prevent damage to IGBT, ISO5852S slowly turns OFF the IGBT in the event of fault detection. Slow
turn OFF ensures the overcurrent is reduced in a controlled manner during the fault condition. The DESAT
fault detection involves a comparator that monitors the IGBT’s VCE and compares it to an internal 9-V
reference. If voltage across the IGBT reaches the threshold, DESAT detects immediately and blocks the
gate driver output and initiates a soft-turn-off procedure that disables the OUTH, and reduces the voltage
at OUTL over a minimum time span of 2 μs. The output is hard clamped to VEE2 when OUTL reaches 2 V
with respect to VEE2.

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6.4.6.1 DESAT Pin Protection

The diodes (GL41Y in Figure 11) at the DESAT signal block the high voltage during the IGBT OFF state
and conduct forward current, which allows the sensing of the IGBT’s saturated collector-to-emitter voltage
(VCESAT) when the IGBT is "ON". To avoid false DESAT triggering, fast switching diodes with low
capacitance are recommended. Because the sum of the DESAT diode forward-voltage and the IGBT
collector-emitter voltage make up the voltage at the DESAT-pin, VF + VCE = VDESAT, the VCE level, which
triggers a fault condition, can be modified by adding multiple DESAT diodes in series: VCE-FAULT (TH) = 9 V –
n × VF (where n is the number of DESAT diodes). When using two diodes instead of one, diodes with half
the required maximum reverse-voltage rating may be chosen. See Figure 11 where provision is provided
to mount two DESAT diodes.
Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling
diodes of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw
substantial current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor
can be connected in series with the DESAT diode. Further protection is possible through an optional
Schottky diode (MM3Z12VB), whose low forward voltage assures clamping of the DESAT input to GND
potential at low voltage levels.
U24

15 5
VCC1 VCC2

9 3
GND1 GND2
16
GND1
1
VEE2
10 8 TP6
IN+ VEE2
D53 D54
R159

1
11 2 A C A C DC_POS
IN- DESAT
TP41 1k
GL41Y-E3/96 GL41Y-E3/96
C

1
12 7
RDY CLAMP D73 D55
C149 C150 J33
RB160M-60TR

200pF 100pF QPC02SXGN-RC

MM3Z12VB

13 4
A

FLT OUTH
DNP
14
RST OUTL
6 2
GATE_B_TOP_GND

ISO5852

Figure 11. DESAT Detection

DESAT Blanking Time

The DESAT fault detection must remain disabled for a short time period following the turn-on of the IGBT
to allow its collector voltage to drop below the 9-V DESAT threshold. This time period, called the DESAT
blanking time, tBLK, is controlled by an internal charge current of ICHG = 500 μA, the 9-V DESAT threshold,
VDSTH, and an external blanking capacitor, CBLK.
CDESAT = 100 pF (refer to C150 in Figure 11).
9 V ´ C DESAT
tb =
500 mA (4)
9 V ´ 100 pF
tb =
500 mA
t b (ms ) = 1.8

The capacitor value can be scaled slightly to adjust the blanking time. However, because the blanking
capacitor and the DESAT diode capacitance build a voltage divider that attenuates large voltage transients
at DESAT, CBLK values smaller than 100 pF are not recommended.
If VCE exceeds this reference voltage (9 V) after the blanking time, the comparator inside ISO5852S
causes the gate drive and fault logic to initiate a fault shutdown sequence. This sequence starts with the
immediate generation of a fault signal, which is transmitted across the isolation barrier towards the fault
indicator circuit at the input side of the ISO5852S.
This board also provides feature of disabling the DESAT during testing by connecting the jumper at the
DESAT pin.

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6.4.7 Active Miller Clamp

During turn-on or turn-off of IGBTs, displacement current flows through the miller capacitor (gate to
collector capacitor) of the IGBT, raising its gate voltage. It could lead to unintentional turn-on of the IGBT.
When the high-side IGBT turns on within an inverter leg, the voltage across the low-side IGBT increases
with a high dv/dt. The ratio of reverse transfer capacitance to the input capacitance is larger for IGBTs
(CRES/CIES). This produces an increased Miller effect and a larger noise is coupled from the collector to the
gate.
This induces a current in the gate of the lower IGBT that may produce turn-on of the low-side device
shorting the DC bus.
However, certain low-power IGBTs have a lesser CRES (reverse transfer capacitance) and do not need
negative gate voltage for turn-off. Instead, the clamp functionality of the ISO5852S can be used to ensure
that gate is pulled to emitter thorough a low-impedance path, preventing a false turn-on.
The CLAMP transistor is turned on when OUTL reaches 2 V with regard to VEE2 during turn-off of the
IGBT. The CLAMP transistor hard clamps the OUTL pin to VEE2. The clamp transistor remains on once it
is ON even if OUTL goes above 2 V. The CLAMP transistor is again turned off during IGBT turn-on
process.
If the supply is unipolar, an active Miller clamp connects the output to VEE2 (Ground), and this condition is
latched. During a bipolar supply operation, the output is hard clamped to VEE2 (-8 V) when the IGBT is
turned off.
For larger IGBTs, a still negative gate voltage is required. Another reason for the negative gate voltage at
IGBTs is of the operation at higher voltages with increased (dv/dt) coupling of noise.

6.4.8 Fault and Protection Handling

The FAULT pin indicates an error event (with soft shutdown) has occurred such as IGBT short circuit.
Fault will be latched until the reset is applied. FAULT will go high, when the logic low pulse is applied to
RESET pin. This can be accomplished with an MCU, or an additional logic gate that synchronizes the
RESET signal with the appropriate input signal.
The ready pin is high during the primary and secondary side supplies are good. It is pulled LOW when the
supply voltage is less than the UVLO limits.

6.4.9 External Gate Emitter Capacitor to Shunt Miller Current

An option to mount external capacitor between IGBT gate and emitter has been provided to evaluate the
effectiveness of clamp functionality.
This capacitor can sink the additional charge originating from the Miller capacitance during the turn-on of
top IGBT. Due to the additional capacitance, the effective input capacitance of the IGBT is CG||CGE, the
gate charge required to reach the threshold voltage will be increased.

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6.4.10 Power Dissipation

In the process of turning the IGBT ON and OFF, power is dissipated by the driver IC, IGBT gate, and by
any RC circuits in the gate drive path.
VDC+

-16 V
Rg
PWM

-8 V
Cge (Ext)

VDC-

Figure 12. Driver Power Loss

The total gate power dissipation is calculated with Equation 5:

) (
P gate = P dc + Q gate ´ F sw ´ DV gate + C ge ´ F sw ´ DV 2gate
( )
where
• Qgate = total gate charge
• Fsw = Switching frequency
• ΔVgate = Gate driver output voltage swing (5)
For CM150TX-24S1, Qg is approximated as 450 nC for bipolar switching and 300 nC for unipolar
switching with Vge = 15 V.
• FSW = 16 KHz
• ΔVgate = 15 V and 23 V
• Cge = 10 nF
The static power dissipation of ISO5852S is PDC = IQ × VDD where IQ is the quiescent current for the
driver. The quiescent current is the current consumed by the device to bias all internal circuits such as
input stage, reference voltage, logic circuits, protections, and so on, and also any current associated with
switching of internal devices when the driver output changes state. The ISO5852S features very low
quiescent currents — 6 mA when supplied with 15 V and –8 V.
Power dissipation for bipolar switching: Pgate = 0.138 + 0.1656 + 0.085 = 0.4 W
Power dissipation for unipolar switching: Pgate = 0.2 W

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6.5 Half-Bridge SMPS for Gate Driver

A half-bridge SMPS is used to generate isolated positive (16 V) and negative (–8 V) voltage rails required
by IGBT gate drivers from a single 24-V DC input supply. The half-bridge driver is operated in open loop
mode with 500 kHz / 50% duty cycle generated by the Piccolo controller.
This half-bridge topology allows for more efficient use of the transformer core than the flyback or forward
converters. The transformer has two secondaries, each generating 8.7 V (required output = 8 V with a
diode drop of 0.7 V). A voltage doubler has been used to generate 16 V from the secondary generated 8
V. Each transformer is used to power TOP and BOTTOM IGBTs of each phase.
+15V R_BOT

C
D68
RB160M-60TR

A
C105 10µF C108 C106
C109 47uF
+15V 10µF
0.1µF

C
D76

R232 RB160M-60TR

A
0R
GATE_R_BOT_GND
Half Bridge converter : SMPS
D42 C111
C112 C113 47uF
C47 C49 A C D77 10µF 0.1µF
10µF 0.33 µF +24V RB160M-60TR
SK310A-LTP C A
-8V R_BOT
1

U16
DGND DGND
2 C88
VDD

HB D43 +15V R
R124 0R 7 3.3uF
HI_PWM HI C A
C110 U15
T2
HS 3 8

C
7
8
R125 0R 8 SK310A-LTP
LI_PWM LI 0.1µF D78
3 HSG R89 0R R90 17.8 ohm 2 RB160M-60TR
HO
9
1

A
5 4 HS 13
NC HS 6
C114 10µF C116 C115
5 C126
6 10 LSG LS1 5 10µF 47uF
NC LO R92
VSS

R91 17.8 ohm 4 14 0.1µF

C
0R Transformer_SMPS D79
UCC27211DPRT D44 750313734 RB160M-60TR
9

C A CSD88537ND C97

A
3.3uF
GATE_R_TOP_GND
SK310A-LTP
DGND C136
C143 C147 47uF
DGND DGND 10µF 0.1µF

C A
-8V R

D80
RB160M-60TR

Figure 13. Isolated Power Supply

During the turn-on and turn-off of IGBT, gate driver requires instant peak current from its power supply for
a short period of time, so it is important to use proper by-pass capacitors for the power supply. To achieve
the minimum output ripple with high-current load transients, a 47-μF capacitor at each of the output on the
secondary side is used.

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6.5.1 Transformer Specification

• Two isolated outputs with VOUT1 = 8.7 V at 250 mA and VOUT2 = 8.7 V at 250 mA
• Switching frequency = 500 kHz
• Primary to secondary isolation = 7.4 kV for 1.2/50-µs impulse voltage
• Type test voltage:
– Primary to Secondary = 3.6 kVRMS
– Secondary1 to Secondary2 = 1.8 kVRMS
• Spacing:
– Primary to Secondary clearance = 8 mm
– Secondary1 to Secondary2 clearance = 5.5 mm
– Creepage distance = 9.2 mm
• Functional Isolation Primary and secondary : 1.5-kV DC
• DC isolation between secondaries: 1.5-kV DC

Figure 14. Half-Bridge Transformer Symbol

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6.6 Design of 24-V to 15-V and 5-V Step-Down DC-DC Converter

The 15-V regulated power supply for the half-bridge driver and 5 V are derived using the TPS54286
switching converter. The TPS54286 device is a dual step-down (buck) regulator with an integrated high-
side and low-side n-channel MOSFET. This operates in constant switching frequency, current mode
control which reduces output capacitance, and also reduces the complexity of compensation design. The
design specifications of the step-down converter are given Table 2. The schematic of the step-down
converter is shown in Figure 15.

Table 2. Design Specifications of Step-Down Converter

PARAMETER SPECIFICATION
Output voltage 15 V and 5 V
Maximum output current 150 mA and 500 mA
Input voltage 24 V pre-regulated
Output voltage ripple 0.5% of VOUT

+24V +24V
C117 C118

U17 TPS54286PWP
10µF 10µF

GND 1 14 GND
PVDD1 PVDD2
+15V C119 C120
R93 2 13 R94 +5V
L1 BOOT1 BOOT2 L2
100uH 0.5A 3.3R 3.3R 47uH 1.5A
0.033µF 3 12 0.033µF
SW1 SW2
+15V
C121 5 11 C122
EN1 BP

C
SK310A-LTP
C

C127 1nF 1nF

R97 6 10 R95 0R D20 C124
C123 D21 EN2 SEQ C125
51.1K GND DNP SK310A-LTP 10µF
4.7µF 4.7µF +5V 4.7µF
7 9 R96

A
R98 FB1 ILIM2
A

C128 10R
10R
DNP
PWPD

4 8 R100
R101 GND FB2 R99 4.7µF
C30 20K
2.87K 0R
0.01µF
DNP
15

GND
DNP R102 GND
C32 3.83K
GND
0.01µF
GND

GND
GND

Figure 15. 24-V to 15-V and 5-V Step-Down Converter

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6.6.1 Circuit Design

6.6.1.1 Output Inductor Selection (LO)

To calculate the minimum value of the output inductor,
For 5-V output
V OUT + V FD
Dmin »
V IN(max ) + V FD
(6)
15 V + 0.7 V
D min » » 0.23
24 V + 0.7 V
V IN(max ) - V OUT 1
L min » ´ D min ´
I LRIP(max ) f SW
(7)
24 - 5 1
L min » ´ 0.23 ´ = 48.71 mH » 47 mH
0.15 600 ´ 103
For 15-V output
15 V + 0.7 V
D min » » 0.635
24 V + 0.7 V
24 V - 15 V 1
L min » ´ 0.635 ´ = 95.25 mH » 100 mH
0.1 600 ´ 103
Ripple current for 15 V
V IN(max ) - V OUT 1
I RIPPLE » ´ Dmin ´
L f SW (8)
24 V - 15 V 1
I RIPPLE » ´ 0.635 ´ = 0.095 A » 0.1 A
100 mH 600 ´ 103
2
I L(rms ) = (I ( ) ) + 121 (I
L avg RIPPLE
2
) (9)

1
I L(rms ) = (0.2 )2 + (0.1)2 = 0.202 A
12
Ripple current for 5 V
24 V - 5 V 1
I RIPPLE » ´ 0.230 ´ = 0.154 A » 0.15 A
47 mH 600 ´ 103
1
I L(rms ) = (0.5 )2 + (0.15 )2 = 0.501 A
12

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6.6.1.2 Output Capacitor

The internal compensation of the TPS54286 limits the selection of the output capacitors. Internal
compensation has a double zero resonance at about 6 kHz, so the output capacitor is selected by
Equation 10.
For 15 V
1
COUT = 2
2
(
4 ´ p ´ f RES ) ´L (10)
1
COUT = 2
= 7.04 mF
2
(
4 ´ p ´ 6 ´ 10 3
) ´ 100 mH
For 5 V
1
COUT = 2
= 14.97 mF
(
4 ´ p2 ´ 6 ´ 103 ) ´ 47 mH
6.6.1.3 Output Voltage Regulation
For this design feedback divider resistors (R97, R100) are 20K and 51.1K. The lower resistor R102 and
R103 are found using the following equations.
V FB ´ R97
R102 =
V OUT1 - V FB (11)

0.8 ´ 51.1 ´ 103

R102 = = 2.873 kW
15 V - 0.8
V FB ´ R97
R103 =
V OUT1 - V FB (12)
3
0.8 ´ 20 ´ 10
R103 = = 3.809 kW
5 - 0.8

6.6.1.4 Bootstrap circuit

A 3.3-nF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. Use
a ceramic capacitor with X5R or better grade dielectric. The capacitor should be rated 50 V or higher.
A small resistor with value between 1 and 3 Ω to be placed in series with the bootstrap capacitor; this
reduces the rising edge ringing at the SW node.

6.6.1.5 Snubber
Fast switching and parasitic inductance and capacitance results in a voltage ringing at the SW node. If the
ringing results in excessive voltage on the SW node or erratic operation of the converter, an R-C snubber
(C = between 330 pF and 1 nF, R = 10 Ω) may be used to dampen the ringing at the SW node to ensure
proper operation over the full load range.

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6.7 Design of 5-V isolated DC-DC Converter

The AMC1200 requires isolated power supply for powering its input section. The SN6501 is used as a
switching device to generate a 5-V isolated output.

Table 3. Specifications for Selection of 5-V DC-DC Converter

PARAMETER SPECIFICATION
Output voltage 5V
Output current required 10 mA
Input voltage 5V
Output voltage ripple 0.5% of VOUT

The SN6501 is a monolithic oscillator and power-driver, specifically designed for isolated power supplies
in isolated interface applications with small form factor. It drives a low-profile, center-tapped transformer
primary from a 3.3-V or 5-V DC power supply. The SN6501 consists of an oscillator followed by a gate
drive circuit that provides the complementary output signals to drive the ground referenced N-channel
power switches. The internal logic ensures break-before-make action between the two switches.
Features:
• Push-pull driver for small transformers
• Single 3.3-V or 5-V supply
+5V

C36 C37
10uF 0.1µF

+5V
U19 DGND D40 +5V_ISO
T1 6 A C R200 47 Ohm
4 3 1
GND D2

C
MBR0520LT3G C41
2 2 5 C43 C44 D63
VCC 10µF 0.1µF 10µF
D41 DNP MM3Z5V1B

A
5 1 3
GND D1 4 A C
Wurth Elektronik
SN6501DBVR 750313734 MBR0520LT3G GND_ISO

DGND

Figure 16. Isolated 5-V Converter

Transformer Selection
To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product
applied by the SN6501. The maximum voltage delivered by the SN6501 is the nominal converter input
plus 10%. The maximum time voltage is applied to the primary is half the period of the lowest frequency at
the specified input voltage. Therefore, the transformer’s minimum V-t product is determined using
Equation 13.
T V IN-max
Vt min ³ V IN-max ´ max =
2 2 ´ f min (13)
5.5 V
Vt min ³ = 9.1 Vms
2 ´ 300 kHz
Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typical
footprints of 10 × 12 mm. Other important factors to be considered in transformer selection are isolation
voltage, transformer wattage, and turns ratio.
Transformer Turns Ratio Estimation
V F-max + V DO -max + V O -max
n min = 1.031 ´
V IN-min - R DS -max ´ I D-max (14)

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Table 4. Transformer Specifications

PARAMETERS TEST CONDITIONS VALUE
DC resistance 1-3 @ 20°C 0.419 Ω max
DC resistance 6-4 @ 20°C 0.335 Ω max
Inductance 1-3 100 kHz,10-mV AC, LS 340 µH min.
Dielectric 1-6 6250 VRMS, 1 second 5000 VRMS, 1 minute
Turns ratio (6-4): (1-3) 1.1:1, +-2%

Figure 17. Isolated Transformer Construction

6.8 5-V To 3.3-V Regulator

Table 5. Specification of 3.3-V Output LDO

PARAMETER SPECIFICATIONS
Input voltage 5V
Output 3.3 mA
Output current 350 mA

The LP38691 is selected is based on specifications outlined in Table 5. The LP3869x is a low-dropout
CMOS linear regulator providing tight output tolerance (2% typical), extremely low-dropout voltage (250
mV at 500-mA load current VOUT = 5 V), and excellent AC performance using ultra-low equivalent series
resistance (ESR) ceramic output capacitors.

Figure 18. 3.3-V Circuit

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6.9 Status Indications

The ISO5852S fault and ready indications are shorted and connected to two LED indications as shown in
Figure 19.

Figure 19. Status Indication Through LED

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6.10 LaunchPad Connections

The C2000 InstaSPIN™ Piccolo LaunchPad is used for controlling the inverter.
The LaunchPad has following connections to the power stage:
• Thermistor feedback from the IGBT module
• DC bus voltage feedback
• FAULT ready
• PWM enable and RESET signals from the ISO5852S
• Relay_Enable signal
• Fan drive signals
• PWM signals for half-bridge SMPS
• PWM signals for gate driver
PWM_EN is used to control the buffer providing PWM signals to ISO5852S.

Figure 20. LaunchPad Connections for C2000 Piccolo LaunchPad

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7 System Test Results

7.1 Power Supply

7.1.1 3.3-V LDO Output (U18)

Figure 21. Output Voltage of 3.3-V LDO With Load of 100 Figure 22. Ripples in 3.3-V LDO Output With Load of 100
mA mA

7.1.2 Buck Converter Outputs TPS54286PWP (U17)

7.1.2.1 15-V Output

Figure 23. 15-V Supply With Load of 15 mA Figure 24. Ripples in 15-V Supply With Load of 15 mA

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7.1.2.2 5-V Output

Figure 25. 5-V Supply With Load of 150 mA Figure 26. Ripples on 5 V With Load of 150 mA

7.1.3 Isolated 5-V Output SN6501DBVR (U19)

Figure 27. 5-V Isolated Supply Output With Load of 7 mA Figure 28. Ripple on 5-V Isolated Supply Output With
Load of 7 mA

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7.1.4 Half-Bridge Gate Driver supply

7.1.4.1 16-V Output From Half-Bridge SMPS

Figure 29. 16 V during power ON Figure 30. Ripples on 16 V at 2.5-A Source Current and
4.5-A Sink current

Figure 31. Ripples on 16 V at 2.5-A Source Current Figure 32. Ripples on 16 V at 4.5-A Sink Current

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7.1.4.2 –8-V Output From Half-Bridge SMPS

Figure 33. –8 V During Power ON Figure 34. Ripple on –8 V

Figure 35. Ripple on –8 V at 2.5-A Source Current Figure 36. Ripple on –8 V at 4.5-A Sink Current

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7.2 Power ON Test Without External BJT/MOSFET Buffer

The undervoltage lockout feature monitors the secondary voltage rail and prevents the IGBT operating
with insufficient gate voltage (VGE-ON) by forcing OUTH/OUTL to low (during power-up else VCC2 drops
below 12 V). In Figure 37 and Figure 38, the gate driver output is held low (CH2) until VCC (CH3)
exceeds 12 V. CH1 represents the PWM input of ISO5852S.

Figure 37. Gate Driver Output During Power ON With Figure 38. Gate Driver Output (Zoomed)
Unipolar Supply

NOTE: CH1: PWM from controller, CH2: Gate driver output, CH3: 16-V supply

Figure 39. Gate Driver Output During Power ON With Figure 40. Gate Driver Output (Zoomed)
Bipolar Supply

NOTE: CH1: –8-V supply, CH2: Gate driver output, CH3: 16-V supply

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7.3 Power ON Test With External BJT Buffer

Figure 41. External BJT Buffer Output During Power ON Figure 42. Gate Driver Output (Zoomed)
With Unipolar Supply

NOTE: CH1: PWM from controller, CH2: Gate driver output, CH3: 16-V supply

Figure 43. Gate Driver Output During Power ON With Figure 44. Gate Driver Output (Zoomed)
Bipolar Supply

NOTE: CH1: –8-V supply, CH2: Gate driver output, CH3: 16-V supply

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7.4 2.5-A/5-A Sink and Source Current With Bipolar Supply Without BJT Buffer (Infineon
Module)
Figure 45 through Figure 47 show the sink and source currents delivered directly by ISO5852S.
Test conditions:
• RG (ON): 7.5 Ω
• RG (OFF): 0.0 Ω
• IGBT module: Infineon FS200R12KT4R_B11
• Gate charge (QG): 1.65 μC
• Internal resistance: 3.5 Ω
• Input capacitance Cies: 14 nF

Figure 45. Gate Driver Output — 2.5-A Source Current Figure 46. Gate Driver Output — 4.5-A Sink Current

Figure 47. Source and Sink Current

NOTE: CH2: Gate current, CH3: Gate driver output

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7.5 PWM Signal Delay

Section 7.5.1 and Section 7.5.2 show the propagation delay between the Piccolo controller and the gate
driver.

PWM ISO5852S
Controller PWM buffer
IGBT gate driver

Figure 48. Piccolo Controller and Gate Driver Diagram

7.5.1 Delay Between PWM Buffer Input and PWM Buffer Output

Figure 49. Propagation Delay of PWM Buffer (R-Top) Figure 50. Propagation Delay of PWM Buffer (R-Top)
(Rising Edge) (Falling Edge)

Figure 51. Propagation Delay of PWM Buffer (R-Bot) Figure 52. Propagation Delay of PWM Buffer (R-Bot)
(Rising Edge) (Falling Edge)

NOTE: CH1: PWM from controller, CH2: PWM buffer output, CH3: Current buffer output

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Table 6. Delay Between PWM Signals

PWM BUFFER INPUT AND PWM BUFFER OUTPUT TIME (ns)
R_Top (Rising) 5.0
R_Top (Falling) 5.0
R_Bottom (Rising) 3.0
R_Bottom (Falling) 4.0

7.5.2 Delay Between PWM Buffer Input and Gate Driver Output

Figure 53. Gate Driver Propagation Delay R_Top (Rising) Figure 54. Gate Driver Propagation Delay R_Top
(Falling)

Figure 55. Gate Driver Propagation Delay R_Bottom Figure 56. Gate Driver Propagation Delay R_Bottom
(Rising) (Falling)

NOTE: CH1: PWM from controller, CH2: PWM buffer output, CH3: Current buffer output

Table 7. Delay Between PWM Signals

PWM BUFFER INPUT AND GATE DRIVER OUTPUT TIME (ns)
R_Top (Rising) 84.0
R_Top (Falling) 80.0
R_Bottom (Rising) 82.0
R_Bottom (Falling) 81.0

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7.6 Induced Voltage at Gate for dV/dt of 2.5 kV/μs With 10-m Motor Cable

7.6.1 Active Miller Clamp Disabled

Figure 57. 2.5-kV/μs Inverter dV/dt Figure 58. Induced Voltage at 2.5-kV/μs dV/dt

NOTE: 2.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp disabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Figure 59. 2.5-kV/μs Inverter dV/dt Figure 60. Induced Voltage at 2.5-kV/μs dV/dt

NOTE: 2.5-kV/μs inverter output and induced voltage at gate of bottom IGBT with active miller clamp
disabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Table 8. Summary of Induced Voltage for 2.5-kV/μS dV/dt (Active Miller Clamp Disabled)
INDUCED VOLTAGE AT THE BOTTOM IGBT
TEST CONDITIONS
(POSITIVE PEAK IN VOLTS)
Active Miller clamp disabled
3.4
Cge(Ext)=0nF
Active Miller clamp disabled
2
Cge(Ext)=10nF

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7.6.2 Active Miller Clamp Enabled

Figure 61. 2.5-kV/μs Inverter dV/dt Figure 62. Induced Voltage at 2.5-kV/μs dV/dt

NOTE: 2.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp enabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Figure 63. 2.5-kV/μs Inverter dV/dt Figure 64. Induced Voltage at 2.5-kV/μs dV/dt

NOTE: 2.5-kV/μs inverter output and induced voltage at gate of bottom IGBT with active miller clamp
enabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Table 9. Summary of Induced Voltage for 2.5-kV/µs dV/dt (Active Miller Clamp Enabled)
INDUCED VOLTAGE AT THE BOTTOM IGBT
TEST CONDITIONS
(POSITIVE PEAK IN VOLTS)
Active Miller clamp enabled.
0.4
Cge(Ext) = 0 nF
Active Miller clamp enabled
0.4
Cge(Ext) = 10 nF

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7.7 Induced Voltage at Gate for dV/dt of 5 kV/μs With 10-m Motor Cable

7.7.1 Active Miller Clamp Disabled

Figure 65. 5-kV/μs Inverter dV/dt Figure 66. Induced Voltage at 5-kV/μs dV/dt

NOTE: 5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp disabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Figure 67. 5-kV/μs Inverter dV/dt Figure 68. Induced Voltage at 5-kV/μs dV/dt

NOTE: 5-kv/µs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp disabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Table 10. Summary of Induced Voltage for 5-kV/µs dV/dT (Active Miller Clamp Disabled)
INDUCED VOLTAGE AT THE BOTTOM IGBT
TEST CONDITIONS
(POSITIVE PEAK IN VOLTS)
Active Miller clamp disabled
4
Cge(Ext)=0nF
Active Miller clamp disabled
2.8
Cge(Ext)=10nF

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7.7.2 Active Miller Clamp Enabled

Figure 69. 5-kV/μs Inverter dV/dt Figure 70. Induced Voltage at 5-kV/μs dV/dt

NOTE: 5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp enabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Figure 71. 5-kV/μs Inverter dV/dt Figure 72. Induced Voltage at 5-kV/μs dV/dt

NOTE: 5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp enabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Table 11. Summary of Induced Voltage for 5-kV/μs dV/dt (Active Miller Clamp Enabled)
INDUCED VOLTAGE AT THE BOTTOM IGBT
TEST CONDITIONS
(POSITIVE PEAK IN VOLTS)
Active Miller clamp enabled
0.44
Cge(Ext) = 0 nF
Active Miller clamp enabled
0.44
Cge(Ext) = 10 nF

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7.8 Induced Voltage at Gate for dV/dt of 7.5 kV/μs With 10-m Motor Cable

7.8.1 Active Miller Clamp Disabled

Figure 73. 7.5-kV/μs Inverter dV/dt Figure 74. Induced Voltage at 7.5-kV/μs dV/dt

NOTE: 7.5-kV/μs inverter output and induced voltage at the bottom IGBT - active miller clamp
disabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Figure 75. 7.5-kV/μs Inverter dV/dt Figure 76. Induced Voltage at 7.5-kV/μs dV/dt

NOTE: 7.5-kV/μs inverter output and induced voltage at the bottom IGBT with active miller clamp
disabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Table 12. Summary of Induced Voltage for 7.5-kV/μs dV/dt (Active Miller Clamp Disabled)
INDUCED VOLTAGE AT THE BOTTOM IGBT
TEST CONDITIONS
(POSITIVE PEAK IN VOLTS)
Active Miller clamp disabled
4
Cge(Ext) = 0 nF
Active Miller clamp disabled
3.2
Cge(Ext) = 10 nF

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7.8.2 Active Miller Clamp Enabled

Figure 77. 7.5-kV/μs Inverter dV/dt Figure 78. Induced Voltage at 7.5-kV/μs dV/dt

NOTE: 7.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp enabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Figure 79. 7.5-kV/μs Inverter dV/dt Figure 80. Induced Voltage at 7.5-kV/μs dV/dt

NOTE: 7.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT - active miller
clamp enabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Table 13. Summary of Induced Voltage for 7.5-kV/μs dV/dt (Active Miller Clamp Enabled)
INDUCED VOLTAGE AT THE BOTTOM IGBT
TEST CONDITIONS
(POSITIVE PEAK IN VOLTS)
Active Miller clamp enabled
0.72
Cge(Ext) = 0 nF
Active Miller clamp enabled
0.56
Cge(Ext) = 10 nF

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7.9 Maximum Achievable dV/dt Without External BJT Buffer

Figure 81. Max dV/dt and Induced Voltage Without External Buffer With 10-m Motor Cable (Bipolar)

NOTE: CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Maximum dV/dt achieved without external BJT buffer: 8.47 kV/μs

Test conditions:
• RG (ON): 2.2 Ω
• RG (OFF): 2.2 Ω
• IGBT module: CM150TX-24S1_MITSUBISHI
• Gate charge (QG): 315 nC
• Internal resistance: 13 Ω
• Input capacitance CIES: 15 nF

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7.10 Current Through Clamp Pin

Figure 82. Current Through Clamp Pin

Test conditions:
• External buffer: without BJT
• Supply: Unipolar
• RG (ON): 2.2 Ω
• RG (OFF): 2.2 Ω
• IGBT module: CM150TX-24S1_MITSUBISHI
• Gate charge (QG): 315 nC
• Internal resistance: 13 Ω
• Input capacitance CIES: 15 nF

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7.11 Validation of Gate Signals With External Cable (Without BJT Buffer)

Figure 83. Gate signal at Gate of IGBT With 100-cm External Cable

NOTE: CH1: Gate driver output, CH3: Vce of bottom IGBT

Probe point

R1 Discharge
Out H 100 cm

cable
Gate driver R3 D1
ISO58252 R4 I1 IGBT
R2 gate
Out L

Charge Inverter
module

Figure 84. Block Diagram for Measurement of Gate Signal With External Cable

7.12 DESAT Signal During Normal Operation

Figure 85. DESAT During Normal Operation (Zoomed) Figure 86. DESAT During Normal Operation

NOTE: CH1: Bottom gate driver output, CH2: DESAT signal, CH3: Vce of bottom IGBT

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7.13 Short Circuit Test — Hard Switched

NOTE: All the tests in Section 7.13 and Section 7.14 were performed using engineering samples of
ISO5852S. The final silicon has a higher pulldown drive during soft shutdown when
compared to the engineering samples, resulting in lower soft shutdown time for given Qg of
the IGBT die. Refer to the latest datasheet of ISO5852S on TI Website at
http://www.ti.com/product/ISO5852S

Figure 87 shows the block diagram of hard-switched fault setup.

+24-V DC

+800-V DC IGBT power

module
SMPS
HALF +16 V
PWMs
BRIDGE Reinforced
-8 V
C2000 LaunchPAD interface

SMPS isolated
+16 V IGBT gate
driver ±
-8 V ISO5852S
Gate
Inverter PWM signals
drive
signals

Short between
DC bus sensing inverter output
to DC (-ve)

NTC output

Figure 87. Block Diagram of Short Circuit Setup (Hard Fault Switch)

A hard fault switch short circuit test was performed using the power module CM150TX-
24S1_MITSUBISHI. This test is performed such that one arm of the inverter bottom IGBT already has a
short (from Figure 87, Y phase output is connected to DC negative), during the same turning ON the top
IGBT (Y_Top) to know the performance of DESAT detection.
Test conditions:
• Short circuit connection: Y-phase inverter output to DC negative
• Motor connected: NO
• Inverter dV/dT: 2.5 kV/μs, 5 kV/μs, 7.5 kV/μs
• IGBT module: CM150TX-24S1_MITSUBISHI
• Gate charge (QG): 315 nC
• Internal resistance: 13 Ω
• Input capacitance CIES: 15 nF

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7.13.1 Hard Switched Fault With Inverter dV/dt of 2.5kV/μs

Figure 88. DESAT Activation to Gate Driver Turn OFF Figure 89. DESAT Activation to Fault Indication

Figure 90. Gate Driver Output During Soft Shutdown

NOTE: CH1: Fault signal, CH2: PWM from Controller, CH3: DESAT signal, CH4: Gate driver output

Figure 91. Voltage Across (Vce) Top IGBT Figure 92. IC — During Short circuit

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NOTE: CH1: Short circuit current, CH2: PWM from Controller, CH3: DESAT signal, CH4: Vce of top
IGBT

Table 14. Summary of Short Circuit Test of Hard Switched Fault with 2.5 kV/µs
PARAMETER VALUE
DESAT activation to gate driver turn OFF 360.0 ns
DESAT activation to Fault indication 1.16 µs
Soft shutdown time 10.2 µs
Short circuit current 1.04 kA
Dip in Vce 220 V

7.13.2 Hard Switched Fault With Inverter dV/dt of 5 kV/μs

Figure 93. DESAT Activation to Gate Driver Turn OFF Figure 94. DESAT Activation to Fault Indication

Figure 95. Gate Driver Output During Soft Shutdown

NOTE: CH1: Fault signal, CH2: PWM from Controller, CH3: DESAT signal, CH4: Gate driver output

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Figure 96. Voltage Across (Vce) Top IGBT and IC– During Short Circuit

NOTE: CH1: Short circuit current, CH2: PWM from Controller, CH3: DESAT signal, CH4: Vce of top
IGBT

Table 15. Summary of Short Circuit Test of Hard Switched Fault with 5 kV/µs
PARAMETER VALUE
DESAT activation time to gate driver turn OFF 360 ns
DESAT activation to fault output 800 ns
Soft shutdown time 10.5 µs
Short circuit current 1.05 kA
Dip in Vce 240 V

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7.13.3 Hard Switched Fault With Inverter dV/dt of 7.5 kV/μs

Figure 97. DESAT Activation to Gate Driver Turn OFF Figure 98. DESAT Activation to Fault Indication

NOTE: CH1: Fault signal, CH2: PWM from Controller, CH3: DESAT signal, CH4: Gate driver output

Figure 99. Voltage Across (Vce) Top IGBT Figure 100. IC– During Short Circuit

NOTE: CH1: Short circuit current, CH2: PWM from Controller, CH3: DESAT signal, CH4: Vce of top
IGBT

Table 16. Summary of Short Circuit Test of Hard Switched Fault with 7.5 kV/µs
PARAMETER VALUE
DESAT activation to gate driver turn OFF 760 ns
DESAT activation to fault 1.12 µs
Soft shutdown time 10 µs
Short circuit current 1.08 kA
Dip in Vce 270 V

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7.14 Short Circuit Test — Fault Under Load

A fault under load short circuit test was performed using the power module CM150TX-4S1_MITSUBISHI.
This test is conducted using a add on module for the short circuit consisting of high power IGBT
connected between one of the phase output to DC negative. Refer Figure 101 for the test setup.

Figure 101. Setup for Short Circuit Test — Fault Under Load

7.14.1 Fault Under Load Short Between Phase to DC –ve for 2.5-kV/µs Inverter Output
Test conditions:
• Short circuit connection: R phase inverter output to DC negative
• Motor connected: Yes
• Inverter dV/dT: 2.5 kV/µs
• IGBT module: CM150TX-24S1_MITSUBISHI
• Gate charge (QG): 315 nC
• Internal resistance: 13 Ω
• Input capacitance CIES: 15 nF

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+24-V DC

+800-V DC IGBT power

module
SMPS
HALF +16 V
PWMs
BRIDGE Reinforced
-8 V
C2000 LaunchPAD interface

SMPS isolated
+16 V IGBT gate
driver ±
-8 V 3N ACIM
ISO5852S
Gate
Inverter PWM signals
drive
signals

DC bus sensing

Add on module for

NTC output short circuit test

Isolated gate
driver

800 V -ve

Figure 102. Block Diagram of Fault Under Load Test Short Between Phase to DC –ve

Figure 103. DESAT Activation to Fault Output Figure 104. Gate Driver Output During Soft Shutdown

Table 17. Summary of Short Circuit Test — Fault Under Load for 2.5 kV/µs
(Phase Output to DC Negative)
PARAMETER VALUE
DESAT activation to gate driver turn OFF 1.30 µs
Soft shutdown 14.80 µs

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7.14.2 Fault Under Load — Short Circuit Between Phase to Phase

A fault under load short circuit test was performed using Mitsubishi power module CM150TX-24S1. This
test is conducted using a add-on module for the short circuit consisting of high-power IGBT connected
between R_phase and Y_phase of inverter output (see Figure 105).

+24-V DC

+800-V DC IGBT power

module
SMPS
HALF +16 V
PWMs
BRIDGE Reinforced
-8 V
C2000 LaunchPAD interface

SMPS isolated
+16 V IGBT gate
driver ±
-8 V 3N ACIM
ISO5852S
Gate
Inverter PWM signals
drive
signals

DC bus sensing

Add on module for

NTC output short circuit test

Isolated gate
driver

Figure 105. Block Diagram of Fault Under Load Test — Phase-to-Phase Short (dV/dt: 2.5 kV/µs)

Test conditions:
• Short circuit connection: Between R_phase and Y_phase
• Motor connected: Yes
• Inverter dV/dT: 2.5 kV/µs
• Cable length: 10 meters
• IGBT module: CM150TX-24S1_MITSUBISHI
• Gate charge (QG): 315 nC
• Internal resistance: 13 Ω
• Input capacitance CIES: 15 nF

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Figure 106. Gate Driver Output During Soft Shutdown Figure 107. DESAT Activation to Gate Driver Turn Off

NOTE: CH1: Fault signal, CH2:PWM from Controller, CH3: DESAT signal, CH4: Gate driver output

Figure 108. IC– During Short Circuit Fault Under Load

NOTE: CH1: Short circuit current, CH2: PWM from Controller, CH3: DESAT signal, CH4: Gate driver
output

Table 18. Summary of Short Circuit Test for Fault Under Load for 2.5 kV/µs (Phase-to-Phase Short)
PARAMETER VALUE
DESAT activation to gate driver turn OFF 420.0 ns
Soft shutdown of gate driver output 11.20 µs
Peak current 980 A

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7.15 EMC Test

7.15.1 Electrical Fast Transient (EFT) Test

EFT pulses were applied to motor cable using capacitive coupling clamp as per IEC 61000-4-4. This test
was conducted for multiple levels of fast transient voltages (±1 kV, ±2 kV, ±3 kV, ±4 kV) at 5 kHz for
duration of 60 seconds.
Different configurations used during testing are listed in Table 19:

Table 19. EFT Test Configurations

UUT/AUX EQUIPMENT
TEST CONFIGURATION MOTOR CABLE REFERENCE
LOCATION
1 Shielded Ground plane Figure 109
2 Shielded 10-cm isolated from plane Figure 110
3 Unshielded Ground plane Figure 111
4 Unshielded 10-cm isolated from plane Figure 112

Test setup:
• DC bus voltage: 400 V
• Auxiliary unit power rating: 2.2 kW
• Load condition: No load
• Motor rpm: 750 rpm
• Cable length: 10 meters
• EFT test equipment: emtest UCS 500N
• Capacitor coupling network

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Figure 109. Test Configuration 1 Figure 110. Test Configuration 2

Figure 111. Test Configuration 3 Figure 112. Test Configuration 4

Table 20. EFT Test Results

TEST RESULTS
EFT PULSES DURATION
Config:1 Config:2 Config:3 Config:4
1 kV 60 seconds PASS PASS PASS PASS
–1 kV 60 seconds PASS PASS PASS PASS
2 kV 60 seconds PASS PASS PASS PASS
–2 kV 60 seconds PASS PASS PASS PASS
3 kV 60 seconds PASS PASS PASS PASS
–3 kV 60 seconds PASS PASS PASS PASS
4 kV 60 seconds PASS PASS PASS PASS
–4 kV 60 seconds PASS PASS PASS PASS

Test pass refers to motor running continuously (without unusual sound) with no malfunctioning observed in
the power stage (includes IGBT gate drivers), thereby meeting performance class B requirements as per
IEC61800-3.

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7.15.2 Electrostatic Discharge (ESD) Test

ESD pulses were applied (contact discharge) to the heat sink while the power stage was running the
motor to check for malfunctions. CD was applied on the heat sink close to the IGBT gate drivers. ESD
pulses were applied at multiple levels (±2 kV, ±4 kV, ±6 kV, ±8 kV) with 10 pulses on each polarity and
level. IEC 61000-4-2 has been used as reference for the test method.
Different configurations used during testing are listed in Table 21:

Table 21. ESD Test Configurations

TEST CONFIGURATION UUT/AUX EQUIPMENT LOCATION REFERENCE
1 Insulated sheet Figure 113 and Figure 114
2 Ground reference plane Figure 116
3 10 cm isolated from reference Figure 115

Test setup:
• DC bus voltage: 400 V
• Auxiliary unit power rating: 2.2 kW
• Load condition: No load
• Motor rpm: 750 rpm
• Cable length: 10 meters (Unshielded)
• ESD test equipment: emtest UCS 500N

Table 22. ESD Test Results

TEST RESULTS
ESD PULSES DURATION
Config:1 Config:2 Config:3
2 kV 10 pulses PASS PASS PASS
–2 kV 10 pulses PASS PASS PASS
4 kV 10 pulses PASS PASS PASS
–4 kV 10 pulses PASS PASS PASS
6 kV 10 pulses PASS PASS PASS
–6 kV 10 pulses PASS PASS PASS
8 kV 10 pulses PASS PASS PASS
–8 kV 10 pulses PASS PASS PASS

A test pass refers to the motor running continuously (without unusual sound) with no malfunctioning
observed in the power stage (includes IGBT gate drivers), thereby meeting performance class B
requirements as per IEC61800-3.

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Figure 113. EUT/AUX Equipment on Insulated Sheet

Figure 114. Test Configuration 1 Figure 115. EUT/AUX Equipment Isolated From
Reference Plane by 10 cm

Figure 116. Test Configuration 2: EUT/AUX Equipment on Reference Plane

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8 Design Files

8.1 Schematics
To download the schematics, see the design files at TIDA-00195.
CN1 D1
1 A C

Te rminal bush RHRG75120 R208

200K
C3

680µF
R209
200K
IGBT Module
U1

R212
C7 200K FS200R12KT4R
680µF C154 30 27
FILM CAP DC_VOLT_POS1 MOT_R_PHASE1
R213 0.22µF 31 28 MOTOR_R_PHASE
200K DC_VOLT_POS2 MOT_R_PHASE2
CN11
1 DC_POS 32 29
DC_VOLT_POS3 MOT_R_PHASE3

C
Te rminal bush 16
R210 D2 DC_VOLT_POS4
200K RHRG75120
17
DC_VOLT_POS5
C6 CN12

A
680µF 1 BRAKE 18
DC_VOLT_POS6
R211 26
MOT_Y_PHASE3

C
200K
25 MOTOR_Y_PHASE
Q1 MOT_Y_PHASE2
INRUSH_BYPASS GATE_BRAKE G 33
DC_VOLT_NEG1
24
MOT_Y_PHASE1
APT70GR120L 34
DC_VOLT_NEG2

E
RT1
100R_PTC 35
DC_VOLT_NEG3
t°

B59109J0130A020
15
DC_VOLT_NEG6
CN2
1 14 21
DC_VOLT_NEG5 MOT_B_PHASE1
13 22 MOTOR_B_PHASE
DC_VOLT_NEG4 MOT_B_PHASE2
23
MOT_B_PHASE3
GATE_R_TOP 1
GATE_R_TOP
GATE_R_TOP_RTN 2
GATE_R_TOP_RTN 19 NTC_1
NTC_1
GATE_Y_TOP 5
PGND GATE_Y_TOP 20 NTC_2
NTC_2
GATE_Y_TOP_RTN 6
GATE_Y_TOP_RTN
GATE_B_TOP 9
GATE_B_TOP DGND
GATE_B_TOP_RTN 10
GATE_B_TOP_RTN

GATE_R_BOTTOM 3
GATE_R_BOTTOM
GATE_R_BOT_RTN 4
GATE_R_BOT_RTN
GATE_Y_BOTTOM 7
GATE_Y_BOTTOM
Motor connector
GATE_Y_BOT_RTN 8
GATE_Y_BOT_RTN
MOTOR_B_PHASE
1
GATE_B_BOTTOM 11 MOTOR_Y_PHASE
GATE_B_BOTTOM 2
MOTOR_R_PHASE
GATE_B_BOT_RTN 12 3
GATE_B_BOT_RTN
CN3
1986242-3
IC_FS200R12KT4R

Figure 117. IGBT Module

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+15V R

3V3 NOTE:
Gate Driver Top IGBT R
C172 C25 C28
DNP 3V3 U7 Unipolar supply- Populate J1 only
1µF 0.1µF
2 Bipolar supply- Populate J2 only
R60 10uF
10R R219 15 5
0R VCC1 VCC2
GATE_R_TOP_GND
C31
R61 1 C29

1
IN+_R_TOP 0.1µF
9 3
0R 4.7µF GND1 GND2 C173 J1
16 C174 C35 C33
PWM_DRV_R_TOP GND1 QPC02SXGN-RC
R62 2
IN-_R_TOP DNP 1µF 1µF 0.1µF
1 10uF
0R VEE2 J2
1 IN+_R_TOP 10 8 TP1
DNP IN+ VEE2 QPC02SXGN-RC

2
R63
0R DGND
VEE_R 2 1 D4 D23
-8V R
R39

1
IN-_R_TOP 11 2 A C A C DC_POS
IN- DESAT
TP37 1k
GL41Y-E3/96 GL41Y-E3/96

1
DGND RDY1 12 7 R34 0R
RDY CLAMP

1
TP44 +15V R D69 D24 C39 J4
C40

RB160M-60TR
200pF 100pF QPC02SXGN-RC

MM3Z12VB
FLT1 13 4 R35 220R

A
FLT OUTH

1
TP17 DNP DNP

2
2
NOTE : RST1 14 6 MJD3055T4
RST OUTL

1
1. Non-inverting Configuration Q6 Q9 GATE_R_TOP_GND
1
2. Inverting Configuration SUD50P08-25L-E3
NOTE:
ISO5852 TP18 DNP To disable DESAT

3
D3
R107 R36 10R C A 3 DNP DESAT Capcitor
Populate umper
J

1
0R R48 0R
R121
2.2R SK310A-LTP DNP
R37 0R 1 2 GATE_R_TOP
J3
QPC02SXGN-RC
R134 DNP C38
R122 2.2R 10nF
0R
NOTE :

3
R38 220R MJD2955T4 3. DNP While testingwith twistedpair
1 Q8 R49
DNP Q7 0R
SUD40N08-16-E3 DNP

2
J16
QPC02SXGN-RC
+15V R_BOT
VEE_R GATE_R_TOP_GND 2 1 GATE_R_TOP_RTN

3
R233
C42 0R DNP All Notes are app
licable for all Gate Driver Sections
3V3 U9 C175 C45
10uF
1µF 0.1µF
10R R220 15 5
VCC1 VCC2
GATE_R_BOT_GND
C46 C48

1
4.7µF 0.1µF
9 3 C176
GND1 GND2 J6
16
DNP
GND1
1µF
C177 C51
10uF C50
QPC02SXGN-RC Gate Driver Bottom IGBT R
1 0.1µF
VEE2 1µF J7
IN+_R_BOT 10 8 TP2
IN+ VEE2 QPC02SXGN-RC

2
DGND
VEE_R_BOT 2 1 D6 D25
-8V R_BOT
R45

1
IN-_R_BOT 11 2 A C A C GATE_R_TOP_RTN
IN- DESAT
TP38 1k
GL41Y-E3/96 GL41Y-E3/96
R40

2
RDY2 12 7

C
RDY CLAMP C57

1
TP19 0R D26 C56 J9
+15V R_BOT D70

RB160M-60TR
200pF 100pF QPC02SXGN-RC
FLT2 13 4

MM3Z12VB
FLT OUTH
1

A
TP20 DNP

1
RST2 14 6
RST OUTL
1

MJD3055T4 GATE_R_BOT_GND
R41 220R 1 Q10 Q13
SUD50P08-25L-E3 R234 3
ISO5852 DNP
0R
3

DNP
1 2 GATE_R_BOTTOM
R135 QPC02SXGN-RC
0R R145 J8
TP21 C55
2.2R DNP D5 10nF
3V3
R42 10R C A
DNP
1

DNP
2 NOTE :
R66 SK310A-LTP 3. DNP While testingwith twistedpair
R146 R161
0R R7 0R
0R 2.2R
R67 1 R235
IN+_R_BOT 0R
DNP
0R R44 220R
PWM_DRV_R_BOT DNP
R822 Q12 J17
3

IN-_R_BOT
MJD2955T4 QPC02SXGN-RC
0R Q11 GATE_R_BOT_GND 2 1 GATE_R_BOT_RTN
1 1
DNP R105 SUD40N08-16-E3 R236 3
0R
0R DNP
2

VEE_R_BOT
DGND

Figure 118. Gate Driver R

60 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System TIDUA15A – June 2015 – Revised August 2015
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+15V Y

3V3
3V3 U20 C178
C52
10uF
C53 Gate Driver Top IGBT Y
2 0.1µF
1µF
R128 10R R214 15 5
0R VCC1 VCC2
GATE_Y_TOP_GND
DNP C58
R1291 C54

1
IN+_Y_TOP 0.1µF
9 3
0R 4.7µF GND1 GND2 C179 J19
16 C59
PWM_DRV_Y_TOP GND1 1µF C180 C61 QPC02SXGN-RC
2 10uF
R130 IN-_Y_TOP DNP 1µF 0.1µF
1
0R VEE2 J20
1 IN+_Y_TOP 10 8 TP4
DNP IN+ VEE2 QPC02SXGN-RC

2
R131
0R VEE_Y 2 1 D45 D46
-8V Y
R132

1
DGND IN-_Y_TOP 11 2 A C A C DC_POS
IN- DESAT
TP39 1k
GL41Y-E3/96 GL41Y-E3/96
R133

1
DGND RDY3 12 7
RDY CLAMP

1
TP22 0R +15V Y C66 J21
D71 D47 C64

RB160M-60TR
200pF 100pF QPC02SXGN-RC
FLT3 13 4

MM3Z12VB
A

A
FLT OUTH DNP

1
TP23

2
2
NOTE : RST3 14 6 MJD3055T4
RST OUTL

1
1. Non-inverting Configuration R136 220R 1 Q14 Q17
2. Inverting Configuration SUD50P08-25L-E3 GATE_Y_TOP_GND
DNP

3
ISO5852
TP24
R162 DNP
R172
0R D48
2.2R R137 R237 3

1
C A
10R 0R DNP
SK310A-LTP
R138 0R 1 2 GATE_Y_TOP
R173 R183 DNP
0R 2.2R QPC02SXGN-RC C71
J22 10nF
NOTE :

3
R139 220R 3. DNP While testingwith twistedpair
1 Q16
DNP MJD2955T4 Q15 R238
SUD40N08-16-E3 0R

2
DNP
J24
QPC02SXGN-RC
+15V Y_BOT
VEE_Y GATE_Y_TOP_GND 2 1 GATE_Y_TOP_RTN

R239 3
0R DNP
3V3 U22 C60
C181 10uF C133
1µF 0.1µF
10R R215 15 5
VCC1 VCC2
GATE_Y_BOT_GND
C134 C135
0.1µF Gate Driver Bottom IGBT Y
1
9 3
4.7µF GND1 GND2 C182
16 J25
GND1 1µF C69
DNP C183 10uF C137 QPC02SXGN-RC
1 1µF 0.1µF
VEE2
IN+_Y_BOT 10 8 J26 TP5
IN+ VEE2
QPC02SXGN-RC
2

DGND VEE_Y_BOT 2 1 D49 D50

-8V Y_BOT R144

1
IN-_Y_BOT 11 2 A C A C GATE_Y_TOP_RTN
IN- DESAT
TP40 1k
GL41Y-E3/96 GL41Y-E3/96
R147

2
RDY4 12 7
RDY CLAMP

1
TP25 0R +15V Y_BOT D72 D51 C138 C139 J27

RB160M-60TR
200pF 100pF QPC02SXGN-RC
FLT4 13 4

A
FLT OUTH

MM3Z12VB
1

TP26 DNP

1
2

RST4 14 6 MJD3055T4
RST OUTL
1

R148 220R 1 Q18 Q21

SUD50P08-25L-E3 GATE_Y_BOT_GND
DNP
3

ISO5852 R240 3

R184 0R DNP
TP27
0R R185 1 2 GATE_Y_BOTTOM
2.2R DNP
D52 QPC02SXGN-RC
3V3
1

R149 10R C A J28 C142

DNP 10nF
2
R140 DNP SK310A-LTP
R187 R150
0R
R186 2.2R
R1411 IN+_Y_BOT 0R 0R R241
0R 0R
NOTE :
3

PWM_DRV_Y_BOT
2
R142 DNP 3. DNP While testingwith twistedpair
IN-_Y_BOT Q20
R151 220R 1 J30
0R 1 MJD2955T4 Q19 QPC02SXGN-RC
DNP R143 DNP SUD40N08-16-E3 GATE_Y_BOT_GND 2 1 GATE_Y_BOT_RTN
2

0R
R242 3

0R DNP
DGND
VEE_Y_BOT

Figure 119. Gate Driver Y

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+15V B

3V3 U24 C91

C184 10uF C144
1µF 0.1µF
10R R216 15 5
VCC1 VCC2
GATE_B_TOP_GND
C145 C146

1
4.7µF 0.1µF
9 3
3V3 GND1 GND2 C185 J31
16
DNP
2 DNP
GND1 1µF
C186
C94
10uF C148
QPC02SXGN-RC Gate Driver Top IGBT B
R155 1 1µF 0.1µF
VEE2 J32
0R IN+_B_TOP 10 8 TP6
IN+ VEE2 QPC02SXGN-RC

2
R156 1 VEE_B 2 1 D53 D54
IN+_B_TOP DGND
-8V B
R159

1
0R IN-_B_TOP 11 2 A C A C DC_POS
IN- DESAT
PWM_DRV_B_TOP TP41 1k
2
R157 IN-_B_TOP GL41Y-E3/96 GL41Y-E3/96

1
0R RDY5 12 7 R160 0R
1 RDY CLAMP

1
DNP R158 TP28 +15V B D55
D73 C150 J33
C149
0R RB160M-60TR 200pF 100pF QPC02SXGN-RC

MM3Z12VB
FLT5 13 4

A
FLT OUTH

1
TP29
DNP

2
DNP MJD3055T4
DGND
RST5 14 6 Q22 Q25
RST OUTL R163 220R 1 1

DS
1
G SUD50P08-25L-E3 GATE_B_TOP_GND
NOTE :

2
1. Non-inverting Configuration TP30
DNP
2. Inverting Configuration ISO5852 D56
R164 C A 3
R243

1
R188 R189
0R 2.2R 10R
SK310A-LTP 0R DNP
R165 0R 1 2 GATE_B_TOP
QPC02SXGN-RC
R191 DNP J34
R190 C153
0R 2.2R
10nF

NOTE :

3
DNP
3. DNP While testingwith twistedpair

2
R166 220R 1 Q24
R244
MJD2955
1T4 Q23

SD
G 0R
SUD40N08-16-E3

2
DNP

3
J36
QPC02SXGN-RC
VEE_B GATE_B_TOP_GND 2 1 GATE_B_TOP_RTN
+15V B_BOT
R245 3

0R DNP
C98
3V3 U26 C187 10uF C155
1µF 0.1µF
10R R217 15 5
VCC1 VCC2
GATE_B_BOT_GND
C156 C157
4.7µF 0.1µF 1
9 3
GND1 GND2 C188 J37
16 C101
DNP
GND1 1µF C189 10uF C159 QPC02SXGN-RC Gate Driver Bottom IGBT B
1 1µF 0.1µF
VEE2 J38
IN+_B_BOT 10 8 TP7
IN+ VEE2 QPC02SXGN-RC
2

DGND VEE_B_BOT 2 1 D57 D58

-8V B_BOT
R171

1
IN-_B_BOT 11 2 A C A C GATE_B_TOP_RTN
IN- DESAT
TP42 1k
GL41Y-E3/96 GL41Y-E3/96
R174

2
RDY6 12 7

C
RDY CLAMP

1
TP31 0R +15V B_BOT D74 D59 C160 C161 J39

RB160M-60TR
200pF 100pF QPC02SXGN-RC
FLT6 13 4

MM3Z12VB
FLT OUTH
1

A
TP32 DNP
2

1
MJD3055T4
RST6 14 6 Q29
RST OUTL R175 220R 1
1

Q26 SUD50P08-25L-E3 GATE_B_BOT_GND

DNP
3

TP33
ISO5852 DNP
D60 R246 3
R192 R176 C A 0R
1

3V3 R193 DNP

0R 2.2R 10R
DNP
SK310A-LTP 1 2 GATE_B_BOTTOM
2
R167 R177 0R
QPC02SXGN-RC
0R J40 C164
R1681 DNP 10nF
IN+_B_BOT R195
0R 2.2R
PWM_DRV_B_BOT
R169 2 R194
IN-_B_BOT R247
0R NOTE :
3

0R 1 0R 3. DNP While testingwith twistedpair

DNP R170 Q28
R178 220R 1
0R MJD2955T4 Q27 J42
DNP
DNP SUD40N08-16-E3 QPC02SXGN-RC
GATE_B_BOT_GND 2 1 GATE_B_BOT_RTN
2

DGND R248 3
VEE_B_BOT 0R DNP

Figure 120. Gate Driver B

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Gate Driver Brake IGBT

+15V B_BOT

C104
3V3 U11 C190 10uF C62
1µF 0.1µF
10R R218 15 5
VCC1 VCC2
GATE_B_BOT_GND
C63 C65

1
0.1µF 9 3
4.7µF GND1 GND2 C191 C192 C107 C67 J11
16
GND1 1µF 10uF QPC02SXGN-RC
1µF 0.1µF
1
VEE2
IN+_BRAKE 10 8 J12 TP3
IN+ VEE2

2
VEE_BRAKE 2 1
DGND -8V B_BOT D10 D62
QPC02SXGN-RC R59

1
IN-_BRAKE 11 2 A C A C BRAKE
IN DESAT
TP43 1k
GL41Y-E3/96 GL41Y-E3/96
R54

1
RDY7 12 7

C
RDY CLAMP

1
TP34 0R D75 D39 C74 C73 J14

RB160M-60TR
R55 200pF 100pF QPC02SXGN-RC
FLT7 13 4

MM3Z12VB
FLT OUTH

A
TP35 47R DNP

2
RST7 14 6
RST OUTL

1
GATE_B_BOT_GND

ISO5852

GATE_BRAKE

R58
NOTE :
47R 3. DNP While testingwith twistedpair

3V3
DNP J18
2 QPC02SXGN-RC
R117 GATE_B_BOT_GND 2 1
0R
R118 1 IN+_BRAKE R251 0R
0R DNP
3
PWM_DRV_BRAKER
R119 2
IN-_BRAKE
0R 1
DNP R120
PGND
0R

DGND

Figure 121. Brake Drive

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Ready Indication RST1

RST2 Reset Control

3V3 RST3
3V3
RST4 R51 RST

A
RST
0R
D7 RST5
R64 GREEN

C
10K LTST-C170GKT RST6

RDY1 R47 RST7

120 Ohm
RDY2
SMPS Power Rails LED indications
RDY3 LTST-C170GKT

RDY4 RDY R50 Q3A 1.3K R108 D27A C GATE_R_TOP_GND

BC847BPN,115 +15V R
20K GREEN
RDY5
620 Ohm R109 D28C A GATE_R_TOP_GND
-8V R
GREEN
RDY6
1.3K R110 D29A C GATE_Y_TOP_GND
+15V Y
RDY7 GREEN
620 Ohm R111 D30C A GATE_Y_TOP_GND
-8V Y
DGND
GREEN

1.3K R112 D31A C GATE_B_TOP_GND

+15V B
GREEN
620 Ohm R113 D32C A GATE_B_TOP_GND
-8V B
GREEN
Fault Indication +15V R_BOT
1.3K R1 D33
A C GATE_R_BOT_GND
GREEN
620 Ohm R2 D34
C A GATE_R_BOT_GND
-8V R_BOT
GREEN
1.3K R3 D81
A C GATE_Y_BOT_GND
+15V Y_BOT
GREEN
3V3
620 Ohm R4 D82
C A GATE_Y_BOT_GND
-8V Y_BOT
GREEN
1.3K R5 D83
A C GATE_B_BOT_GND
3V3 +15V B_BOT
R65 GREEN
10K 620 Ohm R6 D84
C A GATE_B_BOT_GND
-8V B_BOT
GREEN

FLT1 2.37K R152 D35

A C
+24V
GREEN
FLT2 R53 Q3B
FLT 300 Ohm R153 D36
A C
BC847BPN,115 +5V DGND
20K GREEN
FLT3
120 Ohm R154 D37
A C
3V3 LTST-C170GKT
FLT4 GREEN
A 1.3K R116 D38
A C
FLT5 D8 +15V
LTST-C170EKT GREEN
C

FLT6 RED
R52
120 Ohm
FLT7 GND

DGND

Figure 122. LED Indications

64 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System TIDUA15A – June 2015 – Revised August 2015
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GATE_DRIVER_BUFFER

3V3
3V3
R106 3V3
10K U2
R12 3V3 R14
10K U3 1 14
PWM_EN 1OE VCC
1 14 R15 10R
PWM_EN 1OE VCC 2 13
10R PWM_Y_TOP 1A 4OE
0.01µF
2 13
PWM_R_TOP 1A 4OE 3 12 C34
0.01µF PWM_DRV_Y_TOP 1Y 4A PWM_R_BOT
3 12 C68
PWM_DRV_R_TOP 1Y 4A 4 11

R20
2OE 4Y PWM_DRV_R_BOT DGND

R16
4 11

R17
2OE 4Y 5 10
DGND 2A 3OE
5 10
2A 3OE 6 9

10K
2Y 3A

10K
6 9

10K
2Y 3A 7 8
GND 3Y
7 8
GND 3Y SN74ALVC125PW
DGND DGND
SN74ALVC125PW DGND
DGND DGND
DGND

3V3

R18 3V3
3V3 10K U4
U5 1 14 R21
R22 PWM_EN 1OE VCC
1 14 10R
1OE VCC
3V3 10R 2 13
PWM_B_TOP 1A 4OE
2 13 0.01µF
DGND 1A 4OE PWM_EN
0.01µF 3 12 C195
R19 PWM_DRV_B_TOP 1Y 4A PWM_Y_BOT
3 12 C70
10K 1Y 4A FAN_DRV
4 11

R23
2OE 4Y PWM_DRV_Y_BOT DGND
4 11

R24
PWM_EN 2OE 4Y FAN_DRV_BUFFER DGND 5 10
2A 3OE
5 10
BRAKER_ON 2A 3OE
6 9

10K
2Y 3A
6 9

10K
PWM_DRV_BRAKER 2Y 3A PWM_B_BOT
7 8
GND 3Y
R27

7 8
GND 3Y PWM_DRV_B_BOT
SN74ALVC125PW
R25
SN74ALVC125PW DGND DGND
DGND
DGND R26
10K

10K
10K

DGND
DGND DGND

Figure 123. Gate Driver Buffer

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PWM_R_TOP R68 10R

PWM_R_TOP

C76
0.01µF

DGND
PWM_R_BOT R69 10R
PWM_R_BOT

C77 CN6
0.01µF
DGND
20 1

19 2 BYPASS_RELAY
DGND
PWM_Y_TOP R70 10R R74
PWM_Y_TOP 18 3 BRAKER_ON
10R
C82
C78 17 4 0.01µF
0.01µF
16 5
DGND
15 6
DGND
R9 10R
14 7 FAN_DRV
PWM_Y_BOT R71 10R
PWM_Y_BOT
R10 10R HI_PWM
13 8 HI_PWM
C24
C79 R11 10R LI_PWM 0.01µF
0.01µF 12 9 LI_PWM
C26
11 10 1.5nF
C27
1.5nF DGND
DGND PPPC102LFBN-RC
PWM_B_TOP R72 10R DGND
PWM_B_TOP

From Launch Pad

C80 DGND
0.01µF
Launch Pad Connector J6 & J2
DGND

PWM_B_BOT R73 10R

PWM_B_BOT

C81
0.01µF

DGND

3V3 +5V

R8 R13
CN9 0R
0R
C169 10uF C168 10uF
20 1
DGND
19 2
DGND
PWM_EN 18 3
FLT
17 4
RDY
16 5

15 6
3V3
RST DC_BUS_SENSE_NEG
14 7
DC_BUS_SENSE_POS R75
13 8 10K
NTC_1
12 9

11 10
C196
0.01µF
PPPC102LFBN-RC

Launch Pad Connector J1 & J5

DGND

Figure 124. Board-to-Board Connections

66 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System TIDUA15A – June 2015 – Revised August 2015
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DC BUS VOLTAGE SENSING

+5V_ISO
3V3
C166 4.7µF
C83

0.1µF
0.1µF C84
U14
GND_ISO
DGND
R76 R77 R78 R79 R80 R81 R83 1 8
DC_POS VDD1 VDD2
1M 1M 1M 1M 1M 1M 10 Ohm 2 7 R84 0R DC_BUS_SENSE_POS
VINP VOUTP
R85
C85 C197
1K 3 6 R86 0R DC_BUS_SENSE_NEG
0.01µF VINN VOUTN 0.1µF
R87
4 5
10 Ohm GND1 GND2
R88
C86 C87
10K AMC1200SDUBR
10pF 10pF
DGND

GND_ISO
GND_ISO

+5V

C36 C37
10uF 0.1µF

+5V
U19 DGND D40 +5V_ISO
T1 6 A C R200 47 Ohm
4 3 1
GND D2

C
MBR0520LT3G C41
2 2 5 C43 C44 D63
VCC 10µF 0.1µF 10µF
D41 DNP MM3Z5V1B

A
5 1 3
GND D1 4 A C
Wurth Elektronik
SN6501DBVR 750313734 MBR0520LT3G GND_ISO

DGND

R123
0R

PGND GND_ISO

Figure 125. DC Bus Voltage Sensing

TIDUA15A – June 2015 – Revised August 2015 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System 67
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+15V R_BOT

C
D68
RB160M-60TR

A
C105 10µF C108 C106
C109 47uF
+15V 10µF
0.1µF

C
D76

R232 RB160M-60TR

A
0R
GATE_R_BOT_GND
Half Bridge converter : SMPS
D42 C111
C112 C113 47uF
C47 C49 A C D77 10µF 0.1µF
10µF 0.33 µF +24V RB160M-60TR
SK310A-LTP C A
-8V R_BOT

1
U16
DGND DGND
2 C88

VDD
HB D43 +15V R
R124 0R 7 3.3uF
HI_PWM HI C A
C110 U15
T2
HS 3 8

C
7
8
R125 0R 8 SK310A-LTP
LI_PWM LI 0.1µF D78
3 HSG R89 0R R90 17.8 ohm 2 RB160M-60TR
HO
9
1

A
5 4 HS 13
NC HS 6
C114 10µF C116 C115
5 C126
6 10 LSG LS1 5 10µF 47uF
NC LO R92
VSS
R91 17.8 ohm 4 14 0.1µF

C
0R Transformer_SMPS D79
UCC27211DPRT D44 750313734 RB160M-60TR
9

3
C A CSD88537ND C97

A
3.3uF
GATE_R_TOP_GND
SK310A-LTP
DGND C136
C143 C147 47uF
DGND DGND 10µF 0.1µF

C A
-8V R

D80
RB160M-60TR
0393570002
Molex D11 +24V
A C
1
2
S5B-E3/57T
P1
C89 C90
68µF 0.1µF
DGND

DGND

Figure 126. Gate Driver Power Supply (R Phase)

68 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System TIDUA15A – June 2015 – Revised August 2015
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+15V Y_BOT

C
D12
RB160M-60TR

A
C1 10µF
C4 C2
C5 47uF
10µF
0.1µF

C
D13
RB160M-60TR

A
GATE_Y_BOT_GND

C8
C9 C10 47uF
10µF 0.1µF
D14
C A
-8V Y_BOT
RB160M-60TR
+24V
+15V Y

T3
HS 3 8

C
C158 D15
3.3uF RB160M-60TR
9

A
13
C11 10µF C13 C12
LS2 5 C14 47uF
10µF
14 0.1µF

C
Transformer_SMPS D16
C165 750313734 RB160M-60TR
3.3uF

A
GATE_Y_TOP_GND

C15
C16 C17 47uF
DGND D17 10µF 0.1µF
RB160M-60TR
C A
-8V Y

+15V B_BOT

C
D18
RB160M-60TR

A
C18 10µF C20 C19
C21 47uF
10µF
0.1µF

C
D19
RB160M-60TR

A
GATE_B_BOT_GND

C22
C23 C92 47uF
10µF 0.1µF
D64
C A
-8V B_BOT
RB160M-60TR

+15V B
+24V
C

T4
HS 3 8 D65
RB160M-60TR
C167
A

3.3uF 9
13
C93 10µF C96 C95
LS3 5 C99 47uF
10µF
14 0.1µF
C

D66
Transformer_SMPS
750313734 RB160M-60TR
C170
3.3uF
A

GATE_B_TOP_GND

C100
C102 C103 47uF
DGND
10µF 0.1µF

C A
-8V B
D67
RB160M-60TR

Figure 127. Gate Driver Power Supply (Y and B Phase)

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Buck Converter 24V to 15V & 5V

+24V +24V
C117 C118

U17 TPS54286PWP
10µF 10µF

GND 1 14 GND
PVDD1 PVDD2
+15V C119 C120
R93 2 13 R94 +5V
L1 BOOT1 BOOT2 L2
100uH 0.5A 3.3R 3.3R 47uH 1.5A
0.033µF 3 12 0.033µF
SW1 SW2
+15V
C121 5 11 C122
EN1 BP

C
SK310A-LTP
C
C127 1nF 1nF
R97 6 10 R95 0R D20 C124
C123 D21 EN2 SEQ C125
51.1K GND DNP SK310A-LTP 10µF
4.7µF 4.7µF +5V 4.7µF
7 9 R96

A
R98 FB1 ILIM2

A
C128 10R
10R
DNP

PWPD
4 8 R100
R101 GND FB2 R99 4.7µF
C30 20K
2.87K 0R
0.01µF
DNP

15
GND
DNP R102 GND
C32 3.83K
GND
0.01µF
GND

GND
GND
3.3V LDO
+5V 3V3

U18 LP38691DTX

3 1
VCC VOUT
GND

C129
C130
10µF
10µF
2

GND DGND

GND

Figure 128. Buck Converter 24 V to 15 V and 5 V

70 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System TIDUA15A – June 2015 – Revised August 2015
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Inrush Bypass Relay : Drive Circuit Fan Driver Circuit

+24V

CN10

C
D61 1
SK310A-LTP 2
PGND INRUSH_BYPASS

A
Fan

4
RL1

R182
HE1aN-P-DC24V-Y5
0R

5
6
+24V
R103

D
10R

C
Q4
D22 MFG_PN
C131 R179
SK310A-LTP FAN_DRV_BUFFER G CSD18531Q5A
10µF FAN_DRV_BUFFER
200 Ohm

A
DNP

S
R180
10K

C
R104 B Q5
BYPASS_RELAY PZT2222A
470R
DGND

E
DGND

Figure 129. Inrush Relay

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8.2 Bill of Materials

To download the bill of materials (BOM), see the design files at TIDA-00195.

8.3 Layer Plots

To download the layer plots, see the design files at TIDA-00195.

8.4 Altium Project

To download the Altium project files, see the design files at TIDA-00195.

8.5 Gerber Files

To download the Gerber files, see the design files at TIDA-00195.

8.6 Assembly Drawings

To download the assembly drawings, see the design files at TIDA-00195.

72 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System TIDUA15A – June 2015 – Revised August 2015
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9 References
1. IEEE, Analytical calculation of the RMS current stress on the DC-link capacitor of voltage-PWM
converter systems, Kolar, J.W.; ETH Zurich, Power Electron. Syst. Lab., Zurich; Round, S.D., July
2006

10 Terminology

PWM— Pulse Width Modulation

LaunchPad— All reference to LaunchPad refers to InstaSPIN-FOC enabled C2000 LaunchPads
CFM— Cubic Feet per Minute
MCU— Microcontroller unit
FETs, MOSFETs— Metal–oxide–semiconductor field-effect transistor
IGBT— Insulated Bipolar Gate Transistor
ESD— Electro Static Discharge
EFT— Electrical Fast Transients
RPM— Rotation per Minute
RMS— Root Mean Square

11 Acknowledgments
The authors would like to thank Kamat Anant and Baranwal Shailendra (Industrial Interface Business unit
at TI) for their technical contributions to this design.

12 About the Authors

KRISTEN MOGENSEN is a system engineer in the Industrial Systems–Motor Drive team at Texas
Instruments, responsible for developing reference designs for industrial drives.
N. NAVANEETH KUMAR is a systems architect at Texas Instruments, where he is responsible for
developing subsystem solutions for motor controls within Industrial Systems. N. Navaneeth brings to this
role his extensive experience in power electronics, EMC, analog, and mixed signal designs. He has
system-level product design experience in drives, solar inverters, UPS, and protection relays. N.
Navaneeth earned his Bachelor of Electronics and Communication Engineering from Bharathiar
University, India and his Master of Science in Electronic Product Development from Bolton University, UK.

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Revision History

Changes from Original (June 2015) to A Revision ......................................................................................................... Page

• Added Note under Section 7.13 ....................................................................................................... 46

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

74 Revision History TIDUA15A – June 2015 – Revised August 2015

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