Sequential Circuit Design 10.1 Introduction Chapter 9 addressed combinational circuits in which the oupat is function ofthe curent inputs Ths chapeerdlscowes equential eects in which the outpot depeads on peviout aswell ax curtent inputs; uch Gucuts areal to have sof. F Pipelines are to important examples of aequeatel Cret, Sequential Greate are unually designed with flip-flops or latches, which ae some~ times called memory elements, that hold data called fken.The purpose of these elements is not really memory instead, ita to enforce ecquence, to ditnguish the arrest token fora the previous or next token. Therefore, we wil ell them sequencing elements [HarvsO1a} Without sequencing clement, the next token might catch up with the previous tokzn, getting both. Sequencing clements delay tokzns that arrive too ead, preventing theme From catching up with previous token, Unfortunatly, they inevitably ad some delay to tokens that ae already eritial, decreasing the performance ofthe system. This extra delay is called sequencing overhead ‘This chaptcr considers sequencing for both static and dynamic crate. Static iris refer to gates that have no dock input, such as complementary CMOS, peado-n MOS, or pis tractor ogi: Dynamic ircts refer to gates that havea clock input, especialy dom Iho log. To complicate terminology, sequencing clroenta thewacic ean be either Haticor domi. A sequencing cement with ttc rage exploys dome gor of oeback to cain its output value indefinitely An element with dynamic storage generally tntins ts value a5 charge on a capacitor that will leak away if not refreshed for along period of time. The choles of sae or dane for gates and foe seajuencingelroenta can be independent Sections 102-104 explore sequencing elements for static creuits, particularly fip- flops, 2-—phase transparent latches, and pulsed latches, Section 105 delves into a varity of wrapt to sequence dynaraic cui. A periodic clock is commonly tied to indicate the tne ing of cquence. Section 10.6 deacibes how external gma can be eyachvonized fo the clock and analyze the nhs of eynchronize hue. Wave pipaiing is iscused in See tion 107. Clock generation and distribution wil be examined farther in Section 13.4 “The choice of sequencing strategy is intimately ted to the design low that is being ured by an onganization. Thus, te important before departing on design direction to creure that all phases of design caphire,eyntheas and veidcation canbe accommodated. ‘This includes such pees ar cll ibraries (ae the latch o fip-flop crate and modes avaable!); cool sch as Ging analyzes (can timing closure be achicred eal) and automatic tet generation (an oelftest laments be inserted easly), ite state machines and 37510.3 Circuit Design of Latches and Flip-Fops EEN Example 10.7 If the ALU self-bypass path from Figure 10.6 can experience 50 ps of skew from one cycle to the next between flip-flops in the various ALUs, what is the minimum cycle time of the system? How much clock skew can the system have before hold-time fail~ SOLUTION: According to EQ (10.12), the eycle time should inerease by 50 ps to 1202 ps. “The maximum skew for which the system can operate correctly at any cycle time is a= fold * fag = 45~ (10) +75 = 130 ps. Pulsed latches can tolerate an amount of skew proportional to the pulse width, Ifthe pulse is wide enough, the skew will not increase the sequencing overhead because the data can arrive while the latch is transparent. If the pulse is narrow, skew can degrade perfor mance. Again, skew effectively increases the hold time and reduces the amount of time available for borrowing (see Exercise 10.7) fe 5, = ag yay Su Fae) (10.17) agora eT (10.18) Sona S fps -( benp * awn) (10.19) In summary, systems with hard edges (e.g. flip-flops) subtract clock skew from the time available for useful computation. Systems with softer edges (e.g. latches) take advantage of the window of transparency to tolerate some clock skew without increasing the sequencing overhead. Clock skew will be addressed further in Section 13.4. In particular, different amounts of skew can be budgeted for min-delay and max-delay checks. More- ‘over, nearby sequential elements are likely to see less skew than elements on opposite cor ners of the chip. Current automated place & route tools spend considerable effort to ‘model clock delays and insert buffer elements to minimize clock skew, but skew is a grow- ing problem for systems with aggressive cycle times. 10.3 Circuit Design of Latches and Flip-Flops Conventional CMOS latches are built using pass transistors or trstate buffers to pass the data while the latch is transparent and feedback to hold the data while the latch is opaque. ‘We begin by exploring circuit designs for basic latches, then build on them to produce flip-flops and pulsed latches. Many latches accept reset and/or enable inputs. Itis also pos- sible to build logic functions into the latches to reduce the sequencing overhead. ‘A number of alternative latch and flip-flop structures have been used in commercial designs. The True Single Phase Clocking (TSPC) technique uses a single clock with no inversions to simplify clock distribution, The Klass Semidynamic Flip-Flop (SDFF) is a fast flip-flop using a domino-style input stage. Differential lip-fops are good for certain applications, Each of these alternatives are described and compared,Chapter 10 Sequential Circuit Design @ @ @ 0 w FIGURE 10.17 Transparent latches 10.3.1 Conventional CMOS Latches Figure 10.17(a) shows a very simple transparent latch built from a single transistor. It is compact and fast but suffers four imitations. The output does not swing ftom rail-to-rail {ie., from GND to Vpp)s it never rises above Vp ~ V>The ourput is also dynamig, in other words, the output floats when the latch is opaque. Ift lots long enough, it can be disturbed by leakage (see Section 9.3.3). D drives the diffusion input of a pass transistor directly, leading to potential noise issues (see Section 9.3.9) and making the delay harder to model with static timing analyzers. Finally, the stare node is expored, so noise on the output can corrupt the state. The remainder of the figures illustrate improved latches using more transistors to achieve more robust operation Figure 10.17(b) uses a CMOS trans: T ix 1 otros of>eta mission gate in place of the single nMOS pass transistor to offer rail-to-rail output swvings It requires a complementary clock 6, which can be provided as an additional input or locally generated from @ through an pa 3 of >the Q inverter, Figure 10.17(c) adds an output 5 TY Jnverter so that the state node Xs isolated Léy ' from noise on the output. Of course, this a creates an inverting latch. Figure 10.17(d) ® t also behaves as an inverting latch with 2 buffered input but unbuffered output. As + qos discussed in Section 9.2.5.1, the inverter fol i lowed by a transmission gate is essentially Ths ‘Tightly lower logical effort becnase the out bk put is driven by both transistors of the trans mission gate in parallel, Figure 10.17(6) and wn) 3 (d) are both fast dynamic latches. Th adem process, sobhneshold les wn age is lange enough that dynamic nodes Pe retain their values for only shore time, specially tthe high temperatore and vole. ® age encountered daring burnin vest There . fore, practical latches need tobe setae, ea adding feedback to prevent the output from x floating, as shown in Figure 10.17(c). When the clock is 1 the input eanamisvion gate is ON; the feedback estates OF an the larch in eransparent When the clock sO, the inpot transmission gate turns OFF However the fcdback wistatetatns ON, J holding se the correct level, Figure 10.17(£) adds an input inverter so the input ina transistor gate rather than unbuffered10.3 Circuit Design of Latches and Flip-Flops EERIE diffusion, Unfortunately, both (e) and (P) reintroduced output noise sensitivity: A large noise spike on the output ean propagate backward through the feedback gates and corrupt the state node X. Figure 10.17(g) is a robust transparent latch that addeesses all of the deficiencies mentioned so far: The latch is static, all nodes swing rail-to-rail, the state noise is isolated from output noise, and the input drives transistor gates rather than diffusion. Such a latch is widely used in standard cell applications including the Artisan standard cell library [Artisan02]. It is recommended for al but the most performance- or area-critical designs Tn semicustom datapath applications where input noise can be better controlled, the inverting latch of Figure 10.17(h) may be preferable because it is faster and more compact. andard datapath latch (Karnik01]. Figure 10.17(3) shows the jamé latch, a vasiation of Figure 10.17(g) that reduces the clock load and saves two transistors by using a weak feedback inverter in place ofthe trstate. This requires careful circuit design to ensure that the tristate is strong enough to overpower the feedback inverter in all pro- cess comers. Figure 10.17(j) shows another jamb latch comamonly used in register files and Field Programmable Gate Array (FPGA) cells. Many such latches read out onto a single Day wite and only one latch is enabled at any given time with its RD signal. The Ttanium 2 processor uses the latch shown in Figure 10.17(k) [NaffzigerO2]. In the state Feedback, the pulldown stack is elocked, but the pullup is a weak pMOS transistor. Therefore, the gate driving the input must be strong enough to overcome the feedback. The Itanium 2 cell library also contains a similar latch with an additional input inverter to butler the input when the previous gate is too weak or far away. With the input inverter, the latch ean 4 be viewed as a cross between the designs shown in (g) and FAI Tntel uses this a8 a (i). Some latches add one more inverter to provide both true o4 a td complementary ourputs chee (4 ‘The dynamic latch of Figure 10.17(d) ean also be Ly drawn as a clocked tristate, as shown in Figure 10.18(a) ° v Such a form is sometimes called clocked CMOS (C?MOS) @ [Sweuki73]. The conventional form using the inverter and FIGURE 10.18 C2MOS Latch tranomission gates slightly faster because the output 8 den throug the nMOS and pMOS working inp (C2MOS is slightly smaller because it eliminates two con- ; ’ tacts Figure 10-180) shows another frm of the Witte thatnvapthedtaand decker slope eqs So AD So Poa dent but eleetsaly inferior beease toggling D while the F F Itch page can cause charge sharing nose on the Out 7 ; put node Suki73 ‘Allo the latches shown so fir are wansparent while is high They ean be converted to aceve-low latches by sap ping @and § x ¢ + A pa > @ 10.3.2 Conventional CMOS Flip-Flops Tr ° r i] ie Figure 10.19(a) shows a dynamic inverting fip-flop built from a pair of back-to-back dynamic latches [Suzuki73] Either the frst or the last inverter can be removed to reduce 3 delay at the expense of greater noise sensitivity on the) unbuffered input or output. Figure 10.19(b) adds feedback FIGURE 10.19 Flip. oosChapter 10 ‘Sequential Circuit Design and another inverter to produce a noninverting static Bip-flop. The PowerPC 603 micro- processor datapath used this flip-flop design without the input inverter or Q output [Gerosa94], Most standard cell libraries employ this design because it is simple, robust, compact, and energy-efficient [Stojanovic99]. However, some ofthe alternatives deseribed later ae faster Flip-flops usually take a single clock signal ¢ and locally generate its complement @.1F the clock rise/fall time is very slow it is possible that both the clock and its complement will simultaneously be at intermediate voltages, making both latches transparent and increasing the flip-flop hold time. In ASIC standaed eell libraries (such as the Artisan library), the elock is both complemented and buffered in the flip-flop cell to sharpen up the edge rates at the expense of more inverters and elock loading. However, the clock load should be kept as small as possible because it has an activity factor of 1 and thus accounts for much of the power consumption in the fip-flop. Recall that the Rip-flop also has a potential internal race condition between the two latches. This race can be exacerbated by skew between the clock and its complement caused by the delay of the inverter. Figure 10.20(a) redraws Figure 10.19(a) with a built-in clock inverter. When @ fills, both the clock and its complement are momentarily low as shown in Figure 10.20(b), turning on the clocked pMOS transistors in both transmission gates. Ifthe skew (ie, inverter delay) is too large, the data can sneak through both latches on the falling clock edge, leading to incorrect operation. Figure 10.20(c) shows a CMOS, ddynamie fip-Aop buile using C2MOS latches rather than inverters and transmission gates ki73]. Beeause each stage inverts, data passes through the nMOS stack of one latch \¢ PMOS of the other, so skew that turns on both clocked pMOS transistors is not & hazard. However, the fip-Aop is still susceptible to failure from very slow edge rates that turn both transistors partially ON. The same skew advantages apply even when an even number of inverting logic stages are placed between the latches; this technique is some- times called NO Rlce (NORA) [Gonclaves83]. In practice, most flip-flop designs care fully control the delay of the clock inverter so the transmission gate design is safe and slightly faster than C2MOS [Cha089]. All ofthese flip-flop designs still present potential min-delay problems between fip- flops, especially when there is litle or no logic between flops and the clock skew is large or ee ° ao fea i * t @ 20th pMOS momentary ON ‘ becuse of cok vere delay ” FIGURE 10.20 ‘Transmission gate ané NORA dyraricfiplops0.3 Circuit Design of Latches and Flip-Flops EXE poly anlyrd, For VLSI clas projects where careful lock a skew analysis is too much work and performance is less impor- e a tana reuonabeallematie to wea prof wo-phusenone oy Ng AG XN aL Pee cvrapping cock iaead ofthe clock ad it complemen ta o o shows in Figure 10.21. The flip-top captuse its input onthe % 3, Siig edge o By making the conovray age enough, the Coo wl wath dept ge kev, Flowsres te enor i T time is not used by logic, soit direct and sequencing overhead of the Aip-flop (see Exercise 10.8). fiGuRE 10.21 Fipefop with two-phase ronoverapning ‘The layout for the Hip-Alop is shown on the inside front cover cocks and is readily adapted to use a single clock. Observe how diffu- sion nodes are shared to reduce parasitic capacitance. 10.3.3 Pulsed Latches ‘A pulsed latch can be built from a conventional CMOS transparent latch driven by a brief clock pulse. Figure 10.22(a) shows a simple pulse generatos, sometimes ealled a clack chop ‘per or one-shot [HarsisO1a]. The pulsed latch is faster than a regular flip-flop because it involves a single latch sather than two and because it allows time borrowing. It can also consume less energy, although the pulse generator adds to the energy consumption (and is ideally shared across multiple pulsed latches for energy and area efficiency). The drawback is the increased hold time. SH @ Dodo | aie @ FIGURE 10.22 Pulse generatorsChapter 10 ‘Sequential Circuit Design “The Nafizigerpuled lath used on the Tanium 2 processor consists of the latch from Figure 10.17(k) driven by even shorter pulses produced by the generator of Figure 10.22(b) [Naflziger02]. This pulse generator uses a fiely slow (weak) inverter to produce & pulse with a nominal width of about one-sixth of the cycle (125 ps for 1.2 GFlz opera tion). When disabled, the internal node of the pulse generator floats high momentarily, bout no keeper is required because the duration is short, Of course, the enable signal has setup and hold requirements around the rising edge of the clock, as shown in Figure 10.22(¢). Figure 10.22(d) shows yet another pulse generator used on an NEC RISC processor [Kozu96] to produce substantially longer pulses. Ie inchades a built-in dynamic transmission~ gate latch to prevent the enable from glitching during the pulse. Many designers consider short pulses risky. The pulse generator should be carefully simulated across process commers and possible RC loads to ensure the pulse is not degraded too badly by process variation or routing, However, the Itanium 2 team found that the pulses could be used just as regular clocks as long as the pulse generator had adequate drive. The quad-core Itanium pulse generator selects between 1- and 3-inverter delay chains using a tansmission gate multiplexer [Stackhouse09]. The wider pulse offers more robust latch operation across process and environmental variability and permits more time borrowing, but increases the hold time. The multiplexer select is sfiware-programmable to fx problems discovered afer fabrication, “The Partovipuledlachin Figure 10.23 eliminates the need to distribute the pulse by building the pulse generator into the latch itself [Partovi96, Draper97]. The weale cross- coupled inverters in the dashed box staticize the circuit, although the latch is susceptible to back-driven output noise on Qor Qunless an extra inverter is used to buffer the output. The Partovi pulsed latch was used on the AMD K6 and Athlon [Golden99], but is slightly slower than a FIGURE 10.23 Paro pulsed itch simple latch [Naffzger02]. It was originally called an Ege Triggered Latch (ETL), but strictly speaking is a pulsed Jatch because it has a brief window of transparency 10.3.4 Resettable Latches and Flip-Flops Most practical sequencing elements require a reset signal to enter a known initial state on startup and ensure deterministic behavior. Figure 10.24 shows latches and flip-lops with reset inputs. There are two types of reset: synchronous and asynchronous. Asynchronous reset forces Q low immediately, while synchronous reset waits for the clock. Synchronous reset signals must be stable for a setup and hold time around the clock edge while asyn- chronous reset is characterized by a propagation delay from reset to output. Synchronous reset simply requires ANDing the input D with vee. Asynchronous reset requires gating both the data and the feedback to force the reset independent of the clock. The tristate NAND gate can be constructed from a NAND gate in series with a clocked transmission gate Settable latches and flip-flops force the output high instead of low: They ate similar to resettable elements of Figure 10.24 but replace NAND with NOR and vee with set. Fig- ure 10.25 shows a flip-flop combining both asynchronous set and reset10.3 Circuit Design of Latches and Flip-Fiops EXIM ‘symbol Tatch © reset ‘synchronous Reset ’ a o , ‘Asynchronous Reset mt 4 FIGURE 10.25 Flis-lap with asyichranous set and reset 10.3.5 Enabled Latches and Flip-Flops Sequencing elements also often accept an enable input. When enable en is low, the ele ment retains its state independently of the clock.’The enable can be performed with an input muleiplexer or clock garing, as shown in Figure 10.26. The input multiplexer feeds back the old state when the element is disabled. The multiplexer adds area and delay. Clock gating does not affect delay from the data input and che AND gate can be sharedCHAPTER 9 DYNAMIC LOGIC CIRCUITS 9.1. Introduction ‘A wide range of static combinational and sequential logic circuits was introduced in the previous chapters, Static logic circuits allow versatile implementation of logic functions based on static, or steady-state, behavior of simple nMOS or CMOS structures. In other words, all valid output levels in static gates are associated with steady-state operating points of the circuit in question. Hence, a typical static logic gate generates its output corresponding to the applied input voltages after a certain time delay, and itcan preserve its output level (or state) as long asthe power supply is provided. This approach, however, may require a large number of transistors to implement a function, and may cause & considerable time delay. In high-density, high-performance digital implementations where reduction of cireuit delay and silicon area is a major objective, dynamic logic circuits offer several significant advantages over static logic circuits. The operation of all dynamic logic gates depends on temporary (transient) storage of charge in parasitic node capacitances, instead of relying on steady-state circuit behavior. This operational property necessitates periodic updating of internal node voltage levels, since stored charge in a capacitor ly. Consequently, dynamic logic circuits require periodic clock signals in order to control charge refreshing, The capability of temporarily storing a state, ie. a voltage level, at a capacitive node allows us to implement very simplesequential circuits with memory functions. Also, the use of common clock signals throughout the system enables us to synchronize the operations of various circuit blocks. ‘Asaresult, dynamic circuittechniques end themselves wello synchronous logic design. Finally, the dynamic logic implementation of complex functions generally requires a sinaller silicon area than does the static logic implementation. As for the power consumption which increases with the parasitic capacitances, the dynamic circuit implementation ina smaller area will in many cases, consume less power than the static counterpart, despite its use of clock signals The following example presents the operation ofa dynamic D-latch circuit, which essentially consists of two inverters connected in cascade. Ths simple circuit illustrates ‘most ofthe basic operational concepts involved in dynamic cireuit design Example 9.1 Consider the dynamic D-latch circuit shown below. The circuit consists of two cascaded inverters and one nMOS pass transistor driving the input of the primary inverter stage. y ° ws > . a WO de ox oxy ‘We will see that the parasitic input capacitance C, of the primary inverter stage plays an important role in the dynamic operation of this circuit. The input pass transistor is being driven by the external periodic clock signal, as follows: * When the clock is high (CK = 1), the pass transistor turns on. The capacitor C, is either charged up, or charged down through the pass transistor MP, depending. onthe input (D) voltage level. The output (Q) assumes the same logic level asthe input. + When the clock is low (CK = 0), the pass transistor MP turns off, and the capacitor C, is isolated from the input D. Since there is no current path from the termediate node X to ether Vzyq of ground, the amount of charge stored in C, during the previous cycle determines the output voltage level Q. Itcaneasily be seen that this circuit performs the function of a simple D-latch. Infact, the transistor count can be reduced by removing the last inverter stage if the latch output ‘can be inverted. This option will be elaborated on in Section 9.2. The “hold” operation during the inactive clock cycle is accomplished by temporarily storing charge in the parasitic capacitance C, Correct operation of the circuit critically depends on how long 351 Dynamic Logic Circuits382 CHAPTER 9 4 sufficient amount of charge can be retained at node X, before the output state changes due to charge leakage. Therefore, the capacitive intermediate node X is also called a soft, rode. The nature of the soft node makes the dynamic circuits more vulnerable to the so- called single-event upsets (SEUs) caused by a-particle or cosmic ray hits in integrated cireuits. In the following, we will examine the circuit operation in more detail. Assume that the dynamic D-latch circuit is being operated with a power supply voltage of Vp)=5 V, and that the VTC of both inverters are identical, with Furthermore, the threshold voltage of the pass transistor MP is given as V;,,=0.8 V. During the active clock phase (CK = 1), assume that the input is equal to logic "I," ie. V. The pass transistor MP s conducting during this phase, andthe parasitic itance C, is charged up to a logic-high level. We recall thatthe ‘nMOS pass transistor is a poor conductor for logic "I," and its output voltage V, will be lower than Voyy by one threshold voltage: V, = 5.00.8 = 4.2 V. Stil, this voltage is clearly higher than the V,,of the first inverter, thus, the output voltage of the first inverter will be very close to Vp, = 0 V. Consequently, the output level Qof the secondary inverter ‘becomes @ logic "1," Vo = Vopr ‘Next, the clock signal goes to zero, and the pass transistor turns off. Initially, the logic-high level at node X is preserved through charge storage in C,. Thus, the output level @ also remains at logic "I." However, the voltage V, eventually starts to drop from its original level of 4.2 V because of charge leakage from the soft node. Itcan easily be seen that in order to keep the output node Q at logic "I," the voltage level at the intermediate node X cannot be allowed to drop lower than V,,,=2.9 V (once V, falls below this level, the input of the first inverter cannot be interpreted as a logic "I"). Thus, the inactive clock phase during which the clock signal is equal to zero can, at most, be as long as it takes for the intermediate voltage V, to drop from 4.2 V to 2.9 V, due to charge leakage. To avoid an erroneous output, the charge stored in C, must be restored, or refreshed, o its original level before V, reaches 2.9 V. ‘This example shows that the simple dynamic-charge storage principle employed in the D-latchcircutis quite feasible for preserving an output state during the inactive clock ‘Phase, assuming that the leakage currents responsible for draining the capacitance C, are relatively small. Inthe following, wewillexamine the charge-up nd charge-downevents for the sft-node capacitance C, in greater detail 9.2, Basic Principles of Pass Transistor Circults ‘The fundamental building block of nMOS dynamic logic circuits, consisting of an nMOS pass transistor driving the gate of another nMOS transistor, is shown in Fig. 9.1. Asalready discussed in Example 9.1, the pass transistor MP is driven by the periodic clock signal and acts as an access switch to either charge up or charge down the parasitic capacitance C,, depending on the input signal V,. Thus, the two possible operations when the clock signal is active (CK = 1) are the logic "1" transfer (charging up the capacitance C, toa logic-high level) and the logic “0” transfer (charging down the capacitance C, to a logic-low level). In either case, the output of the depletion-load nMOS inverter ‘obviously assumes a logic-low or a logic-high level, depending on the voltage V,. —o oy Figure 9.1. Thebasicbuilding block fornMOS dynamic logic, which consists of annMOS pass transistor driving the gate of another nMOS transistor. Notice thatthe pass transistor MP provides the only current path to the intermediate capacitive node (soft node) X. When the clock signal becomes inactive (CK =0), the pass transistor ceases to conduct and the charge stored in the parasitic capacitor C, continues to determine the output level ofthe inverter. In the following, we will first etamine the charge-up event. Logie "I" Transfer ‘Assume that the soft node voltage is equal to O intially, i, V,(t= 0) =0V. A logic "I" level is applied to the input terminal, which corresponds to Vs, = Voy = Vo Now, the clock signal atthe gate of the pass tr 0. It an be seen that the pass transistor MP starts to conduct as soon as the clock signal becomes active and that MP will operate in saturation throughout this cycle since Ving = Vos. Conse- quently, Vog> Vos~ Vy The circuit to be analyzed for the logic "1" transfer event can be simplified into an equivalent circuit as shown in Fig. 9.2. MP Mx Vin= Vou. = Figure 9.2. Equivalent circuit for the logic "1" transfer event. 353 Dynamic Logic Circuits354 CHAPTER 9 ‘The pass transistor MP operating in the saturation region starts to charge up the capacitor C, thus, av, 6, Tew Fa(Vo9-¥,- Vea)? 1) Note that the threshold voltage of the pass transistor is actually subject to substrate bias effect and therefore, depends on the voltage level V,. To simplify our analysis, we will neglect the substrate bias effect at this point. Integrating (9.1), we obtain fa-2Gph hy (Vao-Ve=Ven) 2G,| 1 i 2) hy (Wop Ve= Yew (9.3) (94) ‘The variation of the node voltage V, according to (9.4) is plotted as a function of time in Fig. 9.3. The voltage rises from its initial value of 0 V and approaches a limit value for large , but it cannot exceed its limit value of V,q, = (Vp ~ Vi.,). The pass transistor will turn off when V,= Ving Since at this point, its gate-to-source voltage will be equal to its threshold voltage. Therefore, the voltage at node X can never attain the full power supply voltage level of Vp during the logic "I" transfer. The actual value of the maximum possible voltage V,,,, at node X can be found by taking into account the substrate bias effect for MP. 5)° Figure 9.3, Variation of V, as a function of time during logic "1" transfer. ‘Thus, the voltage V, which is obtained at node X following a logic "1" transfer can be considerably lower than Vip. Also note that the rise time of the voltage V, will be underestimated ifthe zero-bias threshold voltage Vy is used in (9.3). In that case, the actual charge-up time will be longer than predicted by (9.3), because the drain current of the nMOS transistor is decreased due to the substrate bias effect. ‘The fact that the node voltage V, has an upper limit of Vage = (Vp ~ Vr) has a significant implication for circuit design. As an example, consider the following case in which a logic "1" at the input node (V,, = Vpp) is being transferred through a chain of cascaded pass transistors (Fig. 9.4). For simple analysis, we assume that intially all internal node voltages, V, through V,, are zet0. The first pass transistor M1 operates in saturation with Vpg, > Veg) ~ Vz Therefore, the voltage at node 1 cannot exceed the limit value Vpax, = (Vpo Vr). NOW, assuming thatthe pass transistors in this circuit are identical,"the second pass transistor M2 operates atthe saturation boundary. AS & result, the voltage at node 2 will be equal t0 Vigra = (Vpp ~ Vzqq) Itcan easily be seen that with Vpqy = Vig Vzqy =~ «the node voltage at the end of the pass transistor chain will become one threshold voltage lower than Vp» regardless of the number. of pass ‘transistors in the chain. Itcan be observed thatthe steady-state internal node voltages in this circuit are always one threshold voltage below V,yp, regardless ofthe initial voltages. uy_00-Vrat) yp _Wo0-Vrne) yyy _o0-Vrea) yg ts la gg ay Yoo Yoo Yoo Yoo Veo Vans ® Veo" Vins Figure 9.4. Node voltages in a passtransistor chain during the logic “1” transfer. 355 Dynamic Logic Circuits356 CHAPTER 9 Now consider a different case in which the output of each pass transistor drives the ‘ate of another pass transistor, as depicted in Fig. 95. Yoo Mj + Vnais = Yoo“ Vrat-Vra Vrs Yoo— Mj —— + Vinaxa= Von Vr * Vena om ae Vina *Voo "Vin Yoo Figure 9.5. Node voltages during the logic “I” transfer, when each pass transistor is driving another pass transistor. Here, the output ofthe frst pass transistor M1 can reach the limit Vag, = Vp Vy) This voltage drives the gate ofthe second pass amis, which also operates in the saturation region. Its gate-o-source voltage cannot exceed Vy. hence the upper limit for V, i found 88 Vaz = Vog= Vm ~ Vzqa:Itean be seen that in this cas, each stage causes a significant ios of voltage evel. The amount of voltage drop at each stage can be approximated more realistically by taking into account the corresponding substrate bias effet, which is different in all tages. Vam=Yron~1(\P¢rI* Yaar ~Y2r]) Yan2=Vron-1 (2 6r1*Vaur2 ~1P24r1) 06) ‘The preceding analysis helped us to examine important characteristics of the logic transfer event, Next, we will examine the charge-down event, which is also called a logic."0" transfer. Logic "0" Transfer ‘Assume that the softnode voltage Vis equal to a logic “I* level initially, ie, V,(t= 0) =Vnge= 9p Vp: lugic 0" levels appliod de input terial, which eoresponds | to Vj, =0.V. Now, te clock signal atthe gate ofthe pas transistor goes from O10 Vy | at # = 0. The pass transistor MP starts to conduct as soon as the clock signal becomes | active, and the direction of drain current flow through MP will be opposite to that during, the charge-up (logic "I" transfer) event. This means thatthe intermediate node X willnow correspond to the drain terminal of MP and that the input node will correspond to its source terminal. With Vos = Vpp and Vig = Vay it can be seen thatthe pass transistor ‘operates in the linear region throughout this cycle, since Vg < Vos ~ Vir‘The circuit to be analyzed for the logic "0" transfer event can be simplified into an 357 ‘equivalent circuit as shown in Fig. 9.6. As inthe logic "I" transfer case, the depletion- §—§ load nMOS inverter does not affect this event. Dynamic Logic Circuits Mp _ are] cK FT : I ‘Figure 9.6. Equivalent circuit for the logic "0" transfer event. ‘The pass transistor MP operating in the linear region discharges the parasitic capacitor Gy. follows: = cea (2(Vo0Vou) YH) on 26, av, by 2(Vo0~ Vin) Ye Ve? os Note thatthe source voltage of the nMOS pass transistor is equal to0 V during this event; hence, there is no substrate bias effect for MP (V,, = Vrp,)« But the intial condition V,{t= 0) = (Vpp~ Vz.) contains the threshold voltage with substrate bias effect, because the voltage V, is set during the preceding logic "I" transfer event, To simplify the expressions, we will use V,,, in the following. Integrating both sides of (9.8) yields He foo Vin), 2(Voo- Vr fae 2S 2(¥o0“ Via) _, 2(Voo= Vr Wk Noo-¥4x] 2(Voo— Vin) ~ 09) 9.10) “Ey(Voo~Vrn) ¥, ally, the fall-time expression for the node voltage V, can be obtained as (9.11)358 CHAPTER 9 ‘The variation of the node voltage V, according to (9.11) is plotted as a function of time in Fig. 9.7.Ttis seen that the voltage drops from its logic-high level of V,,,to0 V. Hence, unlike the charge-up case, the applied input voltage level (logic 0) can be transferred to the soft node without any modification during this event. ° Figure 9.7. Variation of V, a3 a function of time during logic transfer. ‘The fall time (7) for the soft-node voltage V, can be calculated from (9.11) as follows. First, define the two time points fgyq, and fyoq the times at which the node voltage is equal 10 0.9 Vig, ad 0.1 Vig Fespectively. These two time points can easily be found by using (9.11). ¢ (2-0.9)(Vop yb 00(Vbo= ; w(24) (9.12) mae) 08“ (op -¥ea) “bd 0.13) ‘The fall time of the soft-node voltage V, is by definition the difference between fog, and ‘y9q Which is found as pat =o — F908 ic; “Temples ies 0.14) =2.74- &, (Yoo —Vawn,Until this point, we have examined the transient charge-up and charge-down events which are responsible for logic "1" transfer and logic “O” transfer during the active clock phase, ie., when CK = 1. Now we will turn our attention to the storage of logic levels at the soft node X during the inactive clock cycle, ie., when CK = 0. ‘Charge Storage and Charge Leakage ‘As already discussed qualitatively inthe preceding section, the preservation of a correct level at the soft node during the inactive clock phase depends on preserving a sufficient amount of charge in C,, despite the leakage currents. To analyze the events during the inactive clock phase in more detail, consider the scenario shown in Fig. 9.8 ‘below. We will assume thatalogic-high voltage level has been transferred tothe soft node during the active clock phase and that now both the input voltage V,, and the clock are equal to 0 V. The charge stored in C, will gradually leak away, primarily due to the leakage currents associated withthe pass transistor. The gate current ofthe inverter driver transistor is negligible forall practical purposes. Figure 9.8. Charge leakage from the soft node. Figure 9.9 shows a simplified cross-section of the nMOS pass transistor, together withthe lumped node capacitance C,, We see thatthe leakage current responsible for draining the soft-node capacitance over time has two main components, namely, the subthreshold channel current and the reverse conduction current of the drain-substrate junction, Tratge = Lativei ur) * Hrve( MP) 15) Note that a certain portion ofthe total oft-node capacitance C, is due tothereverse biased. drain-substrate junction, which is also a function of the soft-node voltage V,. Other components of C,, which are primarily due to oxide-related parasitics, can be considered Constants. In our analysis, these constant capacitance components will be represented by Cp (Fig 9.10). Thus, we have toexpress the total charge stored inthe soft nodeas the sum of two main components, as follows. Q=0,(Vs)+Qn where Oy =CnVe (9.16) Gin = Cy + Cpoty + Catt 359 Dynamic Logic Circuits(CHAPTER 9 Me Vins tow Pivpe si iy ] Figure 9.9. _ Siroplified cross-section of the nMOS pass transistor, showing the leakage current ‘components responsible for draining the soft-node capacitance C,- Figure 9.10, Equivalent cicuit used for analyzing the charge leakage process. The total leakage current can be expressed as the time derivative of the total soft-node charge @. do Taatoge = . dt dt 17) 40MM) a¥e oa, er ie368 CHAPTER 9 Since its drain and source terminals are connected together, the dummy transistor simply acts as an MOS capacitor between V, and V,,. Although this circuit arrangement contains two additional transistors to achieve voltage bootstrapping, the resulting circuit- Performance improvement is usually well worth the extra silicon area used for the bootstrapping devices, a Example 9.3. ‘The transient operation of the simple bootstrap circuit shown in Fig. 9.13 is simulated using SPICE in the following. To provide the needed bootstrap capacitance Cysyu 8 dummy nMOS device with channel length L= 5 jm and channel width W=50 pm is used. ‘Transistor M1 has a (WIL) ratio of 2, while M2 and M3 each have a (W/L) ratio of 1. Voltage (V) ao oie? — 2010 = 4010 =o t0* = sot0* §~— 1.0108 Time (s) Er —————_-S 0.4, Synohrenoue Dynamie Cireult Techniqui Having examined the basic concepts associated with temporary storage of logic levels in nodes, we now turn our attention to digital circuit design techniques which take advantage of this simple yet effective principle. In the following, we will investigate different examples of synchronous dynamic circuits implemented using depletion-load nMOS, enhancement-load nMOS, and CMOS building blocksDynamic Pass Transistor Circuits Consider the generalized view of a multi-stage synchronous circuit shown in Fig. 9.14. ‘The circuit consists of cascaded combinational logic stages, which are interconnected through nMOS pass transistors. All inputs of each combinational logic block are driven by a single clock signal. Individual input capacitances are not shown in this figure for simplicity, but the operation of the circuit obviously depends on temporary charge storage in the parasitic input capacitances. ft com Uogie Figure 9.14, Multistage pass transistor logic driven by two nonoverlapping clocks. To drive the pass transistorsin this system, two nonoverlapping clock signals, 6, and 4, are used. The nonoverlapping property ofthe two clock signals guarantees that at any giventime point, only one ofthe twoclock signals can be active, as illustrated in Fig. 9.15. ‘When clock ¢, is active, the input levels of Stage 1 (and also of Stage 3) are applied through the pass transistors, while the input capacitances of Stage 2 retain their previously setogic levels. During the next phase, when clock g is active, the input levels of Stage 2 will be applied through the pass transistors, while the input capacitances of Stage 1 and Stage 3 retain their logic levels. This allows us to incorporate the simple dynamic memory function at each stage input, and at the same time, to facilitate synchronous operation by controlling the signal flow in the circuit using the two periodic clock signals. This signal timing scheme is aso called two-phase clocking and is one of the most widely used timing strategies. By introducing the two-phase clocking scheme, we have not made any specific assumptions about the internal structure of the combinational logic stages. It will be seen that depletion-load nMOS, enhancement-load nMOS, or CMOS logic circuits can be used for implementing the combinational logic. Figure 9.16 shows. depletion-load dynamic shift register circuit, in which the input data are inverted once and transferred, or shifted into the next stage during each clock phase. 309 Dynamic Logic Circuits370 CHAPTER 9 os | pnase 1] Phase 2 i Period T (or 30) ‘igure 9.13. Nonoveriapping clock signals used for two-phase synchronous operation. = i " Cans SE Coutt Love rlr Figure 9.16. Three stages ofa depletion-load nMOS dynamic shift register circuit driven with two-phase clocking. ‘The operation of the shift register circuits a follows. During the active phase of 6, the input voltage level V, is transferred into the input capacitance C,,. Thus, the valid ‘output voltage level of the first stage is determined as the inverse of the current input during this cycle. When 9, becomes active during the next phase, the output voltage level ofthe first stage is transferred into the second stage input capacitance C,,,, and the valid ‘output voltage level ofthe second stage is determined. During the ative 9, phase, the first-stage input capacitance continues to retain its previous level via charge storage. ‘When 6, becomes active again, the original data bit written into the register during the Previous cycle is transferred into the third stage, and the frst stage can now accept the next data bitInthis circuit, the maximum clock frequency is determined by the signal propagation delay through one inverter stage. One half-period of the clock signal must be long enough toallow the input capacitance C,, to charge up or down, and the logic level to propagate to the output by charging C,,. Also notice thatthe logic-high input evel of each inverter stage in this circuit is one threshold voltage lower than the power supply voltage level. ‘The same operation principle used in the simple shift register circuit can easily be extended to synchronous complex logic. Figures 9.17 and 9.18 show a two-stage circuit example implemented using depletion-load nMOS complex logic gates. 4 & Figure 9.17. A .wo-stage synchronous complex logic circuit example, In a complex logic circuit such as the one shown in Fig. 9.18, we see that the signal ‘propagation delay of each stage may be different. Thus, in order to guarantee that correct logic levels are propagated during each active clock cycle, the half-period length of the ‘lock signal must be longer than the largest single-stage signal propagation delay found in the cireuit, =f LE ale | al-——t | | ‘Sage 3 — 4 Figure 9.18. Depletion-load nMOS implementation of synchronous complex logic. am Dynamic Logic ireuits372. CHAPTER 9 Now consider a different implementation ofthe simple shift register circuit, us enhancement-load nMOS inverters. One important difference is tha, instead of biasing the load transistors with a constant gate voltage, we apply the clock signal to the gate of the load transistor as well. Itcan be shown that the power dissipation and the silicon area can be reduced significantly by using this dynamic (clocked) load approach. Two variants of the dynamic enhancement-oad shift register will be examined in the following, both of which are driven by two non-overlapping clock signals. Figure 9.19 shows the first implementation, where in each stage the input pass transistor and the load transistor are driven by opposite clock phases, 6, and 6, BY RW. “RIFFIE FIT Figure 9.19. Enhancement-load dynamic shift register (ratioed logic). ‘When 9 is active, the input voltage level V,is transferred into the first-stage input capacitance C,,, through the pass transistor. In this phase, the enhancement-type nMOS load transistor ofthe first-stage inverter is not active yet. During the next phase (active 4), the load transistor is turned on. Since the input logic level is still being preserved in jay the output ofthe first inverter stage attains its valid logic level. At the same time, ‘the input pass transistor of the second stage is also turned on, which allows this newly determined output level to be transferred into the input capacitance Cy. of the second stage. When clock @, becomes active again, the valid output level” across Cy is determined, and transferred into C,,. Also, a new input level can be accepted (pipelined) into Cig during this phase. In this circuit, the valid low-output voltage level Vo, of each stage is strictly determined by the driver-to-load ratio, since the output pass transistor (input pass ‘transistor of next stage) turns on in phase with the load transistor. Therefore, this circuit arrangement is also called ratioed dynamic logic. The hasic operation principle can obviously be extended to arbitrary complex logic, as shown in Fig. 9.20. Since the power supply current flows only when the load devices are activated by the clock signal, the ‘overall power consumption of dynamic enhancement-load logic is generally lower than for depletion-load nMOS logic. ‘Next, consider the second dynamic enhancement-load shift register implementation where, in each stage, the input pass transistor and the load transistor are driven by the same clock phase (Fig. 9.21)